/dts-v1/; /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "qcom-ipq5018.dtsi" / { #address-cells = <0x2>; #size-cells = <0x2>; model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.6-C1"; compatible = "qcom,ipq5018-mp03.6-c1", "qcom,ipq5018"; interrupt-parent = <&intc>; aliases { sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ serial0 = &blsp1_uart1; serial1 = &blsp1_uart2; }; chosen { bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; #ifdef __IPQ_MEM_PROFILE_256_MB__ bootargs-append = " swiotlb=1"; #else bootargs-append = " swiotlb=1 coherent_pool=2M"; #endif stdout-path = "serial0"; ethernet0 = "/soc/dp1"; ethernet1 = "/soc/dp2"; }; reserved-memory { #ifdef __IPQ_MEM_PROFILE_256_MB__ /* 256 MB Profile * +=========+==============+========================+ * | | | | * | Region | Start Offset | Size | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | NSS | 0x40000000 | 8MB | * | | | | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | | | | * | | | | * | Linux | 0x40800000 | Depends on total memory | * | | | | * | | | | * | | | | * + | | | * +--------+--------------+-------------------------+ * | | | | * | uboot | 0x4A600000 | 4MB | * | | | | * +--------+--------------+-------------------------+ * | SBL | 0x4AA00000 | 1MB | * +--------+--------------+-------------------------+ * | smem | 0x4AB00000 | 1MB | * +--------+--------------+-------------------------+ * | | | | * | TZ | 0x4AC00000 | 4MB | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | | | | * | Q6 | 0x4B000000 | 23MB | * | | | | * | | | | * | | | | * +--------+--------------+-------------------------+ * | M3 Dump| 0x4C700000 | 1MB | * +--------+--------------+-------------------------+ * | QDSS | 0x4C800000 | 1MB | * +--------+--------------+-------------------------+ * | | | | * |QCN9000 | 0x4C900000 | 17MB | * | | | | * +--------+--------------+-------------------------+ * | | | | * | MHI1 | 0x4DA00000 | 16MB | * | | | | * +--------+--------------+-------------------------+ * | | * | Rest of the memory for Linux | * | | * +=================================================+ */ q6_region: wcnss@4b000000 { no-map; reg = <0x0 0x4b000000 0x0 0x01700000>; }; m3_dump@4c700000 { no-map; reg = <0x0 0x4C700000 0x0 0x100000>; }; q6_etr_region:q6_etr_dump@4c800000 { no-map; reg = <0x0 0x4c800000 0x0 0x100000>; }; qcn9000_pcie0@4c900000 { no-map; reg = <0x0 0x4C900000 0x0 0x01100000>; }; mhi_region1: dma_pool1@4da00000 { compatible = "shared-dma-pool"; no-map; reg = <0x0 0x4da00000 0x0 0x01000000>; }; #else /* 512 MB Profile * +=========+==============+========================+ * | | | | * | Region | Start Offset | Size | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | NSS | 0x40000000 | 16MB | * | | | | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | | | | * | | | | * | Linux | 0x41000000 | Depends on total memory | * | | | | * | | | | * | | | | * | | | | * +--------+--------------+-------------------------+ * | | | | * | uboot | 0x4A600000 | 4MB | * | | | | * +--------+--------------+-------------------------+ * | SBL | 0x4AA00000 | 1MB | * +--------+--------------+-------------------------+ * | smem | 0x4AB00000 | 1MB | * +--------+--------------+-------------------------+ * | | | | * | TZ | 0x4AC00000 | 4MB | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | | | | * | Q6 | 0x4B000000 | 24MB | * | | | | * | | | | * +--------+--------------+-------------------------+ * | M3 Dump| 0x4C800000 | 1MB | * +--------+--------------+-------------------------+ * | QDSS | 0x4C900000 | 1MB | * +--------+--------------+-------------------------+ * | caldb | 0x4CA00000 | 2MB | * +--------+--------------+-------------------------+ * | | | | * |QCN9000 | 0x4CC00000 | 30MB | * | | | | * +--------+--------------+-------------------------+ * | | | | * | MHI1 | 0x4EA00000 | 16MB | * | | | | * +--------+--------------+-------------------------+ * | | * | Rest of the memory for Linux | * | | * +=================================================+ */ q6_region: wcnss@4b000000 { no-map; reg = <0x0 0x4b000000 0x0 0x01800000>; }; m3_dump@4c800000 { no-map; reg = <0x0 0x4c800000 0x0 0x100000>; }; q6_etr_region:q6_etr_dump@4c900000 { no-map; reg = <0x0 0x4c900000 0x0 0x100000>; }; q6_caldb_region:q6_caldb_region@4ca00000 { no-map; reg = <0x0 0x4ca00000 0x0 0x200000>; }; qcn9000_pcie0@4cc00000 { no-map; reg = <0x0 0x4CC00000 0x0 0x01E00000>; }; mhi_region1: dma_pool1@4ea00000 { compatible = "shared-dma-pool"; no-map; reg = <0x0 0x4ea00000 0x0 0x01000000>; }; #endif }; soc { serial@78af000 { status = "ok"; }; qpic_bam: dma@7984000{ status = "ok"; }; nand: qpic-nand@79b0000 { pinctrl-0 = <&qspi_nand_pins>; pinctrl-names = "default"; status = "ok"; }; spi_0: spi@78b5000 { /* BLSP1 QUP0 */ pinctrl-0 = <&blsp0_spi_pins>; pinctrl-names = "default"; cs-select = <0>; status = "ok"; m25p80@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; compatible = "n25q128a11"; linux,modalias = "m25p80", "n25q128a11"; spi-max-frequency = <50000000>; use-default-sizes; }; }; mdio0: mdio@88000 { status = "ok"; #address-cells = <1>; #size-cells = <0>; ethernet-phy@0 { reg = <7>; }; }; mdio1: mdio@90000 { status = "ok"; #address-cells = <1>; #size-cells = <0>; pinctrl-0 = <&mdio1_pins>; pinctrl-names = "default"; phy-reset-gpio = <&tlmm 39 0>; ethernet-phy@0 { reg = <28>; }; }; ess-instance { num_devices = <0x1>; #address-cells = <1>; #size-cells = <0>; ess-switch@0x39c00000 { switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/ cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/ qcom,port_phyinfo { port@0 { port_id = <1>; phy_address = <7>; mdiobus = <&mdio0>; }; port@1 { port_id = <2>; phy_address = <0x1c>; mdiobus = <&mdio1>; port_mac_sel = "QGMAC_PORT"; }; }; led_source@0 { source = <0>; mode = "normal"; speed = "all"; blink_en = "enable"; active = "high"; }; }; }; wifi0: wifi@c000000 { status = "ok"; }; dp1 { device_type = "network"; compatible = "qcom,nss-dp"; clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>; clock-names = "nss-snoc-gmac-axi-clk"; qcom,id = <1>; reg = <0x39C00000 0x10000>; interrupts = ; qcom,mactype = <2>; qcom,link-poll = <1>; qcom,phy-mdio-addr = <7>; mdio-bus = <&mdio0>; local-mac-address = [000000000000]; phy-mode = "sgmii"; }; dp2 { device_type = "network"; compatible = "qcom,nss-dp"; clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>; clock-names = "nss-snoc-gmac-axi-clk"; qcom,id = <2>; reg = <0x39D00000 0x10000>; interrupts = ; qcom,mactype = <2>; qcom,link-poll = <1>; qcom,phy-mdio-addr = <28>; mdio-bus = <&mdio1>; local-mac-address = [000000000000]; phy-mode = "sgmii"; }; qcom,test@0 { status = "ok"; }; lpass: lpass@0xA000000{ status = "disabled"; }; pcm: pcm@0xA3C0000{ pinctrl-0 = <&audio_pins>; pinctrl-names = "default"; status = "disabled"; }; pcm_lb: pcm_lb@0 { status = "disabled"; }; }; thermal-zones { status = "ok"; }; }; &tlmm { pinctrl-0 = <&blsp0_uart_pins &pcie_sdx_gpio>; pinctrl-names = "default"; blsp0_uart_pins: uart_pins { blsp0_uart_rx_tx { pins = "gpio20", "gpio21"; function = "blsp0_uart0"; bias-disable; }; }; blsp0_spi_pins: blsp0_spi_pins { mux { pins = "gpio10", "gpio11", "gpio12", "gpio13"; function = "blsp0_spi"; drive-strength = <2>; bias-disable; }; }; qspi_nand_pins: qspi_nand_pins { qspi_clock { pins = "gpio9"; function = "qspi_clk"; drive-strength = <8>; bias-disable; }; qspi_cs { pins = "gpio8"; function = "qspi_cs"; drive-strength = <8>; bias-disable; }; qspi_data_0 { pins = "gpio7"; function = "qspi0"; drive-strength = <8>; bias-disable; }; qspi_data_1 { pins = "gpio6"; function = "qspi1"; drive-strength = <8>; bias-disable; }; qspi_data_2 { pins = "gpio5"; function = "qspi2"; drive-strength = <8>; bias-disable; }; qspi_data_3 { pins = "gpio4"; function = "qspi3"; drive-strength = <8>; bias-disable; }; }; mdio1_pins: mdio_pinmux { mux_0 { pins = "gpio36"; function = "mdc"; drive-strength = <8>; bias-pull-up; }; mux_1 { pins = "gpio37"; function = "mdio"; drive-strength = <8>; bias-pull-up; }; }; pcie_sdx_gpio: pcie_sdx_gpio { ap2mdm_err_ftl { pins = "gpio1"; function = "gpio"; drive-strength = <8>; bias-pull-down; }; sdx_pon_gpio { pins = "gpio26"; function = "gpio"; drive-strength = <8>; bias-pull-up; output-high; }; ap2mdm_gp_rst_n { pins = "gpio28"; function = "gpio"; drive-strength = <8>; output-high; }; }; ap2mdm_status: ap2mdm_status { pins = "gpio25"; function = "gpio"; drive-strength = <8>; bias-pull-up; output-high; }; mdm2ap_e911_status: mdm2ap_e911_status { pins = "gpio0"; drive-strength = <8>; bias-pull-down; }; pcie_wake_pins: pcie1_wake_gpio { pins = "gpio19"; function = "pcie1_wake"; drive-strength = <8>; bias-pull-up; }; audio_pins: audio_pinmux { mux_1 { pins = "gpio24"; function = "audio_rxbclk"; drive-strength = <8>; bias-pull-down; }; mux_2 { pins = "gpio25"; function = "audio_rxfsync"; drive-strength = <8>; bias-pull-down; }; mux_3 { pins = "gpio26"; function = "audio_rxd"; drive-strength = <8>; bias-pull-down; }; mux_4 { pins = "gpio27"; function = "audio_txmclk"; drive-strength = <8>; bias-pull-down; }; mux_5 { pins = "gpio28"; function = "audio_txbclk"; drive-strength = <8>; bias-pull-down; }; mux_6 { pins = "gpio29"; function = "audio_txfsync"; drive-strength = <8>; bias-pull-down; }; mux_7 { pins = "gpio30"; function = "audio_txd"; drive-strength = <8>; bias-pull-down; }; }; }; &usb3 { status = "ok"; device-power-gpio = <&tlmm 24 1>; }; &eud { status = "ok"; }; &pcie_x1 { interrupts-extended = <&intc GIC_SPI 111 IRQ_TYPE_NONE>, <&intc 0 416 IRQ_TYPE_NONE>, <&intc 0 417 IRQ_TYPE_NONE>, <&intc 0 418 IRQ_TYPE_NONE>, <&intc 0 419 IRQ_TYPE_NONE>, <&intc 0 420 IRQ_TYPE_NONE>, <&intc 0 421 IRQ_TYPE_NONE>, <&intc 0 422 IRQ_TYPE_NONE>, <&intc 0 423 IRQ_TYPE_NONE>, <&intc 0 424 IRQ_TYPE_NONE>, <&intc 0 425 IRQ_TYPE_NONE>, <&intc 0 426 IRQ_TYPE_NONE>, <&intc 0 427 IRQ_TYPE_NONE>, <&intc 0 428 IRQ_TYPE_NONE>, <&intc 0 429 IRQ_TYPE_NONE>, <&intc 0 430 IRQ_TYPE_NONE>, <&intc 0 431 IRQ_TYPE_NONE>, <&intc 0 432 IRQ_TYPE_NONE>, <&intc 0 433 IRQ_TYPE_NONE>, <&intc 0 434 IRQ_TYPE_NONE>, <&intc 0 435 IRQ_TYPE_NONE>, <&intc 0 436 IRQ_TYPE_NONE>, <&intc 0 437 IRQ_TYPE_NONE>, <&intc 0 438 IRQ_TYPE_NONE>, <&intc 0 439 IRQ_TYPE_NONE>, <&intc 0 440 IRQ_TYPE_NONE>, <&intc 0 441 IRQ_TYPE_NONE>, <&intc 0 442 IRQ_TYPE_NONE>, <&intc 0 443 IRQ_TYPE_NONE>, <&intc 0 444 IRQ_TYPE_NONE>, <&intc 0 445 IRQ_TYPE_NONE>, <&intc 0 446 IRQ_TYPE_NONE>, <&intc 0 447 IRQ_TYPE_NONE>, <&tlmm 19 0>, <&tlmm 0 0>; interrupt-names = "msi", "msi_0", "msi_1", "msi_2", "msi_3", "msi_4", "msi_5", "msi_6", "msi_7", "msi_8", "msi_9", "msi_10", "msi_11", "msi_12", "msi_13", "msi_14", "msi_15", "msi_16", "msi_17", "msi_18", "msi_19", "msi_20", "msi_21", "msi_22", "msi_23", "msi_24", "msi_25", "msi_26", "msi_27", "msi_28", "msi_29", "msi_30", "msi_31", "wake_gpio", "mdm2ap_e911"; pinctrl-0 = <&pcie_wake_pins &mdm2ap_e911_status>; e911-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; status = "ok"; perst-gpio = <&tlmm 18 1>; slot_id = <0>; }; &pcie_x2 { status = "ok"; perst-gpio = <&tlmm 15 1>; }; &dwc_0 { /delete-property/ #phy-cells; /delete-property/ phys; /delete-property/ phy-names; }; &hs_m31phy_0 { status = "ok"; }; &pcie_x1phy { status = "ok"; }; &pcie_x2phy { status = "ok"; }; &pcie_x1_rp { status = "ok"; #address-cells = <5>; #size-cells = <0>; aliases { mhi-netdev0 = &mhi_netdev_0; mhi_netdev2 = &mhi_netdev_2; }; mhi_0: qcom,mhi@0 { reg = <0 0 0 0 0 >; ap2mdm = <25>; mdm2ap = <23>; pinctrl-0 = <&ap2mdm_status>; pinctrl-names = "default"; /* controller specific configuration */ qcom,iommu-dma = "disabled"; /* mhi bus specific settings */ mhi,max-channels = <110>; mhi,timeout = <60000>; mhi,ssr-negotiate; mhi_channels: mhi_channels { #address-cells = <1>; #size-cells = <0>; mhi_chan@0 { reg = <0>; label = "LOOPBACK"; mhi,num-elements = <64>; mhi,event-ring = <2>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@1 { reg = <1>; label = "LOOPBACK"; mhi,num-elements = <64>; mhi,event-ring = <2>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@2 { reg = <2>; label = "SAHARA"; mhi,num-elements = <128>; mhi,event-ring = <1>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x2>; }; mhi_chan@3 { reg = <3>; label = "SAHARA"; mhi,num-elements = <128>; mhi,event-ring = <1>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x2>; }; mhi_chan@4 { reg = <4>; label = "DIAG"; mhi,num-elements = <64>; mhi,event-ring = <1>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@5 { reg = <5>; label = "DIAG"; mhi,num-elements = <64>; mhi,event-ring = <3>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@14 { reg = <14>; label = "QMI0"; mhi,num-elements = <64>; mhi,event-ring = <1>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@15 { reg = <15>; label = "QMI0"; mhi,num-elements = <64>; mhi,event-ring = <2>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@16 { reg = <16>; label = "QMI1"; mhi,num-elements = <64>; mhi,event-ring = <3>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@17 { reg = <17>; label = "QMI1"; mhi,num-elements = <64>; mhi,event-ring = <3>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@18 { reg = <18>; label = "IP_CTRL"; mhi,num-elements = <64>; mhi,event-ring = <1>; mhi,chan-dir = <1>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@19 { reg = <19>; label = "IP_CTRL"; mhi,num-elements = <64>; mhi,event-ring = <1>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; mhi,auto-queue; }; mhi_chan@20 { reg = <20>; label = "IPCR"; mhi,num-elements = <64>; mhi,event-ring = <2>; mhi,chan-dir = <1>; mhi,data-type = <1>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; mhi,auto-start; }; mhi_chan@21 { reg = <21>; label = "IPCR"; mhi,num-elements = <64>; mhi,event-ring = <2>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; mhi,auto-queue; mhi,auto-start; }; mhi_chan@46 { reg = <46>; label = "IP_SW0"; mhi,num-elements = <512>; mhi,event-ring = <4>; mhi,chan-dir = <1>; mhi,data-type = <1>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@47 { reg = <47>; label = "IP_SW0"; mhi,num-elements = <512>; mhi,event-ring = <5>; mhi,chan-dir = <2>; mhi,data-type = <4>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@100 { reg = <100>; label = "IP_HW0"; mhi,num-elements = <512>; mhi,event-ring = <6>; mhi,chan-dir = <1>; mhi,data-type = <1>; mhi,doorbell-mode = <3>; mhi,ee = <0x4>; mhi,db-mode-switch; }; mhi_chan@101 { reg = <101>; label = "IP_HW0"; mhi,num-elements = <512>; mhi,event-ring = <7>; mhi,chan-dir = <2>; mhi,data-type = <4>; mhi,doorbell-mode = <3>; mhi,ee = <0x4>; }; mhi_chan@102 { reg = <102>; label = "IP_HW_ADPL"; mhi,event-ring = <8>; mhi,chan-dir = <2>; mhi,data-type = <3>; mhi,ee = <0x4>; mhi,offload-chan; mhi,lpm-notify; }; mhi_chan@105 { reg = <105>; label = "RMNET_CTL"; mhi,num-elements = <128>; mhi,event-ring = <10>; mhi,chan-dir = <1>; mhi,data-type = <1>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; mhi_chan@106 { reg = <106>; label = "RMNET_CTL"; mhi,num-elements = <128>; mhi,event-ring = <11>; mhi,chan-dir = <2>; mhi,data-type = <0>; mhi,doorbell-mode = <2>; mhi,ee = <0x4>; }; }; mhi_events: mhi_events { #address-cells = <1>; #size-cells = <0>; mhi_event@0 { reg = <0>; mhi,num-elements = <32>; mhi,intmod = <1>; mhi,msi = <1>; mhi,priority = <1>; mhi,brstmode = <2>; mhi,data-type = <1>; }; mhi_event@1 { mhi,num-elements = <256>; mhi,intmod = <1>; mhi,msi = <2>; mhi,priority = <1>; mhi,brstmode = <2>; }; mhi_event@2 { mhi,num-elements = <256>; mhi,intmod = <1>; mhi,msi = <3>; mhi,priority = <1>; mhi,brstmode = <2>; }; mhi_event@3 { mhi,num-elements = <256>; mhi,intmod = <1>; mhi,msi = <4>; mhi,priority = <1>; mhi,brstmode = <2>; }; mhi_event@4 { mhi,num-elements = <1024>; mhi,intmod = <5>; mhi,msi = <5>; mhi,chan = <46>; mhi,priority = <1>; mhi,brstmode = <2>; }; mhi_event@5 { mhi,num-elements = <1024>; mhi,intmod = <5>; mhi,msi = <6>; mhi,chan = <47>; mhi,priority = <1>; mhi,brstmode = <2>; mhi,client-manage; }; mhi_event@6 { mhi,num-elements = <1024>; mhi,intmod = <5>; mhi,msi = <5>; mhi,chan = <100>; mhi,priority = <1>; mhi,brstmode = <3>; mhi,hw-ev; }; mhi_event@7 { mhi,num-elements = <1024>; mhi,intmod = <5>; mhi,msi = <6>; mhi,chan = <101>; mhi,priority = <1>; mhi,brstmode = <3>; mhi,client-manage; mhi,hw-ev; }; mhi_event@8 { mhi,num-elements = <0>; mhi,intmod = <0>; mhi,msi = <0>; mhi,chan = <102>; mhi,priority = <1>; mhi,brstmode = <3>; mhi,hw-ev; mhi,client-manage; mhi,offload; }; mhi_event@9 { mhi,num-elements = <1024>; mhi,intmod = <5>; mhi,msi = <7>; mhi,chan = <103>; mhi,priority = <1>; mhi,brstmode = <2>; mhi,hw-ev; }; mhi_event@10 { mhi,num-elements = <1024>; mhi,intmod = <1>; mhi,msi = <8>; mhi,chan = <105>; mhi,priority = <0>; mhi,brstmode = <2>; mhi,hw-ev; }; mhi_event@11 { mhi,num-elements = <1024>; mhi,intmod = <0>; mhi,msi = <9>; mhi,chan = <106>; mhi,priority = <0>; mhi,brstmode = <2>; mhi,hw-ev; }; mhi_event@12 { mhi,num-elements = <0>; mhi,intmod = <0>; mhi,msi = <0>; mhi,chan = <107>; mhi,priority = <1>; mhi,brstmode = <3>; mhi,hw-ev; mhi,client-manage; mhi,offload; }; mhi_event@13 { mhi,num-elements = <0>; mhi,intmod = <0>; mhi,msi = <0>; mhi,chan = <108>; mhi,priority = <1>; mhi,brstmode = <3>; mhi,hw-ev; mhi,client-manage; mhi,offload; }; }; mhi_devices: mhi_devices { #address-cells = <1>; #size-cells = <0>; mhi_netdev_0: mhi_rmnet@0 { reg = <0x0>; mhi,chan = "IP_HW0"; mhi,interface-name = "rmnet_mhi"; mhi,mru = <0x4000>; mhi,chain-skb; }; mhi_rmnet@1 { reg = <0x1>; mhi,chan = "IP_HW0_RSC"; mhi,mru = <0x8000>; mhi,rsc-parent = <&mhi_netdev_0>; }; mhi_netdev_2: mhi_rmnet@2 { reg = <0x2>; mhi,chan = "IP_SW0"; mhi,interface-name = "rmnet_mhi_sw"; mhi,mru = <0x4000>; mhi,disable-chain-skb; }; mhi_qrtr { mhi,chan = "IPCR"; qcom,net-id = <3>; }; }; }; }; &pcie_x2_rp { status = "ok"; #address-cells = <0x5>; #size-cells = <0x0>; mhi_1: qcom,mhi@1 { reg = <0 0 0 0 0 >; qrtr_instance_id = <0x20>; memory-region = <&mhi_region1>; }; }; &qfprom { status = "ok"; }; &tsens { status = "ok"; }; &qcom_q6v5_wcss { #ifdef __IPQ_MEM_PROFILE_256_MB__ memory-region = <&q6_region>, <&q6_etr_region>; #else memory-region = <&q6_region>, <&q6_etr_region>, <&q6_caldb_region>; #endif }; &qgic_msi_0 { status = "ok"; }; &wifi0 { /* IPQ5018 */ qcom,bdf-addr = <0x4BA00000 0x4BA00000 0x4BA00000 0x0 0x0>; qcom,caldb-addr = <0x4CA00000 0x4CA00000 0x0 0x0 0x0>; qcom,caldb-size = <0x200000>; qcom,board_id = <0x23>; status = "ok"; }; &wifi3 { /* QCN9000 6G */ compatible = "qcom,cnss-qcn9000"; board_id = <0xa0>; status = "ok"; };