/dts-v1/; /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "qcom-ipq807x-soc.dtsi" #include "qcom-ipq807x-hk-cpu.dtsi" / { #address-cells = <0x2>; #size-cells = <0x2>; model = "Qualcomm Technologies, Inc. IPQ807x-DB.HK02"; compatible = "qcom,ipq807x-db.hk02", "qcom,ipq807x"; qcom,msm-id = <0x143 0x0>; interrupt-parent = <&intc>; qcom,board-id = <0x8 0x0>; qcom,pmic-id = <0x0 0x0 0x0 0x0>; aliases { /* * Aliases as required by u-boot * to patch MAC addresses */ ethernet0 = "/soc/dp1"; ethernet1 = "/soc/dp2"; ethernet2 = "/soc/dp3"; ethernet3 = "/soc/dp4"; ethernet4 = "/soc/dp5"; ethernet5 = "/soc/dp6"; }; chosen { bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init"; #ifdef __IPQ_MEM_PROFILE_256_MB__ bootargs-append = " swiotlb=1"; #else bootargs-append = " swiotlb=1 coherent_pool=2M"; #endif }; }; &tlmm { mdio_pins: mdio_pinmux { mux_0 { pins = "gpio68"; function = "mdc"; drive-strength = <8>; bias-pull-up; }; mux_1 { pins = "gpio69"; function = "mdio"; drive-strength = <8>; bias-pull-up; }; mux_2 { pins = "gpio26"; function = "gpio"; bias-pull-up; }; }; uart_pins: uart_pins { mux { pins = "gpio23", "gpio24"; function = "blsp4_uart1"; drive-strength = <8>; bias-disable; }; }; i2c_0_pins: i2c_0_pinmux { mux { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; drive-strength = <8>; bias-disable; }; }; spi_0_pins: spi_0_pins { mux { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "blsp0_spi"; drive-strength = <8>; bias-disable; }; }; qpic_pins: qpic_pins { data_0 { pins = "gpio15"; function = "qpic_pad0"; drive-strength = <8>; bias-disable; }; data_1 { pins = "gpio12"; function = "qpic_pad1"; drive-strength = <8>; bias-disable; }; data_2 { pins = "gpio13"; function = "qpic_pad2"; drive-strength = <8>; bias-disable; }; data_3 { pins = "gpio14"; function = "qpic_pad3"; drive-strength = <8>; bias-disable; }; data_4 { pins = "gpio5"; function = "qpic_pad4"; drive-strength = <8>; bias-disable; }; data_5 { pins = "gpio6"; function = "qpic_pad5"; drive-strength = <8>; bias-disable; }; data_6 { pins = "gpio7"; function = "qpic_pad6"; drive-strength = <8>; bias-disable; }; data_7 { pins = "gpio8"; function = "qpic_pad7"; drive-strength = <8>; bias-disable; }; data_8 { pins = "gpio16"; function = "qpic_pad8"; drive-strength = <8>; bias-disable; }; qpic_pad { pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10", "gpio11", "gpio17"; function = "qpic_pad"; drive-strength = <8>; bias-disable; }; }; hsuart_pins: hsuart_pins { mux { pins = "gpio46", "gpio47", "gpio48", "gpio49"; function = "blsp2_uart"; drive-strength = <8>; bias-disable; }; }; uniphy_pins: uniphy_pinmux { mux { pins = "gpio60"; function = "rx2"; bias-disable; }; }; }; &soc { mdio@90000 { #address-cells = <0x1>; #size-cells = <0x0>; pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; phy-reset-gpio = <&tlmm 37 0 &tlmm 26 1>; compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio"; phy0: ethernet-phy@0 { reg = <0>; }; phy1: ethernet-phy@1 { reg = <1>; }; phy2: ethernet-phy@2 { reg = <2>; }; phy3: ethernet-phy@3 { reg = <3>; }; phy4: ethernet-phy@4 { compatible ="ethernet-phy-ieee802.3-c45"; reg = <15>; }; phy5: ethernet-phy@5 { reg = <28>; }; }; ess-switch@3a000000 { pinctrl-0 = <&uniphy_pins>; pinctrl-names = "default"; switch_cpu_bmp = <0x1>; /* cpu port bitmap */ switch_lan_bmp = <0x3e>; /* lan port bitmap */ switch_wan_bmp = <0x40>; /* wan port bitmap */ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/ switch_mac_mode2 = <0xc>; /* mac mode for uniphy instance2*/ bm_tick_mode = <0>; /* bm tick mode */ tm_tick_mode = <0>; /* tm tick mode */ qcom,port_phyinfo { port@0 { port_id = <1>; phy_address = <0>; }; port@1 { port_id = <2>; phy_address = <1>; }; port@2 { port_id = <3>; phy_address = <2>; }; port@3 { port_id = <4>; phy_address = <3>; }; port@4 { port_id = <5>; phy_address = <15>; ethernet-phy-ieee802.3-c45; }; port@5 { port_id = <6>; phy_address = <28>; port_mac_sel = "QGMAC_PORT"; }; }; port_scheduler_resource { port@0 { port_id = <0>; ucast_queue = <0 143>; mcast_queue = <256 271>; l0sp = <0 35>; l0cdrr = <0 47>; l0edrr = <0 47>; l1cdrr = <0 7>; l1edrr = <0 7>; }; port@1 { port_id = <1>; ucast_queue = <144 159>; mcast_queue = <272 275>; l0sp = <36 39>; l0cdrr = <48 63>; l0edrr = <48 63>; l1cdrr = <8 11>; l1edrr = <8 11>; }; port@2 { port_id = <2>; ucast_queue = <160 175>; mcast_queue = <276 279>; l0sp = <40 43>; l0cdrr = <64 79>; l0edrr = <64 79>; l1cdrr = <12 15>; l1edrr = <12 15>; }; port@3 { port_id = <3>; ucast_queue = <176 191>; mcast_queue = <280 283>; l0sp = <44 47>; l0cdrr = <80 95>; l0edrr = <80 95>; l1cdrr = <16 19>; l1edrr = <16 19>; }; port@4 { port_id = <4>; ucast_queue = <192 207>; mcast_queue = <284 287>; l0sp = <48 51>; l0cdrr = <96 111>; l0edrr = <96 111>; l1cdrr = <20 23>; l1edrr = <20 23>; }; port@5 { port_id = <5>; ucast_queue = <208 223>; mcast_queue = <288 291>; l0sp = <52 55>; l0cdrr = <112 127>; l0edrr = <112 127>; l1cdrr = <24 27>; l1edrr = <24 27>; }; port@6 { port_id = <6>; ucast_queue = <224 239>; mcast_queue = <292 295>; l0sp = <56 59>; l0cdrr = <128 143>; l0edrr = <128 143>; l1cdrr = <28 31>; l1edrr = <28 31>; }; port@7 { port_id = <7>; ucast_queue = <240 255>; mcast_queue = <296 299>; l0sp = <60 63>; l0cdrr = <144 159>; l0edrr = <144 159>; l1cdrr = <32 35>; l1edrr = <32 35>; }; }; port_scheduler_config { port@0 { port_id = <0>; l1scheduler { group@0 { sp = <0 1>; /*L0 SPs*/ /*cpri cdrr epri edrr*/ cfg = <0 0 0 0>; }; }; l0scheduler { group@0 { /*unicast queues*/ ucast_queue = <0 4 8>; /*multicast queues*/ mcast_queue = <256 260>; /*sp cpri cdrr epri edrr*/ cfg = <0 0 0 0 0>; }; group@1 { ucast_queue = <1 5 9>; mcast_queue = <257 261>; cfg = <0 1 1 1 1>; }; group@2 { ucast_queue = <2 6 10>; mcast_queue = <258 262>; cfg = <0 2 2 2 2>; }; group@3 { ucast_queue = <3 7 11>; mcast_queue = <259 263>; cfg = <0 3 3 3 3>; }; }; }; port@1 { port_id = <1>; l1scheduler { group@0 { sp = <36>; cfg = <0 8 0 8>; }; group@1 { sp = <37>; cfg = <1 9 1 9>; }; }; l0scheduler { group@0 { ucast_queue = <144>; ucast_loop_pri = <16>; mcast_queue = <272>; mcast_loop_pri = <4>; cfg = <36 0 48 0 48>; }; }; }; port@2 { port_id = <2>; l1scheduler { group@0 { sp = <40>; cfg = <0 12 0 12>; }; group@1 { sp = <41>; cfg = <1 13 1 13>; }; }; l0scheduler { group@0 { ucast_queue = <160>; ucast_loop_pri = <16>; mcast_queue = <276>; mcast_loop_pri = <4>; cfg = <40 0 64 0 64>; }; }; }; port@3 { port_id = <3>; l1scheduler { group@0 { sp = <44>; cfg = <0 16 0 16>; }; group@1 { sp = <45>; cfg = <1 17 1 17>; }; }; l0scheduler { group@0 { ucast_queue = <176>; ucast_loop_pri = <16>; mcast_queue = <280>; mcast_loop_pri = <4>; cfg = <44 0 80 0 80>; }; }; }; port@4 { port_id = <4>; l1scheduler { group@0 { sp = <48>; cfg = <0 20 0 20>; }; group@1 { sp = <49>; cfg = <1 21 1 21>; }; }; l0scheduler { group@0 { ucast_queue = <192>; ucast_loop_pri = <16>; mcast_queue = <284>; mcast_loop_pri = <4>; cfg = <48 0 96 0 96>; }; }; }; port@5 { port_id = <5>; l1scheduler { group@0 { sp = <52>; cfg = <0 24 0 24>; }; group@1 { sp = <53>; cfg = <1 25 1 25>; }; }; l0scheduler { group@0 { ucast_queue = <208>; ucast_loop_pri = <16>; mcast_queue = <288>; mcast_loop_pri = <4>; cfg = <52 0 112 0 112>; }; }; }; port@6 { port_id = <6>; l1scheduler { group@0 { sp = <56>; cfg = <0 28 0 28>; }; group@1 { sp = <57>; cfg = <1 29 1 29>; }; }; l0scheduler { group@0 { ucast_queue = <224>; ucast_loop_pri = <16>; mcast_queue = <292>; mcast_loop_pri = <4>; cfg = <56 0 128 0 128>; }; }; }; port@7 { port_id = <7>; l1scheduler { group@0 { sp = <60>; cfg = <0 32 0 32>; }; group@1 { sp = <61>; cfg = <1 33 1 33>; }; }; l0scheduler { group@0 { ucast_queue = <240>; ucast_loop_pri = <16>; mcast_queue = <296>; cfg = <60 0 144 0 144>; }; }; }; }; }; }; &soc { dp1 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <1>; reg = <0x3a001000 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <0>; phy-mode = "sgmii"; }; dp2 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <2>; reg = <0x3a001200 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <1>; phy-mode = "sgmii"; }; dp3 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <3>; reg = <0x3a001400 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <2>; phy-mode = "sgmii"; }; dp4 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <4>; reg = <0x3a001600 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <3>; phy-mode = "sgmii"; }; dp5 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <5>; reg = <0x3a003000 0x3fff>; qcom,mactype = <1>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <15>; phy-mode = "sgmii"; }; dp6 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <6>; reg = <0x3a001a00 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <28>; phy-mode = "sgmii"; }; }; &serial_blsp4 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; status = "ok"; }; &spi_0 { /* BLSP1 QUP1 */ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "ok"; m25p80@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; compatible = "n25q128a11"; linux,modalias = "m25p80", "n25q128a11"; spi-max-frequency = <50000000>; use-default-sizes; }; }; &serial_blsp2 { pinctrl-0 = <&hsuart_pins>; pinctrl-names = "default"; status = "ok"; }; &msm_imem { status = "disabled"; }; &ssphy_0 { status = "ok"; }; &qusb_phy_0 { status = "ok"; }; &ssphy_1 { status = "ok"; }; &qusb_phy_1 { status = "ok"; }; &usb3_0 { status = "ok"; }; &usb3_1 { status = "ok"; }; &cryptobam { status = "ok"; }; &crypto { status = "ok"; }; &i2c_0 { pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; status = "ok"; }; &i2c_1 { status = "disabled"; }; &qpic_bam { status = "ok"; }; &nand { pinctrl-0 = <&qpic_pins>; pinctrl-names = "default"; status = "ok"; };