/dts-v1/;
/*
 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <dt-bindings/clock/qcom,gcc-ipq807x.h>
#include <dt-bindings/reset/qcom,gcc-ipq807x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "qcom-ipq807x-hwk02-wifi.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ807x-HK01";
	compatible = "qcom,ipq807x-hk01", "qcom,ipq807x";
	qcom,msm-id = <0x125 0x0>;
	interrupt-parent = <&intc>;
	qcom,board-id = <0x10 0x0>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD slot */
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {

			cluster0 {

				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

		};

		 CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc0>;
			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <0x2>;
			};
		};

		 CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc1>;
			reg = <0x1>;
			next-level-cache = <&L2_0>;
		};

		 CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc2>;
			reg = <0x2>;
			next-level-cache = <&L2_0>;
		};

		 CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "qcom,arm-cortex-acc";
			qcom,acc = <&acc3>;
			reg = <0x3>;
			next-level-cache = <&L2_0>;
		};

	};

	soc: soc {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		acc0:clock-controller@b188000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b188000 0x1000>;
		};

		acc1:clock-controller@b198000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b198000 0x1000>;
		};

		acc2:clock-controller@b1a8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b1a8000 0x1000>;
		};

		acc3:clock-controller@b1b8000 {
			compatible = "qcom,arm-cortex-acc";
			reg = <0x0b1b8000 0x1000>;
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq807x-pinctrl";
			reg = <0x1000000 0x300000>;
			interrupts = <0x0 0xd0 0x0>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;

			spi_0_pins: spi_0_pins {
				mux {
					pins = "gpio38", "gpio39",
						"gpio40", "gpio41";
					function = "blsp0_spi";
					bias-disable;
				};
			};
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <0x3>;
			reg = <0xb000000 0x1000>,
			<0xb002000 0x1000>;
		};

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <0x1 0x2 0xff08>,
				     <0x1 0x3 0xff08>,
				     <0x1 0x4 0xff08>,
				     <0x1 0x1 0xff08>;
			clock-frequency = <0x124f800>;
		};


		gcc: qcom,gcc@1800000 {
			compatible = "qcom,gcc-ipq807x-v2";
			reg = <0x1800000 0x80000>;
			#clock-cells = <0x1>;
			#reset-cells = <1>;
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x2b000>;
			interrupts = <0 238 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <0x0 107 0x0>;
			status = "ok";
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
		};

		ess-switch@3a000000 {
			compatible = "qcom,ess-switch-ipq807x";
			reg = <0x3a000000 0x1000000>;
			switch_access_mode = "local bus";
			switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
			switch_lan_bmp = <0x3e>; /* lan port bitmap */
			switch_wan_bmp = <0x40>; /* wan port bitmap */
			switch_mac_mode = <0xb>; /* mac mode for uniphy 0*/
			switch_mac_mode1 = <0xd>; /* mac mode for uniphy 1*/
			switch_mac_mode2 = <0xd>; /* mac mode for uniphy 2*/
			bm_tick_mode = <0>; /* bm tick mode */
			tm_tick_mode = <0>; /* tm tick mode */
			port_scheduler_resource {
				port@0 {
					port_id = <0>;
					ucast_queue = <0 143>;
					mcast_queue = <256 271>;
					l0sp = <0 35>;
					l0cdrr = <0 47>;
					l0edrr = <0 47>;
					l1cdrr = <0 7>;
					l1edrr = <0 7>;
				};
				port@1 {
					port_id = <1>;
					ucast_queue = <144 159>;
					mcast_queue = <272 275>;
					l0sp = <36 39>;
					l0cdrr = <48 63>;
					l0edrr = <48 63>;
					l1cdrr = <8 11>;
					l1edrr = <8 11>;
				};
				port@2 {
					port_id = <2>;
					ucast_queue = <160 175>;
					mcast_queue = <276 279>;
					l0sp = <40 43>;
					l0cdrr = <64 79>;
					l0edrr = <64 79>;
					l1cdrr = <12 15>;
					l1edrr = <12 15>;
				};
				port@3 {
					port_id = <3>;
					ucast_queue = <176 191>;
					mcast_queue = <280 283>;
					l0sp = <44 47>;
					l0cdrr = <80 95>;
					l0edrr = <80 95>;
					l1cdrr = <16 19>;
					l1edrr = <16 19>;
				};
				port@4 {
					port_id = <4>;
					ucast_queue = <192 207>;
					mcast_queue = <284 287>;
					l0sp = <48 51>;
					l0cdrr = <96 111>;
					l0edrr = <96 111>;
					l1cdrr = <20 23>;
					l1edrr = <20 23>;
				};
				port@5 {
					port_id = <5>;
					ucast_queue = <208 223>;
					mcast_queue = <288 291>;
					l0sp = <52 55>;
					l0cdrr = <112 127>;
					l0edrr = <112 127>;
					l1cdrr = <24 27>;
					l1edrr = <24 27>;
				};
				port@6 {
					port_id = <6>;
					ucast_queue = <224 239>;
					mcast_queue = <292 295>;
					l0sp = <56 59>;
					l0cdrr = <128 143>;
					l0edrr = <128 143>;
					l1cdrr = <28 31>;
					l1edrr = <28 31>;
				};
				port@7 {
					port_id = <7>;
					ucast_queue = <240 255>;
					mcast_queue = <296 299>;
					l0sp = <60 63>;
					l0cdrr = <144 159>;
					l0edrr = <144 159>;
					l1cdrr = <32 35>;
					l1edrr = <32 35>;
				};
			};
			port_scheduler_config {
				port@0 {
					port_id = <0>;
					l1scheduler {
						group@0 {
							sp = <0 1>; /*L0 SPs*/
							/*cpri cdrr epri edrr*/
							cfg = <0 0 0 0>;
						};
					};
					l0scheduler {
						group@0 {
							/*unicast queues*/
							ucast_queue = <0 4 8>;
							/*multicast queues*/
							mcast_queue = <256 260>;
							/*sp cpricdrrepriedrr*/
							cfg = <0 0 0 0 0>;
						};
						group@1 {
							ucast_queue = <1 5 9>;
							mcast_queue = <257 261>;
							cfg = <0 1 1 1 1>;
						};
						group@2 {
							ucast_queue = <2 6 10>;
							mcast_queue = <258 262>;
							cfg = <0 2 2 2 2>;
						};
						group@3 {
							ucast_queue = <3 7 11>;
							mcast_queue = <259 263>;
							cfg = <0 3 3 3 3>;
						};
					};
				};
				port@1 {
					port_id = <1>;
					l1scheduler {
						group@0 {
							sp = <36>;
							cfg = <0 8 0 8>;
						};
						group@1 {
							sp = <37>;
							cfg = <1 9 1 9>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <144>;
							ucast_loop_pri = <16>;
							mcast_queue = <272>;
							mcast_loop_pri = <4>;
							cfg = <36 0 48 0 48>;
						};
					};
				};
				port@2 {
					port_id = <2>;
					l1scheduler {
						group@0 {
							sp = <40>;
							cfg = <0 12 0 12>;
						};
						group@1 {
							sp = <41>;
							cfg = <1 13 1 13>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <160>;
							ucast_loop_pri = <16>;
							mcast_queue = <276>;
							mcast_loop_pri = <4>;
							cfg = <40 0 64 0 64>;
						};
					};
				};
				port@3 {
					port_id = <3>;
					l1scheduler {
						group@0 {
							sp = <44>;
							cfg = <0 16 0 16>;
						};
						group@1 {
							sp = <45>;
							cfg = <1 17 1 17>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <176>;
							ucast_loop_pri = <16>;
							mcast_queue = <280>;
							mcast_loop_pri = <4>;
							cfg = <44 0 80 0 80>;
						};
					};
				};
				port@4 {
					port_id = <4>;
					l1scheduler {
						group@0 {
							sp = <48>;
							cfg = <0 20 0 20>;
						};
						group@1 {
							sp = <49>;
							cfg = <1 21 1 21>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <192>;
							ucast_loop_pri = <16>;
							mcast_queue = <284>;
							mcast_loop_pri = <4>;
							cfg = <48 0 96 0 96>;
						};
					};
				};
				port@5 {
					port_id = <5>;
					l1scheduler {
						group@0 {
							sp = <52>;
							cfg = <0 24 0 24>;
						};
						group@1 {
							sp = <53>;
							cfg = <1 25 1 25>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <208>;
							ucast_loop_pri = <16>;
							mcast_queue = <288>;
							mcast_loop_pri = <4>;
							cfg = <52 0 112 0 112>;
						};
					};
				};
				port@6 {
					port_id = <6>;
					l1scheduler {
						group@0 {
							sp = <56>;
							cfg = <0 28 0 28>;
						};
						group@1 {
							sp = <57>;
							cfg = <1 29 1 29>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <224>;
							ucast_loop_pri = <16>;
							mcast_queue = <292>;
							mcast_loop_pri = <4>;
							cfg = <56 0 128 0 128>;
						};
					};
				};
				port@7 {
					port_id = <7>;
					l1scheduler {
						group@0 {
							sp = <60>;
							cfg = <0 32 0 32>;
						};
						group@1 {
							sp = <61>;
							cfg = <1 33 1 33>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <240>;
							ucast_loop_pri = <16>;
							mcast_queue = <296>;
							cfg = <60 0 144 0 144>;
						};
					};
				};
			};
		};

		edma@3ab00000 {
			compatible = "qcom,edma";
			reg = <0x3ab00000 0x76900>;
			reg-names = "edma-reg-base";
			qcom,txdesc-ring-start = <23>;
			qcom,txdesc-rings = <1>;
			qcom,txcmpl-ring-start = <7>;
			qcom,txcmpl-rings = <1>;
			qcom,rxfill-ring-start = <7>;
			qcom,rxfill-rings = <1>;
			qcom,rxdesc-ring-start = <15>;
			qcom,rxdesc-rings = <1>;
			interrupts = <0 345 4>,
				   <0 353 4>,
				   <0 361 4>,
				   <0 344 4>;
			resets = <&gcc GCC_EDMA_HW_RESET>;
			reset-names = "edma_rst";
		};

		dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a001000 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
		};

		dp2 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a001200 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
		};

		dp3 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <3>;
			reg = <0x3a001400 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
		};

		dp4 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <4>;
			reg = <0x3a001600 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
		};

		dp5 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <5>;
			reg = <0x3a003000 0x3fff>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
		};

		dp6 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <6>;
			reg = <0x3a007000 0x3fff>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
		};

		nss-common {
			compatible = "qcom,nss-common";
			reg = <0x01868010 0x1000>;
			reg-names = "nss-misc-reset";
		};

		nss0: nss@40000000 {
			compatible = "qcom,nss";
			interrupts = <0 377 0x1>, <0 378 0x1>, <0 379 0x1>,
				     <0 380 0x1>, <0 381 0x1>, <0 382 0x1>,
				     <0 383 0x1>, <0 384 0x1>, <0 385 0x1>;
			reg = <0x39000000 0x1000>, <0x38000000 0x30000>,
			      <0x0b111000 0x1000>;
			reg-names = "nphys", "vphys", "qgic-phys";
			clocks = <&gcc GCC_NSS_NOC_CLK>,
				 <&gcc GCC_NSS_PTP_REF_CLK>,
				 <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
				 <&gcc GCC_NSS_IMEM_CLK>,
				 <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
				 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
				 <&gcc GCC_NSSNOC_SNOC_CLK>,
				 <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
				 <&gcc GCC_NSS_CE_AXI_CLK>,
				 <&gcc GCC_NSS_CE_APB_CLK>,
				 <&gcc GCC_NSSNOC_CE_AXI_CLK>,
				 <&gcc GCC_NSSNOC_CE_APB_CLK>,
				 <&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
				 <&gcc GCC_UBI0_CORE_CLK>,
				 <&gcc GCC_UBI0_AHB_CLK>,
				 <&gcc GCC_UBI0_AXI_CLK>,
				 <&gcc GCC_UBI0_MPT_CLK>,
				 <&gcc GCC_UBI0_NC_AXI_CLK>;
			clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
				      "nss-csr-clk", "nss-cfg-clk",
				      "nss-imem-clk",
				      "nss-nssnoc-qosgen-ref-clk",
				      "nss-mem-noc-nss-axi-clk",
				      "nss-nssnoc-snoc-clk",
				      "nss-nssnoc-timeout-ref-clk",
				      "nss-ce-axi-clk", "nss-ce-apb-clk",
				      "nss-nssnoc-ce-axi-clk",
				      "nss-nssnoc-ce-apb-clk",
				      "nss-nssnoc-ahb-clk",
				      "nss-core-clk", "nss-ahb-clk",
				      "nss-axi-clk", "nss-mpt-clk",
				      "nss-nc-axi-clk";
			qcom,id = <0>;
			qcom,num-queue = <4>;
			qcom,num-irq = <9>;
			qcom,num-pri = <4>;
			qcom,load-addr = <0x40000000>;
			qcom,low-frequency = <748800000>;
			qcom,mid-frequency = <1497600000>;
			qcom,max-frequency = <1689600000>;
			qcom,bridge-enabled;
			qcom,ipv4-enabled;
			qcom,ipv4-reasm-enabled;
			qcom,ipv6-enabled;
			qcom,ipv6-reasm-enabled;
			qcom,wlanredirect-enabled;
			qcom,tun6rd-enabled;
			qcom,l2tpv2-enabled;
			qcom,gre-enabled;
			qcom,gre-redir-enabled;
			qcom,gre-redir-mark-enabled;
			qcom,map-t-enabled;
			qcom,portid-enabled;
			qcom,ppe-enabled;
			qcom,pppoe-enabled;
			qcom,pptp-enabled;
			qcom,tunipip6-enabled;
			qcom,shaping-enabled;
			qcom,wlan-dataplane-offload-enabled;
			qcom,vlan-enabled;
			qcom,vxlan-enabled;
		};

		nss1: nss@40800000 {
			compatible = "qcom,nss";
			interrupts = <0 390 0x1>, <0 391 0x1>, <0 392 0x1>,
				     <0 393 0x1>, <0 394 0x1>, <0 395 0x1>,
				     <0 396 0x1>, <0 397 0x1>, <0 398 0x1>;
			reg = <0x39400000 0x1000>, <0x38030000 0x30000>,
				<0x0b111000 0x1000>;
			reg-names = "nphys", "vphys", "qgic-phys";
			clocks = <&gcc GCC_NSS_NOC_CLK>,
				 <&gcc GCC_NSS_PTP_REF_CLK>,
				 <&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
				 <&gcc GCC_NSS_IMEM_CLK>,
				 <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
				 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
				 <&gcc GCC_NSSNOC_SNOC_CLK>,
				 <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
				 <&gcc GCC_NSS_CE_AXI_CLK>,
				 <&gcc GCC_NSS_CE_APB_CLK>,
				 <&gcc GCC_NSSNOC_CE_AXI_CLK>,
				 <&gcc GCC_NSSNOC_CE_APB_CLK>,
				 <&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
				 <&gcc GCC_UBI1_CORE_CLK>,
				 <&gcc GCC_UBI1_AHB_CLK>,
				 <&gcc GCC_UBI1_AXI_CLK>,
				 <&gcc GCC_UBI1_MPT_CLK>,
				 <&gcc GCC_UBI1_NC_AXI_CLK>;
			clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
				      "nss-csr-clk", "nss-cfg-clk",
				      "nss-imem-clk",
				      "nss-nssnoc-qosgen-ref-clk",
				      "nss-mem-noc-nss-axi-clk",
				      "nss-nssnoc-snoc-clk",
				      "nss-nssnoc-timeout-ref-clk",
				      "nss-ce-axi-clk", "nss-ce-apb-clk",
				      "nss-nssnoc-ce-axi-clk",
				      "nss-nssnoc-ce-apb-clk",
				      "nss-nssnoc-ahb-clk",
				      "nss-core-clk", "nss-ahb-clk",
				      "nss-axi-clk", "nss-mpt-clk",
				      "nss-nc-axi-clk";
			qcom,id = <1>;
			qcom,num-queue = <4>;
			qcom,num-irq = <9>;
			qcom,num-pri = <4>;
			qcom,load-addr = <0x40800000>;
			qcom,capwap-enabled;
			qcom,dtls-enabled;
			qcom,crypto-enabled;
			qcom,ipsec-enabled;
		};

		nss_crypto: qcom,nss_crypto {
			compatible = "qcom,nss-crypto";
			qcom,max-contexts = <64>;
			qcom,max-context-size = <32>;
			ranges;

			eip197_node {
				compatible = "qcom,eip197";
				reg-names = "crypto_pbase";
				reg = <0x39800000 0x7ffff>;
				clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
					<&gcc GCC_NSSNOC_CRYPTO_CLK>,
					<&gcc GCC_CRYPTO_PPE_CLK>;
				clock-names = "crypto_clk", "crypto_nocclk",
						"crypto_ppeclk";
				clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
				qcom,dma-mask = <0xff>;
				qcom,transform-enabled;
				qcom,aes128-cbc;
				qcom,aes192-cbc;
				qcom,aes256-cbc;
				qcom,aes128-ctr;
				qcom,aes192-ctr;
				qcom,aes256-ctr;
				qcom,aes128-ecb;
				qcom,aes192-ecb;
				qcom,aes256-ecb;
				qcom,3des-cbc;
				qcom,sha160-hash;
				qcom,sha224-hash;
				qcom,sha256-hash;
				qcom,sha160-hmac;
				qcom,sha256-hmac;
				qcom,sha384-hmac;
				qcom,sha512-hmac;
				qcom,aes128-gcm-gmac;
				qcom,aes192-gcm-gmac;
				qcom,aes256-gcm-gmac;
				qcom,aes128-cbc-sha160-hmac;
				qcom,aes192-cbc-sha160-hmac;
				qcom,aes256-cbc-sha160-hmac;
				qcom,aes128-ctr-sha160-hmac;
				qcom,aes192-ctr-sha160-hmac;
				qcom,aes256-ctr-sha160-hmac;
				qcom,3des-cbc-sha160-hmac;
				qcom,aes128-cbc-sha256-hmac;
				qcom,aes192-cbc-sha256-hmac;
				qcom,aes256-cbc-sha256-hmac;
				qcom,aes128-ctr-sha256-hmac;
				qcom,aes192-ctr-sha256-hmac;
				qcom,aes256-ctr-sha256-hmac;
				qcom,3des-cbc-sha256-hmac;

				engine0 {
					reg_offset = <0x80000>;
					qcom,ifpp-enabled;
					qcom,ipue-enabled;
					qcom,ofpp-enabled;
					qcom,opue-enabled;
				};
			};
		};

		tcsr_mutex_block: syscon@1905000 {
			compatible = "syscon";
			reg = <0x1905000 0x8000>;
		};

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;
			#hwlock-cells = <1>;
		};

		smem: qcom,smem@4AB00000 {
			compatible = "qcom,smem";
			memory-region = <&smem_region>;
			hwlocks = <&tcsr_mutex 0>;
		};

		apcs: syscon@b111000 {
			compatible = "syscon";
			reg = <0x0B111000 0x1000>;
		};

		qcom_rng: qrng@e1000 {
			compatible = "qcom,prng-ipq807x";
			reg = <0xe3000 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
			status = "ok";
		};

		wcss: smp2p-wcss {
			compatible = "qcom,smp2p";
			qcom,smem = <435>, <428>;

			interrupt-parent = <&intc>;
			interrupts = <0 322 1>;

			qcom,ipc = <&apcs 8 9>;

			qcom,local-pid = <0>;
			qcom,remote-pid = <1>;

			wcss_smp2p_out: master-kernel {
				qcom,entry-name = "master-kernel";
				qcom,smp2p-feature-ssr-ack;
				#qcom,smem-state-cells = <1>;
			};

			wcss_smp2p_in: slave-kernel {
				qcom,entry-name = "slave-kernel";

				interrupt-controller;
				#interrupt-cells = <2>;
			};
		};


		q6v5_wcss: q6v5_wcss@CD00000 {
			compatible = "qca,q6v5-wcss-rproc";
			firmware = "IPQ8074/q6_fw.mdt";
			reg = <0xCD00000 0x4040>,
				<0x194f000 0x10>,
				<0x1952000 0x10>,
				<0x4ab000 0x20>,
				<0x1818000 0x110>,
				<0x1859000 0x10>,
				<0x1945000 0x10>;
			reg-names = "wcss-base",
					"tcsr-q6-base",
					"tcsr-base",
					"mpm-base",
					"gcc-wcss-bcr-base",
					"gcc-wcss-misc-base",
					"tcsr-global";
			qca,auto-restart;
			qca,extended-intc;
			qca,emulation;
			interrupts-extended = <&intc 0 325 1>,
				<&wcss_smp2p_in 0 0>,
				<&wcss_smp2p_in 1 0>,
				<&wcss_smp2p_in 3 0>;
			interrupt-names = "wdog",
				  "qcom,gpio-err-fatal",
				  "qcom,gpio-err-ready",
				  "qcom,gpio-stop-ack";
			qcom,smem-states = <&wcss_smp2p_out 0>,
				   <&wcss_smp2p_out 1>;
			qcom,smem-state-names = "shutdown",
					"stop";
		};

		spi_0: spi@78b5000 { /* BLSP1 QUP0 */
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x78b5000 0x600>;
			interrupts = <0 95 0>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
			dma-names = "tx", "rx";
			#pinctrl-0 = <&spi_0_pins>;
			#pinctrl-names = "default";
			status = "ok";
			m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				compatible = "n25q128a11";
				linux,modalias = "m25p80", "n25q128a11";
				spi-max-frequency = <24000000>;
				use-default-sizes;
			};
		};

		qpic_bam: dma@7984000{
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7984000 0x1a000>;
			interrupts = <0 146 0>;
			clocks = <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "ok";
		};

		nand: qpic-nand@79b0000 {
			compatible = "qcom,ebi2-nandc-bam-v1.5.0";
			reg = <0x79b0000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				<&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
				<&qpic_bam 1>,
				<&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "ok";

			nandcs@0 {
				compatible = "qcom,nandcs";
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <1>;

				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				nand-bus-width = <8>;
			};
		};

		sdhc_1: sdhci@7824900 {
			compatible = "qcom,sdhci-msm";
			reg = <0x7824900 0x500>, <0x7824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";

			qcom,bus-width = <8>;

			qcom,dedicated-io = <1>;

			/* device core power supply */
			qcom,vdd-voltage-level = <2900000 2900000>;
			qcom,vdd-current-level = <200 570000>;

			/* device communication power supply */
			qcom,vdd-io-lpm-sup;
			qcom,vdd-io-voltage-level = <1800000 1800000>;
			qcom,vdd-io-current-level = <200 325000>;
			qcom,vdd-io-always-on;

			qcom,cpu-dma-latency-us = <701>;
			qcom,msm-bus,name = "sdhc1";
			qcom,msm-bus,num-cases = <9>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
				<78 512 1046 3200>,    /* 400 KB/s*/
				<78 512 52286 160000>, /* 20 MB/s */
				<78 512 65360 200000>, /* 25 MB/s */
				<78 512 130718 400000>, /* 50 MB/s */
				<78 512 261438 800000>, /* 100 MB/s */
				<78 512 261438 800000>, /* 200 MB/s */
				<78 512 261438 800000>, /* 400 MB/s */
				<78 512 1338562 4096000>; /* Max. bandwidth */
			qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 \
						50000000 100000000 200000000 \
						400000000 4294967295>;

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>;
			clock-names = "iface_clk", "core_clk";
			qcom,large-address-bus;
			qcom,disable-aggressive-pm;

			qcom,clk-rates = <400000 25000000 50000000 100000000 \
					192000000 384000000>;
			qcom,bus-speed-mode = "DDR_1p8v";
			qcom,nonremovable;
			qcom,emulation = <1>;
			status = "ok";
		};

		sdhc_2: sdhci@7864900 {
			compatible = "qcom,sdhci-msm";
			reg = <0x7864900 0x500>, <0x7864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";

			qcom,bus-width = <4>;
			qcom,dedicated-io = <1>;
			/* device core power supply */
			qcom,vdd-voltage-level = <2950000 2950000>;
			qcom,vdd-current-level = <15000 400000>;

			/* device communication power supply */
			qcom,vdd-io-lpm-sup;
			qcom,vdd-io-voltage-level = <1800000 2950000>;
			qcom,vdd-io-current-level = <200 22000>;
			qcom,vdd-io-always-on;

			qcom,cpu-dma-latency-us = <701>;
			qcom,msm-bus,name = "sdhc2";
			qcom,msm-bus,num-cases = <8>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
				<81 512 1046 3200>,    /* 400 KB/s*/
				<81 512 52286 160000>, /* 20 MB/s */
				<81 512 65360 200000>, /* 25 MB/s */
				<81 512 130718 400000>, /* 50 MB/s */
				<81 512 261438 800000>, /* 100 MB/s */
				<81 512 261438 800000>, /* 200 MB/s */
				<81 512 1338562 4096000>; /* Max. bandwidth */
			qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 \
						50000000 100000000 200000000 \
						4294967295>;

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>;
			clock-names = "iface_clk", "core_clk";
			qcom,large-address-bus;
			qcom,disable-aggressive-pm;

			qcom,clk-rates = <400000 25000000 50000000 100000000 \
					192000000 384000000>;
			qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
			qcom,emulation = <1>;
			status = "ok";
		};

		ssphy_0: ssphy@78000 {
			compatible = "qcom,usb-ssphy-qmp";
			reg = <0x78000 0x45c>,
				<0x0193f244 0x4>,
				<0x08af8800 0x100>,
				<0x7e000 0x18>;
			reg-names = "qmp_phy_base",
				    "vls_clamp_reg",
				    "qscratch_base",
				    "ahb2phy_base";
			qcom,qmp-phy-init-seq = <0xac 0x14 0x1a 0x00
						0x34 0x08 0x08 0x00
						0x174 0x30 0x30 0x00
						0x3c 0x06 0x06 0x00
						0xb4 0x00 0x00 0x00
						0xb8 0x08 0x08 0x00
						0x194 0x06 0x06 0x3e8
						0x19c 0x01 0x01 0x00
						0x178 0x00 0x00 0x00
						0xd0 0x82 0x82 0x00
						0xdc 0x55 0x55 0x00
						0xe0 0x55 0x55 0x00
						0xe4 0x03 0x03 0x00
						0x78 0x0b 0x0b 0x00
						0x84 0x16 0x16 0x00
						0x90 0x28 0x28 0x00
						0x108 0x80 0x80 0x00
						0x10c 0x00 0x00 0x00
						0x184 0x0a 0x0a 0x00
						0x4c 0x15 0x15 0x00
						0x50 0x34 0x34 0x00
						0x54 0x00 0x00 0x00
						0xc8 0x00 0x00 0x00
						0x18c 0x00 0x00 0x00
						0xcc 0x00 0x00 0x00
						0x128 0x00 0x00 0x00
						0x0c 0x0a 0x0a 0x00
						0x10 0x01 0x01 0x00
						0x1c 0x31 0x31 0x00
						0x20 0x01 0x01 0x00
						0x14 0x00 0x00 0x00
						0x18 0x00 0x00 0x00
						0x24 0xde 0xde 0x00
						0x28 0x07 0x07 0x00
						0x48 0x0f 0x0f 0x00
						0x70 0x0f 0x0f 0x00
						0x100 0x80 0x80 0x00
						0x440 0x0b 0x0b 0x00
						0x4d8 0x02 0x02 0x00
						0x4dc 0x6c 0x6c 0x00
						0x4e0 0xbb 0xb8 0x00
						0x508 0x77 0x77 0x00
						0x50c 0x80 0x80 0x00
						0x514 0x03 0x03 0x00
						0x51c 0x16 0x16 0x00
						0x448 0x75 0x75 0x00
						0x454 0x00 0x00 0x00
						0x40c 0x0a 0x0a 0x00
						0x41c 0x06 0x06 0x00
						0x510 0x00 0x00 0x00
						0x268 0x45 0x45 0x00
						0x2ac 0x12 0x12 0x00
						0x294 0x06 0x06 0x00
						0x254 0x00 0x00 0x00
						0x8c8 0x83 0x83 0x00
						0x8c4 0x02 0x02 0x00
						0x8cc 0x09 0x09 0x00
						0x8d0 0xa2 0xa2 0x00
						0x8d4 0x85 0x85 0x00
						0x880 0xd1 0xd1 0x00
						0x884 0x1f 0x1f 0x00
						0x888 0x47 0x47 0x00
						0x80c 0x9f 0x9f 0x00
						0x824 0x17 0x17 0x00
						0x828 0x0f 0x0f 0x00
						0x8b8 0x75 0x75 0x00
						0x8bc 0x13 0x13 0x00
						0x8b0 0x86 0x86 0x00
						0x8a0 0x04 0x04 0x00
						0x88c 0x44 0x44 0x00
						0x870 0xe7 0xe7 0x00
						0x874 0x03 0x03 0x00
						0x878 0x40 0x40 0x00
						0x87c 0x00 0x00 0x00
						0x9d8 0x88 0x88 0x00
						0xffffffff 0xffffffff 0x00 0x00>;
			qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994
						0x974 0x8d8 0x8dc 0x804 0x800
						0x808>;

			clocks = <&gcc GCC_USB0_AUX_CLK>,
				 <&gcc GCC_USB0_PIPE_CLK>;

			clock-names = "aux_clk", "pipe_clk";

			resets =  <&gcc GCC_USB0_PHY_BCR>,
				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
			reset-names = "usb3_phy_reset",
				      "usb3phy_phy_reset";

			qcom,emulation = <1>;
			status = "ok";
		};

		ssphy_1: ssphy@58000 {
			compatible = "qcom,usb-ssphy-qmp";
			reg = <0x58000 0x45c>,
				<0x08cf8800 0x100>,
				<0x5e000 0x18>;
			reg-names = "qmp_phy_base",
				    "qscratch_base",
				    "ahb2phy_base";
			qcom,qmp-phy-init-seq = <0xac 0x14 0x1a 0x00
						0x34 0x08 0x08 0x00
						0x174 0x30 0x30 0x00
						0x3c 0x06 0x06 0x00
						0xb4 0x00 0x00 0x00
						0xb8 0x08 0x08 0x00
						0x194 0x06 0x06 0x3e8
						0x19c 0x01 0x01 0x00
						0x178 0x00 0x00 0x00
						0xd0 0x82 0x82 0x00
						0xdc 0x55 0x55 0x00
						0xe0 0x55 0x55 0x00
						0xe4 0x03 0x03 0x00
						0x78 0x0b 0x0b 0x00
						0x84 0x16 0x16 0x00
						0x90 0x28 0x28 0x00
						0x108 0x80 0x80 0x00
						0x10c 0x00 0x00 0x00
						0x184 0x0a 0x0a 0x00
						0x4c 0x15 0x15 0x00
						0x50 0x34 0x34 0x00
						0x54 0x00 0x00 0x00
						0xc8 0x00 0x00 0x00
						0x18c 0x00 0x00 0x00
						0xcc 0x00 0x00 0x00
						0x128 0x00 0x00 0x00
						0x0c 0x0a 0x0a 0x00
						0x10 0x01 0x01 0x00
						0x1c 0x31 0x31 0x00
						0x20 0x01 0x01 0x00
						0x14 0x00 0x00 0x00
						0x18 0x00 0x00 0x00
						0x24 0xde 0xde 0x00
						0x28 0x07 0x07 0x00
						0x48 0x0f 0x0f 0x00
						0x70 0x0f 0x0f 0x00
						0x100 0x80 0x80 0x00
						0x440 0x0b 0x0b 0x00
						0x4d8 0x02 0x02 0x00
						0x4dc 0x6c 0x6c 0x00
						0x4e0 0xbb 0xb8 0x00
						0x508 0x77 0x77 0x00
						0x50c 0x80 0x80 0x00
						0x514 0x03 0x03 0x00
						0x51c 0x16 0x16 0x00
						0x448 0x75 0x75 0x00
						0x454 0x00 0x00 0x00
						0x40c 0x0a 0x0a 0x00
						0x41c 0x06 0x06 0x00
						0x510 0x00 0x00 0x00
						0x268 0x45 0x45 0x00
						0x2ac 0x12 0x12 0x00
						0x294 0x06 0x06 0x00
						0x254 0x00 0x00 0x00
						0x8c8 0x83 0x83 0x00
						0x8c4 0x02 0x02 0x00
						0x8cc 0x09 0x09 0x00
						0x8d0 0xa2 0xa2 0x00
						0x8d4 0x85 0x85 0x00
						0x880 0xd1 0xd1 0x00
						0x884 0x1f 0x1f 0x00
						0x888 0x47 0x47 0x00
						0x80c 0x9f 0x9f 0x00
						0x824 0x17 0x17 0x00
						0x828 0x0f 0x0f 0x00
						0x8b8 0x75 0x75 0x00
						0x8bc 0x13 0x13 0x00
						0x8b0 0x86 0x86 0x00
						0x8a0 0x04 0x04 0x00
						0x88c 0x44 0x44 0x00
						0x870 0xe7 0xe7 0x00
						0x874 0x03 0x03 0x00
						0x878 0x40 0x40 0x00
						0x87c 0x00 0x00 0x00
						0x9d8 0x88 0x88 0x00
						0xffffffff 0xffffffff 0x00 0x00>;
			qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994
						0x974 0x8d8 0x8dc 0x804 0x800
						0x808>;

			clocks = <&gcc GCC_USB1_AUX_CLK>,
				 <&gcc GCC_USB1_PIPE_CLK>;

			clock-names = "aux_clk", "pipe_clk";

			resets = <&gcc GCC_USB1_PHY_BCR>,
				 <&gcc GCC_USB3PHY_1_PHY_BCR>;
			reset-names = "usb3_phy_reset",
				      "usb3phy_phy_reset";

			qcom,emulation = <1>;
			status = "ok";
		};

		qusb_phy_0: qusb@79000 {
			  compatible = "qcom,qusb2phy";
			  reg = <0x079000 0x180>,
				<0x08af8800 0x400>,
				<0x01841030 0x4>,
				<0x08A0C12C 0x4>;
			  reg-names = "qusb_phy_base",
				  "qscratch_base",
				  "ref_clk_addr",
				  "usb3_guctl_addr";

			  qcom,qusb-phy-init-seq = <0xF8 0x80
				  0x83 0x84
				  0x83 0x88
				  0xC0 0x8C
				  0x30 0x08
				  0x79 0x0C
				  0x21 0x10
				  0x14 0x9C
				  0x80 0x04
				  0x9F 0x1C>;
			  phy_type= "utmi";

			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
			reset-names = "usb2_phy_reset";

			qcom,emulation = <1>;
			status = "ok";
		};

		qusb_phy_1: qusb@59000 {
			  compatible = "qcom,qusb2phy";
			  reg = <0x059000 0x180>,
				<0x08cf8800 0x400>,
				<0x01841030 0x4>,
				<0x08C0C12C 0x4>;
			  reg-names = "qusb_phy_base",
				  "qscratch_base",
				  "ref_clk_addr",
				  "usb3_guctl_addr";
			  qcom,qusb-phy-init-seq = <0xF8 0x80
				  0x83 0x84
				  0x83 0x88
				  0xC0 0x8C
				  0x30 0x08
				  0x79 0x0C
				  0x21 0x10
				  0x14 0x9C
				  0x80 0x04
				  0x9F 0x1C>;

			  phy_type= "utmi";

			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
			reset-names = "usb2_phy_reset";

			qcom,emulation = <1>;
			status = "ok";
		};

		usb3_0: usb3@8A00000 {
			compatible = "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			reg = <0x8AF8800 0x100>;
			reg-names = "qscratch_base";
			clocks = <&gcc GCC_SNOC_BUS_TIMEOUT2_AHB_CLK>,
				<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
				<&gcc GCC_USB0_MASTER_CLK>,
				<&gcc GCC_USB0_SLEEP_CLK>,
				<&gcc GCC_USB0_MOCK_UTMI_CLK>,
				<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				<&gcc GCC_USB0_AUX_CLK>,
				<&gcc GCC_USB0_PIPE_CLK>;
			clock-names = "snoc_bus_timeout2",
				"sys_noc_axi",
				"master",
				"sleep",
				"mock_utmi",
				"cfg_ahb_clk",
				"aux_clk",
				"pipe_clk";
			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
					  <&gcc GCC_USB0_MASTER_CLK>,
					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
			assigned-clock-rates = <133330000>,
					       <133330000>,
					       <20000000>;
			qca,host = <1>;
			status = "ok";

			dwc_0: dwc3@8A00000 {
				compatible = "snps,dwc3";
				reg = <0x8A00000 0xcd00>;
				interrupts = <0 140 0>;
				usb-phy = <&qusb_phy_0>, <&ssphy_0>;
				tx-fifo-resize;
				snps,usb3-u1u2-disable;
				snps,nominal-elastic-buffer;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				usb2-susphy-quirk;
				qcom,emulation = <1>;
				dr_mode = "host";
			};
		};

		usb3_1: usb3@8C00000 {
			compatible = "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			reg = <0x8CF8800 0x100>;
			reg-names = "qscratch_base";
			clocks = <&gcc GCC_SNOC_BUS_TIMEOUT3_AHB_CLK>,
				<&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
				<&gcc GCC_USB1_MASTER_CLK>,
				<&gcc GCC_USB1_SLEEP_CLK>,
				<&gcc GCC_USB1_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
				 <&gcc GCC_USB1_AUX_CLK>,
				 <&gcc GCC_USB1_PIPE_CLK>;
			clock-names = "snoc_bus_timeout3",
				"sys_noc_axi",
				"master",
				"sleep",
				"mock_utmi",
				"cfg_ahb_clk",
				"aux_clk",
				"pipe_clk";

			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
					  <&gcc GCC_USB1_MASTER_CLK>,
					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
			assigned-clock-rates = <133330000>,
					       <133330000>,
					       <20000000>;
			qca,host = <1>;
			status = "ok";

			dwc_1: dwc3@8C00000 {
				compatible = "snps,dwc3";
				reg = <0x8C00000 0xcd00>;
				interrupts = <0 99 0>;
				usb-phy = <&qusb_phy_1>, <&ssphy_1>;
				tx-fifo-resize;
				snps,usb3-u1u2-disable;
				snps,nominal-elastic-buffer;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				usb2-susphy-quirk;
				qcom,emulation = <1>;
				dr_mode = "host";
			};
		};

		pcie0: pci@20000000 {
			compatible = "qcom,pcie-ipq807x";
			reg =  <0x20000000 0xf1d
				0x20000F20 0xa8
				0x20001000 0x1000
				0x80000 0x2000
				0x20100000 0x1000>;
			reg-names = "dbi", "elbi", "dm_iatu", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x20200000 0x20200000
				  0 0x00100000   /* downstream I/O */
				  0x82000000 0 0x20300000 0x20300000
				  0 0x10000000>; /* non-prefetchable memory */

			interrupts = <0 52 0>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 75
					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 78
					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 79
					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 83
					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
				 <&gcc GCC_PCIE0_AXI_M_CLK>,
				 <&gcc GCC_PCIE0_AXI_S_CLK>,
				 <&gcc GCC_PCIE0_AHB_CLK>,
				 <&gcc GCC_PCIE0_AUX_CLK>;

			clock-names = "sys_noc",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "aux";
			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
				 <&gcc GCC_PCIE0_SLEEP_ARES>,
				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
				 <&gcc GCC_PCIE0_AHB_ARES>,
				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
			reset-names = "pipe",
				      "sleep",
				      "sticky",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "axi_m_sticky";

			perst-gpio = <&tlmm 58 1>;
			is_emulation = <1>;
			is_gen3 = <1>;
			status = "disabled";
		};

		pcie1: pci@10000000 {
			compatible = "qcom,pcie-ipq807x";
			reg =  <0x10000000 0xf1d
				0x10000F20 0xa8
				0x88000 0x2000
				0x10100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x10200000 0x10200000
				  0 0x00100000   /* downstream I/O */
				  0x82000000 0 0x10300000 0x10300000
				  0 0x00d00000>; /* non-prefetchable memory */

			interrupts = <0 85 0>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 142
					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 143
					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 144
					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 145
					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
				 <&gcc GCC_PCIE1_AXI_M_CLK>,
				 <&gcc GCC_PCIE1_AXI_S_CLK>,
				 <&gcc GCC_PCIE1_AHB_CLK>,
				 <&gcc GCC_PCIE1_AUX_CLK>;
			clock-names = "sys_noc",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "aux";
			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
				 <&gcc GCC_PCIE1_SLEEP_ARES>,
				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
				 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
				 <&gcc GCC_PCIE1_AHB_ARES>,
				 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
			reset-names = "pipe",
				      "sleep",
				      "sticky",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "axi_m_sticky";

			perst-gpio = <&tlmm 61 1>;
			is_emulation = <1>;
			status = "disabled";
		};

		glink_modem: qcom,glink-smem-native-xprt-modem@4AB00000 {
			compatible = "qcom,glink-smem-native-xprt";
			reg = <0x4AB00000 0x100000>, <0x0b111008 0x4>;
			reg-names = "smem", "irq-reg-base";
			qcom,irq-mask = <0x100>;
			interrupts = <0 321 1>;
			label = "mpss";
			qcom,subsys-id = <1>;
			smem-entry = <478>, <479>, <480>;
			smem-entry-names = "ch", "tx_fifo", "rx_fifo";
		};

		ipc_router: qcom,ipc_router {
			compatible = "qcom,ipc_router";
			qcom,node-id = <1>;
		};

		ipc_router_modem: qcom,ipc_router_modem_xprt {
			compatible = "qcom,ipc_router_glink_xprt";
			qcom,ch-name = "IPCRTR";
			qcom,xprt-remote = "mpss";
			qcom,glink-xprt = "smem";
			qcom,xprt-linkid = <1>;
			qcom,xprt-version = <1>;
			qcom,fragmented-data;
		};
	};

	clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <19200000>;
			#clock-cells = <0>;
		};
	};

	chosen {
		linux,initrd-end = <0x46000000>;
		linux,initrd-start = <0x44000000>;
		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
			    init=/init";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000 0x0 0x20000000>;
	};

	/*
	 * +=========+==============+========================+
	 * |        |              |                         |
	 * | Region | Start Offset |          Size           |
	 * |        |              |                         |
	 * +--------+--------------+-------------------------+
	 * |        |              |                         |
	 * |        |              |                         |
	 * |  NSS   |  0x40000000  |          16MB           |
	 * |        |              |                         |
	 * |        |              |                         |
	 * +--------+--------------+-------------------------+
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * | Linux  |  0x41000000  | Depends on total memory |
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * +--------+--------------+-------------------------+
	 * | uboot  |  0x4A600000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |  SBL   |  0x4AA00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  smem  |  0x4AB00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |        |              |                         |
	 * |TZ+APPS |  0x4AC00000  |           4MB           |
	 * |        |              |                         |
	 * +--------+--------------+-------------------------+
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * |   Q6   |  0x4B000000  |          85MB           |
	 * |        |              |                         |
	 * |        |              |                         |
	 * |        |              |                         |
	 * +--------+--------------+-------------------------+
	 * |                                                 |
	 * |      Rest of the memory for Linux               |
	 * |                                                 |
	 * +=================================================+
	 */

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		nss@40000000 {
			no-map;
			reg = <0x0 0x40000000 0x0 0x01000000>;
		};

		uboot@4a600000 {
			no-map;
			reg = <0x0 0x4a600000 0x0 0x00400000>;
		};

		sbl@4aa00000 {
			no-map;
			reg = <0x0 0x4aa00000 0x0 0x00100000>;
		};

		smem_region:smem@4ab00000 {
			no-map;
			reg = <0x0 0x4ab00000 0x0 0x00100000>;
		};

		tz@4ac00000 {	/* TZ and TZ_APPS */
			no-map;
			reg = <0x0 0x4ac00000 0x0 0x00400000>;
		};

		wcnss@4b000000 {
			no-map;
			reg = <0x0 0x4b000000 0x0 0x05500000>;
		};

		tzapp:tzapp@4a400000 {
			no-map;
			reg = <0x0 0x4a400000 0x0 0x00200000>;
		};
	};

};