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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Marvell nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ #ifndef __INCmvDramIfRegsh #define __INCmvDramIfRegsh /* DDR SDRAM Controller Address Decode Registers */ /* SDRAM CSn Base Address Register (SCBAR) */ #define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) #define SCBAR_BASE_OFFS 16 #define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) #define SCBAR_BASE_ALIGNMENT 0x10000 /* SDRAM CSn Size Register (SCSR) */ #define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) #define SCSR_WIN_EN BIT0 #define SCSR_SIZE_OFFS 16 #define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) #define SCSR_SIZE_ALIGNMENT 0x10000 /* configuration register */ #define SDRAM_CONFIG_REG 0x1400 #define SDRAM_REFRESH_OFFS 0 #define SDRAM_REFRESH_MAX 0x3000 #define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) #define SDRAM_DWIDTH_OFFS 14 #define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) #define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) #define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) #define SDRAM_DTYPE_OFFS 16 #define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) #define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) #define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) #define SDRAM_REGISTERED (1 << 17) #define SDRAM_PERR_OFFS 18 #define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) #define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) #define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) #define SDRAM_DCFG_OFFS 20 #define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) #define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) #define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) #define SDRAM_SRMODE (1 << 24) #define SDRAM_SRCLK_OFFS 25 #define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) #define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) #define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) #define SDRAM_CATTH_OFFS 26 #define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) /* dunit control register */ #define SDRAM_DUNIT_CTRL_REG 0x1404 #define SDRAM_CTRL_POS_OFFS 6 #define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) #define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) #define SDRAM_CLK1DRV_OFFS 12 #define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) #define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) #define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) #define SDRAM_LOCKEN_OFFS 18 #define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) #define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) #define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) #define SDRAM_ST_BURST_DEL_OFFS 24 #define SDRAM_ST_BURST_DEL_MAX 0xf #define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX<