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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Marvell nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ #ifndef __INCPCIREGSH #define __INCPCIREGSH #include "pci-if/mvPciIfRegs.h" /* defines */ #define MAX_PCI_DEVICES 32 #define MAX_PCI_FUNCS 8 #define MAX_PCI_BUSSES 128 /* enumerators */ /* This enumerator described the possible PCI slave targets. */ /* PCI slave targets are designated memory/IO address spaces that the */ /* PCI slave targets can access. They are also refered as "targets" */ /* this enumeratoe order is determined by the content of : PCI_BASE_ADDR_ENABLE_REG */ /* registers offsetes defines */ /*************************/ /* PCI control registers */ /*************************/ /* maen : should add new registers */ #define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) #define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) #define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) #define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) #define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) #define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) #define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) #define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) #define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) #define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) /* PCI Dll Control (PDC)*/ #define PDC_DLL_EN BIT0 /* PCI Command Register (PCR) */ #define PCR_MASTER_BYTE_SWAP_EN BIT0 #define PCR_MASTER_WR_COMBINE_EN BIT4 #define PCR_MASTER_RD_COMBINE_EN BIT5 #define PCR_MASTER_WR_TRIG_WHOLE BIT6 #define PCR_MASTER_RD_TRIG_WHOLE BIT7 #define PCR_MASTER_MEM_RD_LINE_EN BIT8 #define PCR_MASTER_MEM_RD_MULT_EN BIT9 #define PCR_MASTER_WORD_SWAP_EN BIT10 #define PCR_SLAVE_WORD_SWAP_EN BIT11 #define PCR_NS_ACCORDING_RCV_TRANS BIT14 #define PCR_MASTER_PCIX_REQ64N_EN BIT15 #define PCR_SLAVE_BYTE_SWAP_EN BIT16 #define PCR_MASTER_DAC_EN BIT17 #define PCR_MASTER_M64_ALLIGN BIT18 #define PCR_ERRORS_PROPAGATION_EN BIT19 #define PCR_SLAVE_SWAP_ENABLE BIT20 #define PCR_MASTER_SWAP_ENABLE BIT21 #define PCR_MASTER_INT_SWAP_EN BIT22 #define PCR_LOOP_BACK_ENABLE BIT23 #define PCR_SLAVE_INTREG_SWAP_OFFS 24 #define PCR_SLAVE_INTREG_SWAP_MASK 0x3 #define PCR_SLAVE_INTREG_BYTE_SWAP \ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) #define PCR_SLAVE_INTREG_NO_SWAP \ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) #define PCR_SLAVE_INTREG_BYTE_WORD \ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) #define PCR_SLAVE_INTREG_WORD_SWAP \ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) #define PCR_RESET_REASSERTION_EN BIT26 #define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 #define PCR_CPU_TO_PCI_ORDER_EN BIT29 #define PCR_PCI_TO_CPU_ORDER_EN BIT30 /* PCI Mode Register (PMR) */ #define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ #define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) #define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) #define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ #define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) #define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) #define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) #define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ #define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) #define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) #define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) #define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) #define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) #define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ #define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ #define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) #define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) /* PCI Retry Register (PRR) */ #define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ #define PRR_RETRY_CNTR_MAX 0xff #define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) /* PCI Discard Timer Register (PDTR) */ #define PDTR_TIMER_OFFS 0 /* Timer */ #define PDTR_TIMER_MAX 0xffff #define PDTR_TIMER_MIN 0x7F #define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) /* PCI Arbiter Control Register (PACR) */ #define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ #define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ #define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) #define PACR_BROKEN_VAL_CONV_MIN 0x2 #define PACR_BROKEN_VAL_PCIX_MIN 0x6 #define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ #define PACR_PARK_DIS_MAX_AGENT 0x3f #define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<