/****************************************************************************** Copyright (c) 2010 Lantiq Deutschland GmbH Am Campeon 3; 85579 Neubiberg, Germany For licensing information, see the file 'LICENSE' in the root folder of this software module. ******************************************************************************/ #include #include #include IFX_ETHSW_regMapper_t regMapper_AR9[] = { /* ARP_APT (# 0) */ { (IFX_uint16_t)ARP_APT, (IFX_uint16_t)AR9_ARP_REG_APT_OFFSET, (IFX_uint8_t)AR9_ARP_REG_APT_SHIFT, (IFX_uint8_t)AR9_ARP_REG_APT_SIZE}, /* ARP_MACA (# 1) */ { (IFX_uint16_t)ARP_MACA, (IFX_uint16_t)AR9_ARP_REG_MACA_OFFSET, (IFX_uint8_t)AR9_ARP_REG_MACA_SHIFT, (IFX_uint8_t)AR9_ARP_REG_MACA_SIZE}, /* ARP_RAPA (# 2) */ { (IFX_uint16_t)ARP_RAPA, (IFX_uint16_t)AR9_ARP_REG_RAPA_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RAPA_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RAPA_SIZE}, /* ARP_RAPOTH (# 3) */ { (IFX_uint16_t)ARP_RAPOTH, (IFX_uint16_t)AR9_ARP_REG_RAPOTH_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RAPOTH_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RAPOTH_SIZE}, /* ARP_RAPP (# 4) */ { (IFX_uint16_t)ARP_RAPP, (IFX_uint16_t)AR9_ARP_REG_RAPP_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RAPP_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RAPP_SIZE}, /* ARP_RAPPE (# 5) */ { (IFX_uint16_t)ARP_RAPPE, (IFX_uint16_t)AR9_ARP_REG_RAPPE_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RAPPE_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RAPPE_SIZE}, /* ARP_RAPTM (# 6) */ { (IFX_uint16_t)ARP_RAPTM, (IFX_uint16_t)AR9_ARP_REG_RAPTM_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RAPTM_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RAPTM_SIZE}, /* ARP_RPT (# 7) */ { (IFX_uint16_t)ARP_RPT, (IFX_uint16_t)AR9_ARP_REG_RPT_OFFSET, (IFX_uint8_t)AR9_ARP_REG_RPT_SHIFT, (IFX_uint8_t)AR9_ARP_REG_RPT_SIZE}, /* ARP_TAP (# 8) */ { (IFX_uint16_t)ARP_TAP, (IFX_uint16_t)AR9_ARP_REG_TAP_OFFSET, (IFX_uint8_t)AR9_ARP_REG_TAP_SHIFT, (IFX_uint8_t)AR9_ARP_REG_TAP_SIZE}, /* ARP_TAPTS (# 9) */ { (IFX_uint16_t)ARP_TAPTS, (IFX_uint16_t)AR9_ARP_REG_TAPTS_OFFSET, (IFX_uint8_t)AR9_ARP_REG_TAPTS_SHIFT, (IFX_uint8_t)AR9_ARP_REG_TAPTS_SIZE}, /* ARP_TRP (# 10) */ { (IFX_uint16_t)ARP_TRP, (IFX_uint16_t)AR9_ARP_REG_TRP_OFFSET, (IFX_uint8_t)AR9_ARP_REG_TRP_SHIFT, (IFX_uint8_t)AR9_ARP_REG_TRP_SIZE}, /* ARP_UPT (# 11) */ { (IFX_uint16_t)ARP_UPT, (IFX_uint16_t)AR9_ARP_REG_UPT_OFFSET, (IFX_uint8_t)AR9_ARP_REG_UPT_SHIFT, (IFX_uint8_t)AR9_ARP_REG_UPT_SIZE}, /* BIST_CTBR (# 12) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_DBBR (# 13) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_DONE (# 14) */ { (IFX_uint16_t)BIST_DONE, (IFX_uint16_t)AR9_SW_GCTL1_REG_BISTDN_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_BISTDN_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_BISTDN_SIZE}, /* BIST_HIGTBR (# 15) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_HISTBR (# 16) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_LLTBR (# 17) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_LTBR (# 18) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PFA (# 19) */ { (IFX_uint16_t)BUFFER_PFA, (IFX_uint16_t)AR9_BF_TH_REG_PFA_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PFA_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PFA_SIZE}, /* BUFFER_PFO0 (# 20) */ { (IFX_uint16_t)BUFFER_PFO0, (IFX_uint16_t)AR9_BF_TH_REG_PFO0_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PFO0_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PFO0_SIZE}, /* BUFFER_PFO1 (# 21) */ { (IFX_uint16_t)BUFFER_PFO1, (IFX_uint16_t)AR9_BF_TH_REG_PFO1_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PFO1_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PFO1_SIZE}, /* BUFFER_PFO2 (# 22) */ { (IFX_uint16_t)BUFFER_PFO2, (IFX_uint16_t)AR9_BF_TH_REG_PFO2_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PFO2_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PFO2_SIZE}, /* BUFFER_PUA (# 23) */ { (IFX_uint16_t)BUFFER_PUA, (IFX_uint16_t)AR9_BF_TH_REG_PUA_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PUA_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PUA_SIZE}, /* BUFFER_PUO0 (# 24) */ { (IFX_uint16_t)BUFFER_PUO0, (IFX_uint16_t)AR9_BF_TH_REG_PUO0_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PUO0_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PUO0_SIZE}, /* BUFFER_PUO1 (# 25) */ { (IFX_uint16_t)BUFFER_PUO1, (IFX_uint16_t)AR9_BF_TH_REG_PUO1_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PUO1_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PUO1_SIZE}, /* BUFFER_PUO2 (# 26) */ { (IFX_uint16_t)BUFFER_PUO2, (IFX_uint16_t)AR9_BF_TH_REG_PUO2_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_PUO2_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_PUO2_SIZE}, /* BUFFER_THA (# 27) */ { (IFX_uint16_t)BUFFER_THA, (IFX_uint16_t)AR9_BF_TH_REG_THA_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_THA_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_THA_SIZE}, /* BUFFER_THO (# 28) */ { (IFX_uint16_t)BUFFER_THO, (IFX_uint16_t)AR9_BF_TH_REG_THO_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_THO_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_THO_SIZE}, /* BUFFER_TLA (# 29) */ { (IFX_uint16_t)BUFFER_TLA, (IFX_uint16_t)AR9_BF_TH_REG_TLA_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_TLA_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_TLA_SIZE}, /* BUFFER_TLO (# 30) */ { (IFX_uint16_t)BUFFER_TLO, (IFX_uint16_t)AR9_BF_TH_REG_TLO_OFFSET, (IFX_uint8_t)AR9_BF_TH_REG_TLO_SHIFT, (IFX_uint8_t)AR9_BF_TH_REG_TLO_SIZE}, /* CHIPID_BOND (# 31) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* CHIPID_PC (# 32) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* CHIPID_VN (# 33) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* CONGESTION_EDSTX (# 34) */ { (IFX_uint16_t)CONGESTION_EDSTX, (IFX_uint16_t)AR9_SW_GCTL1_REG_EDSTX_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_EDSTX_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_EDSTX_SIZE}, /* CONGESTION_IJT (# 35) */ { (IFX_uint16_t)CONGESTION_IJT, (IFX_uint16_t)AR9_SW_GCTL1_REG_IJT_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_IJT_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_IJT_SIZE}, /* CONGESTION_IRSJA (# 36) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* CONGESTION_STORM_100_TH (# 37) */ { (IFX_uint16_t)CONGESTION_STORM_100_TH, (IFX_uint16_t)AR9_STRM_CTL_REG_STORM_100_TH_OFFSET, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_100_TH_SHIFT, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_100_TH_SIZE}, /* CONGESTION_STORM_10_TH (# 38) */ { (IFX_uint16_t)CONGESTION_STORM_10_TH, (IFX_uint16_t)AR9_STRM_CTL_REG_STORM_10_TH_OFFSET, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_10_TH_SHIFT, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_10_TH_SIZE}, /* CONGESTION_STORM_B (# 39) */ { (IFX_uint16_t)CONGESTION_STORM_B, (IFX_uint16_t)AR9_STRM_CTL_REG_STORM_B_OFFSET, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_B_SHIFT, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_B_SIZE}, /* CONGESTION_STORM_M (# 40) */ { (IFX_uint16_t)CONGESTION_STORM_M, (IFX_uint16_t)AR9_STRM_CTL_REG_STORM_M_OFFSET, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_M_SHIFT, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_M_SIZE}, /* CONGESTION_STORM_U (# 41) */ { (IFX_uint16_t)CONGESTION_STORM_U, (IFX_uint16_t)AR9_STRM_CTL_REG_STORM_U_OFFSET, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_U_SHIFT, (IFX_uint8_t)AR9_STRM_CTL_REG_STORM_U_SIZE}, /* DIFFSERV_PQA (# 42) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ0_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ0_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ0_SIZE}, /* DIFFSERV_PQA01 (# 43) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ1_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ1_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ1_SIZE}, /* DIFFSERV_PQA02 (# 44) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ2_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ2_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ2_SIZE}, /* DIFFSERV_PQA03 (# 45) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ3_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ3_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ3_SIZE}, /* DIFFSERV_PQA04 (# 46) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ4_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ4_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ4_SIZE}, /* DIFFSERV_PQA05 (# 47) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ5_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ5_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ5_SIZE}, /* DIFFSERV_PQA06 (# 48) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ6_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ6_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ6_SIZE}, /* DIFFSERV_PQA07 (# 49) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ7_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ7_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ7_SIZE}, /* DIFFSERV_PQA08 (# 50) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ8_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ8_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ8_SIZE}, /* DIFFSERV_PQA09 (# 51) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQ9_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ9_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQ9_SIZE}, /* DIFFSERV_PQA10 (# 52) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQA_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQA_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQA_SIZE}, /* DIFFSERV_PQA11 (# 53) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQB_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQB_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQB_SIZE}, /* DIFFSERV_PQA12 (# 54) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQC_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQC_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQC_SIZE}, /* DIFFSERV_PQA13 (# 55) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQD_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQD_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQD_SIZE}, /* DIFFSERV_PQA14 (# 56) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQE_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQE_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQE_SIZE}, /* DIFFSERV_PQA15 (# 57) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)AR9_DFSRV_MAP0_REG_PQF_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQF_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP0_REG_PQF_SIZE}, /* DIFFSERV_PQB (# 58) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ10_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ10_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ10_SIZE}, /* DIFFSERV_PQB01 (# 59) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ11_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ11_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ11_SIZE}, /* DIFFSERV_PQB02 (# 60) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ12_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ12_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ12_SIZE}, /* DIFFSERV_PQB03 (# 61) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ13_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ13_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ13_SIZE}, /* DIFFSERV_PQB04 (# 62) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ14_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ14_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ14_SIZE}, /* DIFFSERV_PQB05 (# 63) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ15_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ15_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ15_SIZE}, /* DIFFSERV_PQB06 (# 64) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ16_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ16_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ16_SIZE}, /* DIFFSERV_PQB07 (# 65) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ17_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ17_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ17_SIZE}, /* DIFFSERV_PQB08 (# 66) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ18_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ18_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ18_SIZE}, /* DIFFSERV_PQB09 (# 67) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ19_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ19_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ19_SIZE}, /* DIFFSERV_PQB10 (# 68) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1A_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1A_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1A_SIZE}, /* DIFFSERV_PQB11 (# 69) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1B_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1B_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1B_SIZE}, /* DIFFSERV_PQB12 (# 70) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1C_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1C_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1C_SIZE}, /* DIFFSERV_PQB13 (# 71) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1D_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1D_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1D_SIZE}, /* DIFFSERV_PQB14 (# 72) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1E_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1E_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1E_SIZE}, /* DIFFSERV_PQB15 (# 73) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)AR9_DFSRV_MAP1_REG_PQ1F_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1F_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP1_REG_PQ1F_SIZE}, /* DIFFSERV_PQC (# 74) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ20_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ20_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ20_SIZE}, /* DIFFSERV_PQC01 (# 75) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ21_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ21_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ21_SIZE}, /* DIFFSERV_PQC02 (# 76) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ22_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ22_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ22_SIZE}, /* DIFFSERV_PQC03 (# 77) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ23_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ23_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ23_SIZE}, /* DIFFSERV_PQC04 (# 78) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ24_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ24_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ24_SIZE}, /* DIFFSERV_PQC05 (# 79) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ25_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ25_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ25_SIZE}, /* DIFFSERV_PQC06 (# 80) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ26_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ26_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ26_SIZE}, /* DIFFSERV_PQC07 (# 81) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ27_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ27_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ27_SIZE}, /* DIFFSERV_PQC08 (# 82) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ28_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ28_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ28_SIZE}, /* DIFFSERV_PQC09 (# 83) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ29_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ29_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ29_SIZE}, /* DIFFSERV_PQC10 (# 84) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2A_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2A_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2A_SIZE}, /* DIFFSERV_PQC11 (# 85) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2B_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2B_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2B_SIZE}, /* DIFFSERV_PQC12 (# 86) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2C_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2C_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2C_SIZE}, /* DIFFSERV_PQC13 (# 87) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2D_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2D_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2D_SIZE}, /* DIFFSERV_PQC14 (# 88) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2E_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2E_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2E_SIZE}, /* DIFFSERV_PQC15 (# 89) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)AR9_DFSRV_MAP2_REG_PQ2F_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2F_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP2_REG_PQ2F_SIZE}, /* DIFFSERV_PQD (# 90) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ30_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ30_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ30_SIZE}, /* DIFFSERV_PQD01 (# 91) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ31_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ31_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ31_SIZE}, /* DIFFSERV_PQD02 (# 92) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ32_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ32_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ32_SIZE}, /* DIFFSERV_PQD03 (# 93) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ33_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ33_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ33_SIZE}, /* DIFFSERV_PQD04 (# 94) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ34_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ34_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ34_SIZE}, /* DIFFSERV_PQD05 (# 95) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ35_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ35_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ35_SIZE}, /* DIFFSERV_PQD06 (# 96) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ36_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ36_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ36_SIZE}, /* DIFFSERV_PQD07 (# 97) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ37_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ37_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ37_SIZE}, /* DIFFSERV_PQD08 (# 98) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ38_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ38_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ38_SIZE}, /* DIFFSERV_PQD09 (# 99) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ39_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ39_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ39_SIZE}, /* DIFFSERV_PQD10 (# 100) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3A_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3A_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3A_SIZE}, /* DIFFSERV_PQD11 (# 101) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3B_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3B_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3B_SIZE}, /* DIFFSERV_PQD12 (# 102) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3C_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3C_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3C_SIZE}, /* DIFFSERV_PQD13 (# 103) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3D_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3D_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3D_SIZE}, /* DIFFSERV_PQD14 (# 104) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3E_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3E_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3E_SIZE}, /* DIFFSERV_PQD15 (# 105) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)AR9_DFSRV_MAP3_REG_PQ3F_OFFSET, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3F_SHIFT, (IFX_uint8_t)AR9_DFSRV_MAP3_REG_PQ3F_SIZE}, /* DOT1X_PRIORITY_1PPQ (# 106) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ0_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ0_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ0_SIZE}, /* DOT1X_PRIORITY_1PPQ1 (# 107) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ1_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ1_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ1_SIZE}, /* DOT1X_PRIORITY_1PPQ2 (# 108) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ2_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ2_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ2_SIZE}, /* DOT1X_PRIORITY_1PPQ3 (# 109) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ3_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ3_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ3_SIZE}, /* DOT1X_PRIORITY_1PPQ4 (# 110) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ4_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ4_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ4_SIZE}, /* DOT1X_PRIORITY_1PPQ5 (# 111) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ5_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ5_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ5_SIZE}, /* DOT1X_PRIORITY_1PPQ6 (# 112) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ6_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ6_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ6_SIZE}, /* DOT1X_PRIORITY_1PPQ7 (# 113) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)AR9_1P_PRT_REG_1PPQ7_OFFSET, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ7_SHIFT, (IFX_uint8_t)AR9_1P_PRT_REG_1PPQ7_SIZE}, /* GLOBAL_ATS (# 114) */ { (IFX_uint16_t)GLOBAL_ATS, (IFX_uint16_t)AR9_SW_GCTL0_REG_ATS_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_ATS_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_ATS_SIZE}, /* GLOBAL_CTTX (# 115) */ { (IFX_uint16_t)GLOBAL_CTTX, (IFX_uint16_t)AR9_SW_GCTL1_REG_CTTX_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_CTTX_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_CTTX_SIZE}, /* GLOBAL_DIE (# 116) */ { (IFX_uint16_t)GLOBAL_DIE, (IFX_uint16_t)AR9_SW_GCTL1_REG_DIE_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIE_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIE_SIZE}, /* GLOBAL_DII6P (# 117) */ { (IFX_uint16_t)GLOBAL_DII6P, (IFX_uint16_t)AR9_SW_GCTL1_REG_DII6P_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DII6P_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DII6P_SIZE}, /* GLOBAL_DIIP (# 118) */ { (IFX_uint16_t)GLOBAL_DIIP, (IFX_uint16_t)AR9_SW_GCTL1_REG_DIIP_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIIP_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIIP_SIZE}, /* GLOBAL_DIIPS (# 119) */ { (IFX_uint16_t)GLOBAL_DIIPS, (IFX_uint16_t)AR9_SW_GCTL1_REG_DIIPS_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIIPS_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIIPS_SIZE}, /* GLOBAL_DIS (# 120) */ { (IFX_uint16_t)GLOBAL_DIS, (IFX_uint16_t)AR9_SW_GCTL1_REG_DIS_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIS_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIS_SIZE}, /* GLOBAL_DIVS (# 121) */ { (IFX_uint16_t)GLOBAL_DIVS, (IFX_uint16_t)AR9_SW_GCTL1_REG_DIVS_OFFSET, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIVS_SHIFT, (IFX_uint8_t)AR9_SW_GCTL1_REG_DIVS_SIZE}, /* GLOBAL_DMQ0 (# 122) */ { (IFX_uint16_t)GLOBAL_DMQ0, (IFX_uint16_t)AR9_SW_GCTL0_REG_DMQ0_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ0_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ0_SIZE}, /* GLOBAL_DMQ1 (# 123) */ { (IFX_uint16_t)GLOBAL_DMQ1, (IFX_uint16_t)AR9_SW_GCTL0_REG_DMQ1_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ1_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ1_SIZE}, /* GLOBAL_DMQ2 (# 124) */ { (IFX_uint16_t)GLOBAL_DMQ2, (IFX_uint16_t)AR9_SW_GCTL0_REG_DMQ2_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ2_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ2_SIZE}, /* GLOBAL_DMQ3 (# 125) */ { (IFX_uint16_t)GLOBAL_DMQ3, (IFX_uint16_t)AR9_SW_GCTL0_REG_DMQ3_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ3_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_DMQ3_SIZE}, /* GLOBAL_DPWECH (# 126) */ { (IFX_uint16_t)GLOBAL_DPWECH, (IFX_uint16_t)AR9_SW_GCTL0_REG_DPWECH_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_DPWECH_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_DPWECH_SIZE}, /* GLOBAL_DUPCOLSP (# 127) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_ICRCCD (# 128) */ { (IFX_uint16_t)GLOBAL_ICRCCD, (IFX_uint16_t)AR9_SW_GCTL0_REG_ICRCCD_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_ICRCCD_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_ICRCCD_SIZE}, /* GLOBAL_ITENLMT (# 129) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_ITRUNK (# 130) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_LPE (# 131) */ { (IFX_uint16_t)GLOBAL_LPE, (IFX_uint16_t)AR9_SW_GCTL0_REG_LPE_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_LPE_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_LPE_SIZE}, /* GLOBAL_MPL (# 132) */ { (IFX_uint16_t)GLOBAL_MPL, (IFX_uint16_t)AR9_SW_GCTL0_REG_MPL_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MPL_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MPL_SIZE}, /* GLOBAL_P4M (# 133) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_P5M (# 134) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_P6M (# 135) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_PCE (# 136) */ { (IFX_uint16_t)GLOBAL_PCE, (IFX_uint16_t)AR9_SW_GCTL0_REG_PCE_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_PCE_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_PCE_SIZE}, /* GLOBAL_PCR (# 137) */ { (IFX_uint16_t)GLOBAL_PCR, (IFX_uint16_t)AR9_SW_GCTL0_REG_PCR_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_PCR_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_PCR_SIZE}, /* GLOBAL_PHYBA (# 138) */ { (IFX_uint16_t)GLOBAL_PHYBA, (IFX_uint16_t)AR9_SW_GCTL0_REG_PHYBA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_PHYBA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_PHYBA_SIZE}, /* GLOBAL_RVID0 (# 139) */ { (IFX_uint16_t)GLOBAL_RVID0, (IFX_uint16_t)AR9_SW_GCTL0_REG_RVID0_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVID0_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVID0_SIZE}, /* GLOBAL_RVID1 (# 140) */ { (IFX_uint16_t)GLOBAL_RVID1, (IFX_uint16_t)AR9_SW_GCTL0_REG_RVID1_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVID1_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVID1_SIZE}, /* GLOBAL_RVIDFFF (# 141) */ { (IFX_uint16_t)GLOBAL_RVIDFFF, (IFX_uint16_t)AR9_SW_GCTL0_REG_RVIDFFF_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVIDFFF_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_RVIDFFF_SIZE}, /* GLOBAL_SE (# 142) */ { (IFX_uint16_t)GLOBAL_SE, (IFX_uint16_t)AR9_SW_GCTL0_REG_SE_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_SE_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_SE_SIZE}, /* GLOBAL_TSIPGE (# 143) */ { (IFX_uint16_t)GLOBAL_TSIPGE, (IFX_uint16_t)AR9_SW_GCTL0_REG_TSIPGE_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_TSIPGE_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_TSIPGE_SIZE}, /* INGRESS_FLOW_CTRL_B (# 144) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_B, (IFX_uint16_t)AR9_PAUSE_OFF_WM_B_OFFSET, (IFX_uint8_t)AR9_PAUSE_OFF_WM_B_SHIFT, (IFX_uint8_t)AR9_PAUSE_OFF_WM_B_SIZE}, /* INGRESS_FLOW_CTRL_BASE15_0 (# 145) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* INGRESS_FLOW_CTRL_BASE17_16 (# 146) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* INGRESS_FLOW_CTRL_EBASE15_0 (# 147) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* INGRESS_FLOW_CTRL_EBASE17_16 (# 148) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* INGRESS_FLOW_CTRL_F (# 149) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_F, (IFX_uint16_t)AR9_PAUSE_ON_WM_F_OFFSET, (IFX_uint8_t)AR9_PAUSE_ON_WM_F_SHIFT, (IFX_uint8_t)AR9_PAUSE_ON_WM_F_SIZE}, /* IRQ_DBF (# 150) */ { (IFX_uint16_t)IRQ_DBF, (IFX_uint16_t)AR9_INT_ST_REG_DBF_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_DBF_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_DBF_SIZE}, /* IRQ_DBFIE (# 151) */ { (IFX_uint16_t)IRQ_DBFIE, (IFX_uint16_t)AR9_INT_ENA_REG_DBFIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_DBFIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_DBFIE_SIZE}, /* IRQ_DBNF (# 152) */ { (IFX_uint16_t)IRQ_DBNF, (IFX_uint16_t)AR9_INT_ST_REG_DBNF_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_DBNF_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_DBNF_SIZE}, /* IRQ_DBNFIE (# 153) */ { (IFX_uint16_t)IRQ_DBNFIE, (IFX_uint16_t)AR9_INT_ENA_REG_DBNFIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_DBNFIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_DBNFIE_SIZE}, /* IRQ_LTAD (# 154) */ { (IFX_uint16_t)IRQ_LTAD, (IFX_uint16_t)AR9_INT_ST_REG_LTAD_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_LTAD_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_LTAD_SIZE}, /* IRQ_LTADIE (# 155) */ { (IFX_uint16_t)IRQ_LTADIE, (IFX_uint16_t)AR9_INT_ENA_REG_LTADIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_LTADIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_LTADIE_SIZE}, /* IRQ_LTF (# 156) */ { (IFX_uint16_t)IRQ_LTF, (IFX_uint16_t)AR9_INT_ST_REG_LTF_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_LTF_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_LTF_SIZE}, /* IRQ_LTFIE (# 157) */ { (IFX_uint16_t)IRQ_LTFIE, (IFX_uint16_t)AR9_INT_ENA_REG_LTFIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_LTFIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_LTFIE_SIZE}, /* IRQ_PSC (# 158) */ { (IFX_uint16_t)IRQ_PSC, (IFX_uint16_t)AR9_INT_ST_REG_PSC_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_PSC_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_PSC_SIZE}, /* IRQ_PSCIE (# 159) */ { (IFX_uint16_t)IRQ_PSCIE, (IFX_uint16_t)AR9_INT_ENA_REG_PSCIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_PSCIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_PSCIE_SIZE}, /* IRQ_PSV (# 160) */ { (IFX_uint16_t)IRQ_PSV, (IFX_uint16_t)AR9_INT_ST_REG_PSV_OFFSET, (IFX_uint8_t)AR9_INT_ST_REG_PSV_SHIFT, (IFX_uint8_t)AR9_INT_ST_REG_PSV_SIZE}, /* IRQ_PSVIE (# 161) */ { (IFX_uint16_t)IRQ_PSVIE, (IFX_uint16_t)AR9_INT_ENA_REG_PSVIE_OFFSET, (IFX_uint8_t)AR9_INT_ENA_REG_PSVIE_SHIFT, (IFX_uint8_t)AR9_INT_ENA_REG_PSVIE_SIZE}, /* MAC_TABLE_ADDR15_0 (# 162) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDR31_0 (# 163) */ { (IFX_uint16_t)MAC_TABLE_ADDR31_0, (IFX_uint16_t)AR9_ADR_TB_CTL0_REG_ADDR31_0_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL0_REG_ADDR31_0_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL0_REG_ADDR31_0_SIZE}, /* MAC_TABLE_ADDR31_16 (# 164) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDR47_32 (# 165) */ { (IFX_uint16_t)MAC_TABLE_ADDR47_32, (IFX_uint16_t)AR9_ADR_TB_CTL1_REG_ADDR47_32_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_ADDR47_32_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_ADDR47_32_SIZE}, /* MAC_TABLE_ADDRS15_0 (# 166) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDRS31_0 (# 167) */ { (IFX_uint16_t)MAC_TABLE_ADDRS31_0, (IFX_uint16_t)AR9_ADR_TB_ST0_REG_ADDRS31_0_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST0_REG_ADDRS31_0_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST0_REG_ADDRS31_0_SIZE}, /* MAC_TABLE_ADDRS31_16 (# 168) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDRS47_32 (# 169) */ { (IFX_uint16_t)MAC_TABLE_ADDRS47_32, (IFX_uint16_t)AR9_ADR_TB_ST1_REG_ADDRS47_32_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_ADDRS47_32_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_ADDRS47_32_SIZE}, /* MAC_TABLE_BAD (# 170) */ { (IFX_uint16_t)MAC_TABLE_BAD, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_BAD_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_BAD_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_BAD_SIZE}, /* MAC_TABLE_BUSY (# 171) */ { (IFX_uint16_t)MAC_TABLE_BUSY, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_BUSY_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_BUSY_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_BUSY_SIZE}, /* MAC_TABLE_C_AC (# 172) */ { (IFX_uint16_t)MAC_TABLE_C_AC, (IFX_uint16_t)AR9_ADR_TB_CTL2_REG_AC_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_AC_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_AC_SIZE}, /* MAC_TABLE_C_CMD (# 173) */ { (IFX_uint16_t)MAC_TABLE_C_CMD, (IFX_uint16_t)AR9_ADR_TB_CTL2_REG_CMD_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_CMD_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_CMD_SIZE}, /* MAC_TABLE_C_FCE (# 174) */ { (IFX_uint16_t)MAC_TABLE_C_FCE, (IFX_uint16_t)AR9_ADR_TB_CTL2_REG_IFCE_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_IFCE_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_IFCE_SIZE}, /* MAC_TABLE_FID (# 175) */ { (IFX_uint16_t)MAC_TABLE_FID, (IFX_uint16_t)AR9_ADR_TB_CTL1_REG_FID_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_FID_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_FID_SIZE}, /* MAC_TABLE_FIDS (# 176) */ { (IFX_uint16_t)MAC_TABLE_FIDS, (IFX_uint16_t)AR9_ADR_TB_ST1_REG_FIDS_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_FIDS_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_FIDS_SIZE}, /* MAC_TABLE_INFOT (# 177) */ { (IFX_uint16_t)MAC_TABLE_INFOT, (IFX_uint16_t)AR9_ADR_TB_CTL2_REG_INFOT_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_INFOT_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_INFOT_SIZE}, /* MAC_TABLE_INFOTS (# 178) */ { (IFX_uint16_t)MAC_TABLE_INFOTS, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_INFOTS_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_INFOTS_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_INFOTS_SIZE}, /* MAC_TABLE_ITAT (# 179) */ { (IFX_uint16_t)MAC_TABLE_ITAT, (IFX_uint16_t)AR9_ADR_TB_CTL2_REG_ITAT_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_ITAT_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL2_REG_ITAT_SIZE}, /* MAC_TABLE_ITATS (# 180) */ { (IFX_uint16_t)MAC_TABLE_ITATS, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_ITATS_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_ITATS_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_ITATS_SIZE}, /* MAC_TABLE_OCP (# 181) */ { (IFX_uint16_t)MAC_TABLE_OCP, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_OCP_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_OCP_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_OCP_SIZE}, /* MAC_TABLE_PMAP (# 182) */ { (IFX_uint16_t)MAC_TABLE_PMAP, (IFX_uint16_t)AR9_ADR_TB_CTL1_REG_PMAP_OFFSET, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_PMAP_SHIFT, (IFX_uint8_t)AR9_ADR_TB_CTL1_REG_PMAP_SIZE}, /* MAC_TABLE_PMAPS (# 183) */ { (IFX_uint16_t)MAC_TABLE_PMAPS, (IFX_uint16_t)AR9_ADR_TB_ST1_REG_PMAPS_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_PMAPS_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST1_REG_PMAPS_SIZE}, /* MAC_TABLE_RSLT (# 184) */ { (IFX_uint16_t)MAC_TABLE_RSLT, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_RSLT_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_RSLT_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_RSLT_SIZE}, /* MAC_TABLE_S_AC (# 185) */ { (IFX_uint16_t)MAC_TABLE_S_AC, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_AC_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_AC_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_AC_SIZE}, /* MAC_TABLE_S_CMD (# 186) */ { (IFX_uint16_t)MAC_TABLE_S_CMD, (IFX_uint16_t)AR9_ADR_TB_ST2_REG_CMD_OFFSET, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_CMD_SHIFT, (IFX_uint8_t)AR9_ADR_TB_ST2_REG_CMD_SIZE}, /* MAC_TABLE_S_FCE (# 187) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MCS (# 188) */ { (IFX_uint16_t)MCS, (IFX_uint16_t)AR9_RGMII_CTL_REG_MCS_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_MCS_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_MCS_SIZE}, /* MDIO_MBUSY (# 189) */ { (IFX_uint16_t)MDIO_MBUSY, (IFX_uint16_t)AR9_MDIO_CTL_REG_MBUSY_OFFSET, (IFX_uint8_t)AR9_MDIO_CTL_REG_MBUSY_SHIFT, (IFX_uint8_t)AR9_MDIO_CTL_REG_MBUSY_SIZE}, /* MDIO_OP (# 190) */ { (IFX_uint16_t)MDIO_OP, (IFX_uint16_t)AR9_MDIO_CTL_REG_OP_OFFSET, (IFX_uint8_t)AR9_MDIO_CTL_REG_OP_SHIFT, (IFX_uint8_t)AR9_MDIO_CTL_REG_OP_SIZE}, /* MDIO_PHYAD (# 191) */ { (IFX_uint16_t)MDIO_PHYAD, (IFX_uint16_t)AR9_MDIO_CTL_REG_PHYAD_OFFSET, (IFX_uint8_t)AR9_MDIO_CTL_REG_PHYAD_SHIFT, (IFX_uint8_t)AR9_MDIO_CTL_REG_PHYAD_SIZE}, /* MDIO_RD (# 192) */ { (IFX_uint16_t)MDIO_RD, (IFX_uint16_t)AR9_MDIO_DATA_REG_RD_OFFSET, (IFX_uint8_t)AR9_MDIO_DATA_REG_RD_SHIFT, (IFX_uint8_t)AR9_MDIO_DATA_REG_RD_SIZE}, /* MDIO_REGAD (# 193) */ { (IFX_uint16_t)MDIO_REGAD, (IFX_uint16_t)AR9_MDIO_CTL_REG_REGAD_OFFSET, (IFX_uint8_t)AR9_MDIO_CTL_REG_REGAD_SHIFT, (IFX_uint8_t)AR9_MDIO_CTL_REG_REGAD_SIZE}, /* MDIO_WD (# 194) */ { (IFX_uint16_t)MDIO_WD, (IFX_uint16_t)AR9_MDIO_CTL_REG_WD_OFFSET, (IFX_uint8_t)AR9_MDIO_CTL_REG_WD_SHIFT, (IFX_uint8_t)AR9_MDIO_CTL_REG_WD_SIZE}, /* MIRROR_CCCRC (# 195) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MIRROR_CPN (# 196) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MIRROR_IGSTA (# 197) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MIRROR_MCA (# 198) */ { (IFX_uint16_t)MIRROR_MCA, (IFX_uint16_t)AR9_SW_GCTL0_REG_MCA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MCA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MCA_SIZE}, /* MIRROR_MLA (# 199) */ { (IFX_uint16_t)MIRROR_MLA, (IFX_uint16_t)AR9_SW_GCTL0_REG_MLA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MLA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MLA_SIZE}, /* MIRROR_MPA (# 200) */ { (IFX_uint16_t)MIRROR_MPA, (IFX_uint16_t)AR9_SW_GCTL0_REG_MPA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MPA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MPA_SIZE}, /* MIRROR_MRA (# 201) */ { (IFX_uint16_t)MIRROR_MRA, (IFX_uint16_t)AR9_SW_GCTL0_REG_MRA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MRA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MRA_SIZE}, /* MIRROR_MSA (# 202) */ { (IFX_uint16_t)MIRROR_MSA, (IFX_uint16_t)AR9_SW_GCTL0_REG_MSA_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_MSA_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_MSA_SIZE}, /* MIRROR_PAST (# 203) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MIRROR_SNIFFPN (# 204) */ { (IFX_uint16_t)MIRROR_SNIFFPN, (IFX_uint16_t)AR9_SW_GCTL0_REG_SNIFFPN_OFFSET, (IFX_uint8_t)AR9_SW_GCTL0_REG_SNIFFPN_SHIFT, (IFX_uint8_t)AR9_SW_GCTL0_REG_SNIFFPN_SIZE}, /* MIRROR_STRE (# 205) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MIRROR_STTE (# 206) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_ASC (# 207) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_B01 (# 208) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_B224 (# 209) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_B33 (# 210) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_DAIPS (# 211) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_DRP (# 212) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_FMODE (# 213) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_GID15_0 (# 214) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_GID31_16 (# 215) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_HIPI (# 216) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_HISE (# 217) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_HISFL (# 218) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_ICMD (# 219) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_IGMPV3E (# 220) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_INVC (# 221) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_IPMPT (# 222) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_PORT (# 223) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_PPPOEHR (# 224) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_QI (# 225) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_RV (# 226) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_S3PMI (# 227) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_S3PMV (# 228) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_S4BUSY (# 229) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_S4R (# 230) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SARE (# 231) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPA (# 232) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPP (# 233) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPPE (# 234) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPTCP (# 235) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPTMP (# 236) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPTSP (# 237) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SCPTTH (# 238) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIP15_0 (# 239) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIP31_16 (# 240) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIP47_32 (# 241) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIPGID0 (# 242) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIPGID1 (# 243) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_SIPGID2 (# 244) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MULTICAST_TIMERC (# 245) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PAUSE_ADDR15_0 (# 246) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PAUSE_ADDR31_16 (# 247) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PAUSE_ADDR39_32 (# 248) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PAUSE_ADDR47_41 (# 249) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PAUSE_PAC (# 250) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE0 (# 251) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE01 (# 252) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE02 (# 253) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE03 (# 254) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE1 (# 255) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE11 (# 256) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE12 (# 257) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE13 (# 258) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE2 (# 259) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE21 (# 260) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE22 (# 261) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE23 (# 262) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE3 (# 263) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE31 (# 264) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE32 (# 265) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE33 (# 266) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE4 (# 267) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE41 (# 268) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE42 (# 269) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE43 (# 270) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE5 (# 271) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE51 (# 272) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE52 (# 273) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE53 (# 274) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE6 (# 275) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE61 (# 276) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE62 (# 277) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_PHYIE63 (# 278) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGA (# 279) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGA1 (# 280) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGA2 (# 281) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGA3 (# 282) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGD (# 283) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGD1 (# 284) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGD2 (# 285) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PHY_INIT_REGD3 (# 286) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_ADD (# 287) */ { (IFX_uint16_t)PMAC_ADD, (IFX_uint16_t)AR9_PMAC_HD_CTL_ADD_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_ADD_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_ADD_SIZE}, /* PMAC_ADD_CRC (# 288) */ { (IFX_uint16_t)PMAC_ADD_CRC, (IFX_uint16_t)AR9_PMAC_HD_CTL_AC_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_AC_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_AC_SIZE}, /* PMAC_AS (# 289) */ { (IFX_uint16_t)PMAC_AS, (IFX_uint16_t)AR9_PMAC_HD_CTL_AS_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_AS_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_AS_SIZE}, /* PMAC_CFI (# 290) */ { (IFX_uint16_t)PMAC_CFI, (IFX_uint16_t)AR9_PMAC_VLAN_CFI_OFFSET, (IFX_uint8_t)AR9_PMAC_VLAN_CFI_SHIFT, (IFX_uint8_t)AR9_PMAC_VLAN_CFI_SIZE}, /* PMAC_DA_31_0 (# 291) */ { (IFX_uint16_t)PMAC_DA_31_0, (IFX_uint16_t)AR9_PMAC_DA2_DA_31_0_OFFSET, (IFX_uint8_t)AR9_PMAC_DA2_DA_31_0_SHIFT, (IFX_uint8_t)AR9_PMAC_DA2_DA_31_0_SIZE}, /* PMAC_DA_47_32 (# 292) */ { (IFX_uint16_t)PMAC_DA_47_32, (IFX_uint16_t)AR9_PMAC_DA1_DA_47_32_OFFSET, (IFX_uint8_t)AR9_PMAC_DA1_DA_47_32_SHIFT, (IFX_uint8_t)AR9_PMAC_DA1_DA_47_32_SIZE}, /* PMAC_IDIS_REQ_WM (# 293) */ { (IFX_uint16_t)PMAC_IDIS_REQ_WM, (IFX_uint16_t)AR9_PMAC_RX_IPG_IDIS_REQ_WM_OFFSET, (IFX_uint8_t)AR9_PMAC_RX_IPG_IDIS_REQ_WM_SHIFT, (IFX_uint8_t)AR9_PMAC_RX_IPG_IDIS_REQ_WM_SIZE}, /* PMAC_IPG_RX_CNT (# 294) */ { (IFX_uint16_t)PMAC_IPG_RX_CNT, (IFX_uint16_t)AR9_PMAC_RX_IPG_IPG_CNT_OFFSET, (IFX_uint8_t)AR9_PMAC_RX_IPG_IPG_CNT_SHIFT, (IFX_uint8_t)AR9_PMAC_RX_IPG_IPG_CNT_SIZE}, /* PMAC_IPG_TX_CNT (# 295) */ { (IFX_uint16_t)PMAC_IPG_TX_CNT, (IFX_uint16_t)AR9_PMAC_TX_IPG_IPG_CNT_OFFSET, (IFX_uint8_t)AR9_PMAC_TX_IPG_IPG_CNT_SHIFT, (IFX_uint8_t)AR9_PMAC_TX_IPG_IPG_CNT_SIZE}, /* PMAC_IREQ_WM (# 296) */ { (IFX_uint16_t)PMAC_IREQ_WM, (IFX_uint16_t)AR9_PMAC_RX_IPG_IREQ_WM_OFFSET, (IFX_uint8_t)AR9_PMAC_RX_IPG_IREQ_WM_SHIFT, (IFX_uint8_t)AR9_PMAC_RX_IPG_IREQ_WM_SIZE}, /* PMAC_PRI (# 297) */ { (IFX_uint16_t)PMAC_PRI, (IFX_uint16_t)AR9_PMAC_VLAN_PRI_OFFSET, (IFX_uint8_t)AR9_PMAC_VLAN_PRI_SHIFT, (IFX_uint8_t)AR9_PMAC_VLAN_PRI_SIZE}, /* PMAC_RC (# 298) */ { (IFX_uint16_t)PMAC_RC, (IFX_uint16_t)AR9_PMAC_HD_CTL_RC_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_RC_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_RC_SIZE}, /* PMAC_RL2 (# 299) */ { (IFX_uint16_t)PMAC_RL2, (IFX_uint16_t)AR9_PMAC_HD_CTL_RL2_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_RL2_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_RL2_SIZE}, /* PMAC_RXSH (# 300) */ { (IFX_uint16_t)PMAC_RXSH, (IFX_uint16_t)AR9_PMAC_HD_CTL_RXSH_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_RXSH_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_RXSH_SIZE}, /* PMAC_SA_31_0 (# 301) */ { (IFX_uint16_t)PMAC_SA_31_0, (IFX_uint16_t)AR9_PMAC_SA2_SA_31_0_OFFSET, (IFX_uint8_t)AR9_PMAC_SA2_SA_31_0_SHIFT, (IFX_uint8_t)AR9_PMAC_SA2_SA_31_0_SIZE}, /* PMAC_SA_47_32 (# 302) */ { (IFX_uint16_t)PMAC_SA_47_32, (IFX_uint16_t)AR9_PMAC_SA1_SA_47_32_OFFSET, (IFX_uint8_t)AR9_PMAC_SA1_SA_47_32_SHIFT, (IFX_uint8_t)AR9_PMAC_SA1_SA_47_32_SIZE}, /* PMAC_TAG (# 303) */ { (IFX_uint16_t)PMAC_TAG, (IFX_uint16_t)AR9_PMAC_HD_CTL_TAG_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_TAG_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_TAG_SIZE}, /* PMAC_TYPE_LEN (# 304) */ { (IFX_uint16_t)PMAC_TYPE_LEN, (IFX_uint16_t)AR9_PMAC_HD_CTL_TYPE_LEN_OFFSET, (IFX_uint8_t)AR9_PMAC_HD_CTL_TYPE_LEN_SHIFT, (IFX_uint8_t)AR9_PMAC_HD_CTL_TYPE_LEN_SIZE}, /* PMAC_VLAN ID (# 305) */ { (IFX_uint16_t)PMAC_VLAN_ID, (IFX_uint16_t)AR9_PMAC_VLAN_VLAN_ID_OFFSET, (IFX_uint8_t)AR9_PMAC_VLAN_VLAN_ID_SHIFT, (IFX_uint8_t)AR9_PMAC_VLAN_VLAN_ID_SIZE}, /* PORT_AD (# 306) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)AR9_P0_CTL_REG_AD_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_AD_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_AD_SIZE}, /* PORT_AD1 (# 307) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)AR9_P1_CTL_REG_AD_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_AD_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_AD_SIZE}, /* PORT_AD2 (# 308) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)AR9_P2_CTL_REG_AD_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_AD_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_AD_SIZE}, /* PORT_AD3 (# 309) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_AD4 (# 310) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_AD5 (# 311) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_AD6 (# 312) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_BP (# 313) */ { (IFX_uint16_t)PORT_BP, (IFX_uint16_t)AR9_DF_PORTMAP_REG_BP_OFFSET, (IFX_uint8_t)AR9_DF_PORTMAP_REG_BP_SHIFT, (IFX_uint8_t)AR9_DF_PORTMAP_REG_BP_SIZE}, /* PORT_DFWD (# 314) */ { (IFX_uint16_t)PORT_DFWD, (IFX_uint16_t)AR9_P0_CTL_REG_DFWD_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_DFWD_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_DFWD_SIZE}, /* PORT_DFWD1 (# 315) */ { (IFX_uint16_t)PORT_DFWD, (IFX_uint16_t)AR9_P1_CTL_REG_DFWD_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_DFWD_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_DFWD_SIZE}, /* PORT_DFWD2 (# 316) */ { (IFX_uint16_t)PORT_DFWD, (IFX_uint16_t)AR9_P2_CTL_REG_DFWD_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_DFWD_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_DFWD_SIZE}, /* PORT_DSV821X (# 317) */ { (IFX_uint16_t)PORT_DSV821X, (IFX_uint16_t)AR9_P0_CTL_REG_DSV8021X_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_DSV8021X_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_DSV8021X_SIZE}, /* PORT_DSV821X1 (# 318) */ { (IFX_uint16_t)PORT_DSV821X, (IFX_uint16_t)AR9_P1_CTL_REG_DSV8021X_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_DSV8021X_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_DSV8021X_SIZE}, /* PORT_DSV821X2 (# 319) */ { (IFX_uint16_t)PORT_DSV821X, (IFX_uint16_t)AR9_P2_CTL_REG_DSV8021X_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_DSV8021X_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_DSV8021X_SIZE}, /* PORT_EGRESS_PSPQ0TR (# 320) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)AR9_P0_ECS_Q10_REG_P0SPQ0TR_OFFSET, (IFX_uint8_t)AR9_P0_ECS_Q10_REG_P0SPQ0TR_SHIFT, (IFX_uint8_t)AR9_P0_ECS_Q10_REG_P0SPQ0TR_SIZE}, /* PORT_EGRESS_PSPQ0TR1 (# 321) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)AR9_P1_ECS_Q10_REG_P0SPQ0TR_OFFSET, (IFX_uint8_t)AR9_P1_ECS_Q10_REG_P0SPQ0TR_SHIFT, (IFX_uint8_t)AR9_P1_ECS_Q10_REG_P0SPQ0TR_SIZE}, /* PORT_EGRESS_PSPQ0TR2 (# 322) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)AR9_P2_ECS_Q10_REG_P0SPQ0TR_OFFSET, (IFX_uint8_t)AR9_P2_ECS_Q10_REG_P0SPQ0TR_SHIFT, (IFX_uint8_t)AR9_P2_ECS_Q10_REG_P0SPQ0TR_SIZE}, /* PORT_EGRESS_PSPQ0TR3 (# 323) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ0TR4 (# 324) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ0TR5 (# 325) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ0TR6 (# 326) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ1TR (# 327) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR , (IFX_uint16_t)AR9_P0_ECS_Q10_REG_P0SPQ1TR_OFFSET, (IFX_uint8_t)AR9_P0_ECS_Q10_REG_P0SPQ1TR_SHIFT, (IFX_uint8_t)AR9_P0_ECS_Q10_REG_P0SPQ1TR_SIZE}, /* PORT_EGRESS_PSPQ1TR1 (# 328) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)AR9_P1_ECS_Q10_REG_P0SPQ1TR_OFFSET, (IFX_uint8_t)AR9_P1_ECS_Q10_REG_P0SPQ1TR_SHIFT, (IFX_uint8_t)AR9_P1_ECS_Q10_REG_P0SPQ1TR_SIZE}, /* PORT_EGRESS_PSPQ1TR2 (# 329) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)AR9_P2_ECS_Q10_REG_P0SPQ1TR_OFFSET, (IFX_uint8_t)AR9_P2_ECS_Q10_REG_P0SPQ1TR_SHIFT, (IFX_uint8_t)AR9_P2_ECS_Q10_REG_P0SPQ1TR_SIZE}, /* PORT_EGRESS_PSPQ1TR3 (# 330) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ1TR4 (# 331) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ1TR5 (# 332) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ1TR6 (# 333) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ2TR (# 334) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)AR9_P0_ECS_Q32_REG_P0SPQ2TR_OFFSET, (IFX_uint8_t)AR9_P0_ECS_Q32_REG_P0SPQ2TR_SHIFT, (IFX_uint8_t)AR9_P0_ECS_Q32_REG_P0SPQ2TR_SIZE}, /* PORT_EGRESS_PSPQ2TR1 (# 335) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)AR9_P1_ECS_Q32_REG_P0SPQ2TR_OFFSET, (IFX_uint8_t)AR9_P1_ECS_Q32_REG_P0SPQ2TR_SHIFT, (IFX_uint8_t)AR9_P1_ECS_Q32_REG_P0SPQ2TR_SIZE}, /* PORT_EGRESS_PSPQ2TR2 (# 336) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)AR9_P2_ECS_Q32_REG_P0SPQ2TR_OFFSET, (IFX_uint8_t)AR9_P2_ECS_Q32_REG_P0SPQ2TR_SHIFT, (IFX_uint8_t)AR9_P2_ECS_Q32_REG_P0SPQ2TR_SIZE}, /* PORT_EGRESS_PSPQ2TR3 (# 337) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ2TR4 (# 338) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ2TR5 (# 339) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ2TR6 (# 340) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ3TR (# 341) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)AR9_P0_ECS_Q32_REG_P0SPQ3TR_OFFSET, (IFX_uint8_t)AR9_P0_ECS_Q32_REG_P0SPQ3TR_SHIFT, (IFX_uint8_t)AR9_P0_ECS_Q32_REG_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR1 (# 342) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)AR9_P1_ECS_Q32_REG_P0SPQ3TR_OFFSET, (IFX_uint8_t)AR9_P1_ECS_Q32_REG_P0SPQ3TR_SHIFT, (IFX_uint8_t)AR9_P1_ECS_Q32_REG_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR2 (# 343) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)AR9_P2_ECS_Q32_REG_P0SPQ3TR_OFFSET, (IFX_uint8_t)AR9_P2_ECS_Q32_REG_P0SPQ3TR_SHIFT, (IFX_uint8_t)AR9_P2_ECS_Q32_REG_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR3 (# 344) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ3TR4 (# 345) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ3TR5 (# 346) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ3TR6 (# 347) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ0TR (# 348) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)AR9_P0_ECW_Q10_REG_P0WQ0TR_OFFSET, (IFX_uint8_t)AR9_P0_ECW_Q10_REG_P0WQ0TR_SHIFT, (IFX_uint8_t)AR9_P0_ECW_Q10_REG_P0WQ0TR_SIZE}, /* PORT_EGRESS_PWQ0TR1 (# 349) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)AR9_P1_ECW_Q10_REG_P1WQ0TR_OFFSET, (IFX_uint8_t)AR9_P1_ECW_Q10_REG_P1WQ0TR_SHIFT, (IFX_uint8_t)AR9_P1_ECW_Q10_REG_P1WQ0TR_SIZE}, /* PORT_EGRESS_PWQ0TR2 (# 350) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)AR9_P2_ECW_Q10_REG_P2WQ0TR_OFFSET, (IFX_uint8_t)AR9_P2_ECW_Q10_REG_P2WQ0TR_SHIFT, (IFX_uint8_t)AR9_P2_ECW_Q10_REG_P2WQ0TR_SIZE}, /* PORT_EGRESS_PWQ0TR3 (# 351) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ0TR4 (# 352) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ0TR5 (# 353) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ0TR6 (# 354) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ1TR (# 355) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ1TR1 (# 356) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)AR9_P0_ECW_Q10_REG_P0WQ1TR_OFFSET, (IFX_uint8_t)AR9_P0_ECW_Q10_REG_P0WQ1TR_SHIFT, (IFX_uint8_t)AR9_P0_ECW_Q10_REG_P0WQ1TR_SIZE}, /* PORT_EGRESS_PWQ1TR2 (# 357) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)AR9_P2_ECW_Q10_REG_P2WQ1TR_OFFSET, (IFX_uint8_t)AR9_P2_ECW_Q10_REG_P2WQ1TR_SHIFT, (IFX_uint8_t)AR9_P2_ECW_Q10_REG_P2WQ1TR_SIZE}, /* PORT_EGRESS_PWQ1TR3 (# 358) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ1TR4 (# 359) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ1TR5 (# 360) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ1TR6 (# 361) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ2TR (# 362) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)AR9_P0_ECW_Q32_REG_P0WQ2TR_OFFSET, (IFX_uint8_t)AR9_P0_ECW_Q32_REG_P0WQ2TR_SHIFT, (IFX_uint8_t)AR9_P0_ECW_Q32_REG_P0WQ2TR_SIZE}, /* PORT_EGRESS_PWQ2TR1 (# 363) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)AR9_P1_ECW_Q32_REG_P1WQ2TR_OFFSET, (IFX_uint8_t)AR9_P1_ECW_Q32_REG_P1WQ2TR_SHIFT, (IFX_uint8_t)AR9_P1_ECW_Q32_REG_P1WQ2TR_SIZE}, /* PORT_EGRESS_PWQ2TR2 (# 364) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)AR9_P2_ECW_Q32_REG_P2WQ2TR_OFFSET, (IFX_uint8_t)AR9_P2_ECW_Q32_REG_P2WQ2TR_SHIFT, (IFX_uint8_t)AR9_P2_ECW_Q32_REG_P2WQ2TR_SIZE}, /* PORT_EGRESS_PWQ2TR3 (# 365) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ2TR4 (# 366) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ2TR5 (# 367) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ2TR6 (# 368) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ3TR (# 369) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)AR9_P0_ECW_Q32_REG_P0WQ3TR_OFFSET, (IFX_uint8_t)AR9_P0_ECW_Q32_REG_P0WQ3TR_SHIFT, (IFX_uint8_t)AR9_P0_ECW_Q32_REG_P0WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR1 (# 370) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)AR9_P1_ECW_Q32_REG_P1WQ3TR_OFFSET, (IFX_uint8_t)AR9_P1_ECW_Q32_REG_P1WQ3TR_SHIFT, (IFX_uint8_t)AR9_P1_ECW_Q32_REG_P1WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR2 (# 371) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)AR9_P2_ECW_Q32_REG_P2WQ3TR_OFFSET, (IFX_uint8_t)AR9_P2_ECW_Q32_REG_P2WQ3TR_SHIFT, (IFX_uint8_t)AR9_P2_ECW_Q32_REG_P2WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR3 (# 372) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ3TR4 (# 373) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ3TR5 (# 374) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PWQ3TR6 (# 375) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FILTER_ATUF (# 376) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF0_REG_ATUF0_OFFSET, (IFX_uint8_t)AR9_TCP_PF0_REG_ATUF0_SHIFT, (IFX_uint8_t)AR9_TCP_PF0_REG_ATUF0_SIZE}, /* PORT_FILTER_ATUF1 (# 377) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF1_REG_ATUF1_OFFSET, (IFX_uint8_t)AR9_TCP_PF1_REG_ATUF1_SHIFT, (IFX_uint8_t)AR9_TCP_PF1_REG_ATUF1_SIZE}, /* PORT_FILTER_ATUF2 (# 378) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF2_REG_ATUF2_OFFSET, (IFX_uint8_t)AR9_TCP_PF2_REG_ATUF2_SHIFT, (IFX_uint8_t)AR9_TCP_PF2_REG_ATUF2_SIZE}, /* PORT_FILTER_ATUF3 (# 379) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF3_REG_ATUF3_OFFSET, (IFX_uint8_t)AR9_TCP_PF3_REG_ATUF3_SHIFT, (IFX_uint8_t)AR9_TCP_PF3_REG_ATUF3_SIZE}, /* PORT_FILTER_ATUF4 (# 380) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF4_REG_ATUF4_OFFSET, (IFX_uint8_t)AR9_TCP_PF4_REG_ATUF4_SHIFT, (IFX_uint8_t)AR9_TCP_PF4_REG_ATUF4_SIZE}, /* PORT_FILTER_ATUF5 (# 381) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF5_REG_ATUF5_OFFSET, (IFX_uint8_t)AR9_TCP_PF5_REG_ATUF5_SHIFT, (IFX_uint8_t)AR9_TCP_PF5_REG_ATUF5_SIZE}, /* PORT_FILTER_ATUF6 (# 382) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF6_REG_ATUF6_OFFSET, (IFX_uint8_t)AR9_TCP_PF6_REG_ATUF6_SHIFT, (IFX_uint8_t)AR9_TCP_PF6_REG_ATUF6_SIZE}, /* PORT_FILTER_ATUF7 (# 383) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)AR9_TCP_PF7_REG_ATUF7_OFFSET, (IFX_uint8_t)AR9_TCP_PF7_REG_ATUF7_SHIFT, (IFX_uint8_t)AR9_TCP_PF7_REG_ATUF7_SIZE}, /* PORT_FILTER_BASEPT (# 384) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF0_REG_BASEPT0_OFFSET, (IFX_uint8_t)AR9_TCP_PF0_REG_BASEPT0_SHIFT, (IFX_uint8_t)AR9_TCP_PF0_REG_BASEPT0_SIZE}, /* PORT_FILTER_BASEPT1 (# 385) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF1_REG_BASEPT1_OFFSET, (IFX_uint8_t)AR9_TCP_PF1_REG_BASEPT1_SHIFT, (IFX_uint8_t)AR9_TCP_PF1_REG_BASEPT1_SIZE}, /* PORT_FILTER_BASEPT2 (# 386) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF2_REG_BASEPT2_OFFSET, (IFX_uint8_t)AR9_TCP_PF2_REG_BASEPT2_SHIFT, (IFX_uint8_t)AR9_TCP_PF2_REG_BASEPT2_SIZE}, /* PORT_FILTER_BASEPT3 (# 387) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF3_REG_BASEPT3_OFFSET, (IFX_uint8_t)AR9_TCP_PF3_REG_BASEPT3_SHIFT, (IFX_uint8_t)AR9_TCP_PF3_REG_BASEPT3_SIZE}, /* PORT_FILTER_BASEPT4 (# 388) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF4_REG_BASEPT4_OFFSET, (IFX_uint8_t)AR9_TCP_PF4_REG_BASEPT4_SHIFT, (IFX_uint8_t)AR9_TCP_PF4_REG_BASEPT4_SIZE}, /* PORT_FILTER_BASEPT5 (# 389) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF5_REG_BASEPT5_OFFSET, (IFX_uint8_t)AR9_TCP_PF5_REG_BASEPT5_SHIFT, (IFX_uint8_t)AR9_TCP_PF5_REG_BASEPT5_SIZE}, /* PORT_FILTER_BASEPT6 (# 390) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF6_REG_BASEPT6_OFFSET, (IFX_uint8_t)AR9_TCP_PF6_REG_BASEPT6_SHIFT, (IFX_uint8_t)AR9_TCP_PF6_REG_BASEPT6_SIZE}, /* PORT_FILTER_BASEPT7 (# 391) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)AR9_TCP_PF7_REG_BASEPT7_OFFSET, (IFX_uint8_t)AR9_TCP_PF7_REG_BASEPT7_SHIFT, (IFX_uint8_t)AR9_TCP_PF7_REG_BASEPT7_SIZE}, /* PORT_FILTER_COMP (# 392) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF0_REG_COMP0_OFFSET, (IFX_uint8_t)AR9_TCP_PF0_REG_COMP0_SHIFT, (IFX_uint8_t)AR9_TCP_PF0_REG_COMP0_SIZE}, /* PORT_FILTER_COMP1 (# 393) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF1_REG_COMP1_OFFSET, (IFX_uint8_t)AR9_TCP_PF1_REG_COMP1_SHIFT, (IFX_uint8_t)AR9_TCP_PF1_REG_COMP1_SIZE}, /* PORT_FILTER_COMP2 (# 394) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF2_REG_COMP2_OFFSET, (IFX_uint8_t)AR9_TCP_PF2_REG_COMP2_SHIFT, (IFX_uint8_t)AR9_TCP_PF2_REG_COMP2_SIZE}, /* PORT_FILTER_COMP3 (# 395) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF3_REG_COMP3_OFFSET, (IFX_uint8_t)AR9_TCP_PF3_REG_COMP3_SHIFT, (IFX_uint8_t)AR9_TCP_PF3_REG_COMP3_SIZE}, /* PORT_FILTER_COMP4 (# 396) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF4_REG_COMP4_OFFSET, (IFX_uint8_t)AR9_TCP_PF4_REG_COMP4_SHIFT, (IFX_uint8_t)AR9_TCP_PF4_REG_COMP4_SIZE}, /* PORT_FILTER_COMP5 (# 397) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF5_REG_COMP5_OFFSET, (IFX_uint8_t)AR9_TCP_PF5_REG_COMP5_SHIFT, (IFX_uint8_t)AR9_TCP_PF5_REG_COMP5_SIZE}, /* PORT_FILTER_COMP6 (# 398) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF6_REG_COMP6_OFFSET, (IFX_uint8_t)AR9_TCP_PF6_REG_COMP6_SHIFT, (IFX_uint8_t)AR9_TCP_PF6_REG_COMP6_SIZE}, /* PORT_FILTER_COMP7 (# 399) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)AR9_TCP_PF7_REG_COMP7_OFFSET, (IFX_uint8_t)AR9_TCP_PF7_REG_COMP7_SHIFT, (IFX_uint8_t)AR9_TCP_PF7_REG_COMP7_SIZE}, /* PORT_FILTER_PRANGE (# 400) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF0_REG_PRANGE0_OFFSET, (IFX_uint8_t)AR9_TCP_PF0_REG_PRANGE0_SHIFT, (IFX_uint8_t)AR9_TCP_PF0_REG_PRANGE0_SIZE}, /* PORT_FILTER_PRANGE1 (# 401) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF1_REG_PRANGE1_OFFSET, (IFX_uint8_t)AR9_TCP_PF1_REG_PRANGE1_SHIFT, (IFX_uint8_t)AR9_TCP_PF1_REG_PRANGE1_SIZE}, /* PORT_FILTER_PRANGE2 (# 402) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF2_REG_PRANGE2_OFFSET, (IFX_uint8_t)AR9_TCP_PF2_REG_PRANGE2_SHIFT, (IFX_uint8_t)AR9_TCP_PF2_REG_PRANGE2_SIZE}, /* PORT_FILTER_PRANGE3 (# 403) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF3_REG_PRANGE3_OFFSET, (IFX_uint8_t)AR9_TCP_PF3_REG_PRANGE3_SHIFT, (IFX_uint8_t)AR9_TCP_PF3_REG_PRANGE3_SIZE}, /* PORT_FILTER_PRANGE4 (# 404) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF4_REG_PRANGE4_OFFSET, (IFX_uint8_t)AR9_TCP_PF4_REG_PRANGE4_SHIFT, (IFX_uint8_t)AR9_TCP_PF4_REG_PRANGE4_SIZE}, /* PORT_FILTER_PRANGE5 (# 405) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF5_REG_PRANGE5_OFFSET, (IFX_uint8_t)AR9_TCP_PF5_REG_PRANGE5_SHIFT, (IFX_uint8_t)AR9_TCP_PF5_REG_PRANGE5_SIZE}, /* PORT_FILTER_PRANGE6 (# 406) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF6_REG_PRANGE6_OFFSET, (IFX_uint8_t)AR9_TCP_PF6_REG_PRANGE6_SHIFT, (IFX_uint8_t)AR9_TCP_PF6_REG_PRANGE6_SIZE}, /* PORT_FILTER_PRANGE7 (# 407) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)AR9_TCP_PF7_REG_PRANGE7_OFFSET, (IFX_uint8_t)AR9_TCP_PF7_REG_PRANGE7_SHIFT, (IFX_uint8_t)AR9_TCP_PF7_REG_PRANGE7_SIZE}, /* PORT_FILTER_TUPF (# 408) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF0_REG_TUPF0_OFFSET, (IFX_uint8_t)AR9_TCP_PF0_REG_TUPF0_SHIFT, (IFX_uint8_t)AR9_TCP_PF0_REG_TUPF0_SIZE}, /* PORT_FILTER_TUPF1 (# 409) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF1_REG_TUPF1_OFFSET, (IFX_uint8_t)AR9_TCP_PF1_REG_TUPF1_SHIFT, (IFX_uint8_t)AR9_TCP_PF1_REG_TUPF1_SIZE}, /* PORT_FILTER_TUPF2 (# 410) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF2_REG_TUPF2_OFFSET, (IFX_uint8_t)AR9_TCP_PF2_REG_TUPF2_SHIFT, (IFX_uint8_t)AR9_TCP_PF2_REG_TUPF2_SIZE}, /* PORT_FILTER_TUPF3 (# 411) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF3_REG_TUPF3_OFFSET, (IFX_uint8_t)AR9_TCP_PF3_REG_TUPF3_SHIFT, (IFX_uint8_t)AR9_TCP_PF3_REG_TUPF3_SIZE}, /* PORT_FILTER_TUPF4 (# 412) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF4_REG_TUPF4_OFFSET, (IFX_uint8_t)AR9_TCP_PF4_REG_TUPF4_SHIFT, (IFX_uint8_t)AR9_TCP_PF4_REG_TUPF4_SIZE}, /* PORT_FILTER_TUPF5 (# 413) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF5_REG_TUPF5_OFFSET, (IFX_uint8_t)AR9_TCP_PF5_REG_TUPF5_SHIFT, (IFX_uint8_t)AR9_TCP_PF5_REG_TUPF5_SIZE}, /* PORT_FILTER_TUPF6 (# 414) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF6_REG_TUPF6_OFFSET, (IFX_uint8_t)AR9_TCP_PF6_REG_TUPF6_SHIFT, (IFX_uint8_t)AR9_TCP_PF6_REG_TUPF6_SIZE}, /* PORT_FILTER_TUPF7 (# 415) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)AR9_TCP_PF7_REG_TUPF7_OFFSET, (IFX_uint8_t)AR9_TCP_PF7_REG_TUPF7_SHIFT, (IFX_uint8_t)AR9_TCP_PF7_REG_TUPF7_SIZE}, /* PORT_FLD (# 416) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)AR9_P0_CTL_REG_FLD_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_FLD_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_FLD_SIZE}, /* PORT_FLD1 (# 417) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)AR9_P1_CTL_REG_FLD_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_FLD_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_FLD_SIZE}, /* PORT_FLD2 (# 418) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)AR9_P2_CTL_REG_FLD_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_FLD_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_FLD_SIZE}, /* PORT_FLD3 (# 419) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLD4 (# 420) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLD5 (# 421) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLD6 (# 422) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLP (# 423) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)AR9_P0_CTL_REG_FLP_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_FLP_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_FLP_SIZE}, /* PORT_FLP1 (# 424) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)AR9_P1_CTL_REG_FLP_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_FLP_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_FLP_SIZE}, /* PORT_FLP2 (# 425) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)AR9_P2_CTL_REG_FLP_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_FLP_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_FLP_SIZE}, /* PORT_FLP3 (# 426) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLP4 (# 427) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLP5 (# 428) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_FLP6 (# 429) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IFNTE (# 430) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)AR9_P0_VLAN_REG_IFNTE_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_IFNTE_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_IFNTE_SIZE}, /* PORT_IFNTE1 (# 431) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)AR9_P1_VLAN_REG_IFNTE_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_IFNTE_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_IFNTE_SIZE}, /* PORT_IFNTE2 (# 432) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)AR9_P2_VLAN_REG_IFNTE_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_IFNTE_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_IFNTE_SIZE}, /* PORT_IFNTE3 (# 433) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IFNTE4 (# 434) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IFNTE5 (# 435) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IFNTE6 (# 436) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE (# 437) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE1 (# 438) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE2 (# 439) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE3 (# 440) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE4 (# 441) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE5 (# 442) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IMTE6 (# 443) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITR (# 444) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)AR9_P0_INCTL_REG_P0ITR_OFFSET, (IFX_uint8_t)AR9_P0_INCTL_REG_P0ITR_SHIFT, (IFX_uint8_t)AR9_P0_INCTL_REG_P0ITR_SIZE}, /* PORT_INGRESS_PITR1 (# 445) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)AR9_P1_INCTL_REG_P1ITR_OFFSET, (IFX_uint8_t)AR9_P1_INCTL_REG_P1ITR_SHIFT, (IFX_uint8_t)AR9_P1_INCTL_REG_P1ITR_SIZE}, /* PORT_INGRESS_PITR2 (# 446) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)AR9_P2_INCTL_REG_P2ITR_OFFSET, (IFX_uint8_t)AR9_P2_INCTL_REG_P2ITR_SHIFT, (IFX_uint8_t)AR9_P2_INCTL_REG_P2ITR_SIZE}, /* PORT_INGRESS_PITR3 (# 447) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITR4 (# 448) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITR5 (# 449) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITR6 (# 450) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITT (# 451) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)AR9_P0_INCTL_REG_P0ITT_OFFSET, (IFX_uint8_t)AR9_P0_INCTL_REG_P0ITT_SHIFT, (IFX_uint8_t)AR9_P0_INCTL_REG_P0ITT_SIZE}, /* PORT_INGRESS_PITT1 (# 452) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)AR9_P1_INCTL_REG_P1ITT_OFFSET, (IFX_uint8_t)AR9_P1_INCTL_REG_P1ITT_SHIFT, (IFX_uint8_t)AR9_P1_INCTL_REG_P1ITT_SIZE}, /* PORT_INGRESS_PITT2 (# 453) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)AR9_P2_INCTL_REG_P2ITT_OFFSET, (IFX_uint8_t)AR9_P2_INCTL_REG_P2ITT_SHIFT, (IFX_uint8_t)AR9_P2_INCTL_REG_P2ITT_SIZE}, /* PORT_INGRESS_PITT3 (# 454) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITT4 (# 455) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITT5 (# 456) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_INGRESS_PITT6 (# 457) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPMO (# 458) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)AR9_P0_CTL_REG_IPMO_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_IPMO_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_IPMO_SIZE}, /* PORT_IPMO1 (# 459) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)AR9_P1_CTL_REG_IPMO_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_IPMO_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_IPMO_SIZE}, /* PORT_IPMO2 (# 460) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)AR9_P2_CTL_REG_IPMO_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_IPMO_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_IPMO_SIZE}, /* PORT_IPMO3 (# 461) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPMO4 (# 462) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPMO5 (# 463) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPMO6 (# 464) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPOVTU (# 465) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)AR9_P0_CTL_REG_IPOVTU_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_IPOVTU_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_IPOVTU_SIZE}, /* PORT_IPOVTU1 (# 466) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)AR9_P1_CTL_REG_IPOVTU_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_IPOVTU_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_IPOVTU_SIZE}, /* PORT_IPOVTU2 (# 467) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)AR9_P2_CTL_REG_IPOVTU_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_IPOVTU_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_IPOVTU_SIZE}, /* PORT_IPOVTU3 (# 468) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPOVTU4 (# 469) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPOVTU5 (# 470) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPOVTU6 (# 471) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPVLAN (# 472) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)AR9_P0_CTL_REG_IPVLAN_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_IPVLAN_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_IPVLAN_SIZE}, /* PORT_IPVLAN1 (# 473) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)AR9_P1_CTL_REG_IPVLAN_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_IPVLAN_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_IPVLAN_SIZE}, /* PORT_IPVLAN2 (# 474) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)AR9_P2_CTL_REG_IPVLAN_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_IPVLAN_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_IPVLAN_SIZE}, /* PORT_IPVLAN3 (# 475) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPVLAN4 (# 476) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPVLAN5 (# 477) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_IPVLAN6 (# 478) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_LD (# 479) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)AR9_P0_CTL_REG_LD_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_LD_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_LD_SIZE}, /* PORT_LD1 (# 480) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)AR9_P1_CTL_REG_LD_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_LD_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_LD_SIZE}, /* PORT_LD2 (# 481) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)AR9_P2_CTL_REG_LD_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_LD_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_LD_SIZE}, /* PORT_LD3 (# 482) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_LD4 (# 483) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_LD5 (# 484) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_LD6 (# 485) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_MNA24 (# 486) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)AR9_P0_CTL_REG_MNA024_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_MNA024_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_MNA024_SIZE}, /* PORT_MNA241 (# 487) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)AR9_P1_CTL_REG_MNA024_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_MNA024_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_MNA024_SIZE}, /* PORT_MNA242 (# 488) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)AR9_P2_CTL_REG_MNA024_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_MNA024_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_MNA024_SIZE}, /* PORT_MNA243 (# 489) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_MNA244 (# 490) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_MNA245 (# 491) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_MNA246 (# 492) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_MP (# 493) */ { (IFX_uint16_t)PORT_MP, (IFX_uint16_t)AR9_DF_PORTMAP_REG_MP_OFFSET, (IFX_uint8_t)AR9_DF_PORTMAP_REG_MP_SHIFT, (IFX_uint8_t)AR9_DF_PORTMAP_REG_MP_SIZE}, /* PORT_PAS (# 494) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)AR9_P0_CTL_REG_PAS_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_PAS_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_PAS_SIZE}, /* PORT_PAS1 (# 495) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)AR9_P1_CTL_REG_PAS_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_PAS_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_PAS_SIZE}, /* PORT_PAS2 (# 496) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)AR9_P2_CTL_REG_PAS_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_PAS_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_PAS_SIZE}, /* PORT_PAS3 (# 497) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PAS4 (# 498) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PAS5 (# 499) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PAS6 (# 500) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PDS (# 501) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)AR9_PS_REG_P0DS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P0DS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P0DS_SIZE}, /* PORT_PDS1 (# 502) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)AR9_PS_REG_P1DS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P1DS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P1DS_SIZE}, /* PORT_PDS2 (# 503) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PDS3 (# 504) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PDS4 (# 505) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PDS5 (# 506) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PDS6 (# 507) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PFCS (# 508) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)AR9_PS_REG_P0FCS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P0FCS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P0FCS_SIZE}, /* PORT_PFCS1 (# 509) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)AR9_PS_REG_P1FCS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P1FCS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P1FCS_SIZE}, /* PORT_PFCS2 (# 510) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PFCS3 (# 511) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PFCS4 (# 512) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PFCS5 (# 513) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PFCS6 (# 514) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PLS (# 515) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)AR9_PS_REG_P0LS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P0LS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P0LS_SIZE}, /* PORT_PLS1 (# 516) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)AR9_PS_REG_P1LS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P1LS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P1LS_SIZE}, /* PORT_PLS2 (# 517) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PLS3 (# 518) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PLS4 (# 519) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PLS5 (# 520) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PLS6 (# 521) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PM (# 522) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)AR9_P0_CTL_REG_PM_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_PM_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_PM_SIZE}, /* PORT_PM1 (# 523) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)AR9_P1_CTL_REG_PM_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_PM_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_PM_SIZE}, /* PORT_PM2 (# 524) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)AR9_P2_CTL_REG_PM_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_PM_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_PM_SIZE}, /* PORT_PM3 (# 525) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PM4 (# 526) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PM5 (# 527) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PM6 (# 528) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PPPOEP (# 529) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)AR9_P0_CTL_REG_PPPOEP_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_PPPOEP_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_PPPOEP_SIZE}, /* PORT_PPPOEP1 (# 530) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)AR9_P1_CTL_REG_PPPOEP_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_PPPOEP_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_PPPOEP_SIZE}, /* PORT_PPPOEP2 (# 531) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)AR9_P2_CTL_REG_PPPOEP_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_PPPOEP_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_PPPOEP_SIZE}, /* PORT_PPPOEP3 (# 532) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PPPOEP4 (# 533) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PPPOEP5 (# 534) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PPPOEP6 (# 535) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSHS (# 536) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)AR9_PS_REG_P0SHS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P0SHS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P0SHS_SIZE}, /* PORT_PSHS1 (# 537) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)AR9_PS_REG_P1SHS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P1SHS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P1SHS_SIZE}, /* PORT_PSHS2 (# 538) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSHS3 (# 539) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSHS4 (# 540) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSHS5 (# 541) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSHS6 (# 542) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSS (# 543) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)AR9_PS_REG_P0SS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P0SS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P0SS_SIZE}, /* PORT_PSS1 (# 544) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)AR9_PS_REG_P1SS_OFFSET, (IFX_uint8_t)AR9_PS_REG_P1SS_SHIFT, (IFX_uint8_t)AR9_PS_REG_P1SS_SIZE}, /* PORT_PSS2 (# 545) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSS3 (# 546) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSS4 (# 547) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSS5 (# 548) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_PSS6 (# 549) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_REDIR (# 550) */ { (IFX_uint16_t)PORT_REDIR, (IFX_uint16_t)AR9_P0_CTL_REG_REDIR_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_REDIR_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_REDIR_SIZE}, /* PORT_REDIR1 (# 551) */ { (IFX_uint16_t)PORT_REDIR, (IFX_uint16_t)AR9_P1_CTL_REG_REDIR_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_REDIR_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_REDIR_SIZE}, /* PORT_REDIR2 (# 552) */ { (IFX_uint16_t)PORT_REDIR, (IFX_uint16_t)AR9_P2_CTL_REG_REDIR_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_REDIR_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_REDIR_SIZE}, /* PORT_RGMII_GMII_P0CKIO (# 553) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0CKIO, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0CKIO_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0CKIO_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0CKIO_SIZE}, /* PORT_RGMII_GMII_P0DUP (# 554) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0DUP, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0DUP_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0DUP_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0DUP_SIZE}, /* PORT_RGMII_GMII_P0FCE (# 555) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0FCE, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0FCE_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0FCE_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0FCE_SIZE}, /* PORT_RGMII_GMII_P0FEQ (# 556) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0FEQ, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0FEQ_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0FEQ_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0FEQ_SIZE}, /* PORT_RGMII_GMII_P0IS (# 557) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0IS, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0IS_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0IS_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0IS_SIZE}, /* PORT_RGMII_GMII_P0RDLY (# 558) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0RDLY, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0RDLY_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0RDLY_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0RDLY_SIZE}, /* PORT_RGMII_GMII_P0SPD (# 559) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0SPD, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0SPD_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0SPD_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0SPD_SIZE}, /* PORT_RGMII_GMII_P0TDLY (# 560) */ { (IFX_uint16_t)PORT_RGMII_GMII_P0TDLY, (IFX_uint16_t)AR9_RGMII_CTL_REG_P0TDLY_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0TDLY_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P0TDLY_SIZE}, /* PORT_RGMII_GMII_P1CKIO (# 561) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1CKIO, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1CKIO_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1CKIO_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1CKIO_SIZE}, /* PORT_RGMII_GMII_P1DUP (# 562) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1DUP, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1DUP_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1DUP_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1DUP_SIZE}, /* PORT_RGMII_GMII_P1FCE (# 563) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1FCE, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1FCE_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1FCE_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1FCE_SIZE}, /* PORT_RGMII_GMII_P1FEQ (# 564) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1FEQ, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1FEQ_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1FEQ_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1FEQ_SIZE}, /* PORT_RGMII_GMII_P1IS (# 565) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1IS, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1IS_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1IS_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1IS_SIZE}, /* PORT_RGMII_GMII_P1RDLY (# 566) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1RDLY, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1RDLY_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1RDLY_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1RDLY_SIZE}, /* PORT_RGMII_GMII_P1SPD (# 567) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1SPD, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1SPD_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1SPD_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1SPD_SIZE}, /* PORT_RGMII_GMII_P1TDLY (# 568) */ { (IFX_uint16_t)PORT_RGMII_GMII_P1TDLY, (IFX_uint16_t)AR9_RGMII_CTL_REG_P1TDLY_OFFSET, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1TDLY_SHIFT, (IFX_uint8_t)AR9_RGMII_CTL_REG_P1TDLY_SIZE}, /* PORT_RGMII_GMII_P4DUP (# 569) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P4FCE (# 570) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P4SPD (# 571) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P5DUP (# 572) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P5FCE (# 573) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P5SPD (# 574) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P6DUP (# 575) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P6FCE (# 576) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P6SPD (# 577) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RMWFQ (# 578) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)AR9_P0_CTL_REG_RMWFQ_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_RMWFQ_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_RMWFQ_SIZE}, /* PORT_RMWFQ1 (# 579) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)AR9_P1_CTL_REG_RMWFQ_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_RMWFQ_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_RMWFQ_SIZE}, /* PORT_RMWFQ2 (# 580) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)AR9_P2_CTL_REG_RMWFQ_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_RMWFQ_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_RMWFQ_SIZE}, /* PORT_RMWFQ3 (# 581) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RMWFQ4 (# 582) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RMWFQ5 (# 583) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RMWFQ6 (# 584) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RP (# 585) */ { (IFX_uint16_t)PORT_RP, (IFX_uint16_t)AR9_DF_PORTMAP_REG_RP_OFFSET, (IFX_uint8_t)AR9_DF_PORTMAP_REG_RP_SHIFT, (IFX_uint8_t)AR9_DF_PORTMAP_REG_RP_SIZE}, /* PORT_SPE (# 586) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)AR9_P0_CTL_REG_SPE_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_SPE_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_SPE_SIZE}, /* PORT_SPE1 (# 587) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)AR9_P1_CTL_REG_SPE_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_SPE_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_SPE_SIZE}, /* PORT_SPE2 (# 588) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)AR9_P2_CTL_REG_SPE_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_SPE_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_SPE_SIZE}, /* PORT_SPE3 (# 589) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPE4 (# 590) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPE5 (# 591) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPE6 (# 592) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPS (# 593) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)AR9_P0_CTL_REG_SPS_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_SPS_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_SPS_SIZE}, /* PORT_SPS1 (# 594) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)AR9_P1_CTL_REG_SPS_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_SPS_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_SPS_SIZE}, /* PORT_SPS2 (# 595) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)AR9_P2_CTL_REG_SPS_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_SPS_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_SPS_SIZE}, /* PORT_SPS3 (# 596) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPS4 (# 597) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPS5 (# 598) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_SPS6 (# 599) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TCPE (# 600) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)AR9_P0_CTL_REG_TCPE_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_TCPE_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_TCPE_SIZE}, /* PORT_TCPE1 (# 601) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)AR9_P1_CTL_REG_TCPE_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_TCPE_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_TCPE_SIZE}, /* PORT_TCPE2 (# 602) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)AR9_P2_CTL_REG_TCPE_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_TCPE_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_TCPE_SIZE}, /* PORT_TCPE3 (# 603) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TCPE4 (# 604) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TCPE5 (# 605) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TCPE6 (# 606) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TPE (# 607) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)AR9_P0_CTL_REG_TPE_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_TPE_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_TPE_SIZE}, /* PORT_TPE1 (# 608) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)AR9_P1_CTL_REG_TPE_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_TPE_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_TPE_SIZE}, /* PORT_TPE2 (# 609) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)AR9_P2_CTL_REG_TPE_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_TPE_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_TPE_SIZE}, /* PORT_TPE3 (# 610) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TPE4 (# 611) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TPE5 (# 612) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_TPE6 (# 613) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_UP (# 614) */ { (IFX_uint16_t)PORT_UP, (IFX_uint16_t)AR9_DF_PORTMAP_REG_UP_OFFSET, (IFX_uint8_t)AR9_DF_PORTMAP_REG_UP_SHIFT, (IFX_uint8_t)AR9_DF_PORTMAP_REG_UP_SIZE}, /* PORT_VLAN_AOVTP (# 615) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)AR9_P0_VLAN_REG_AOVTP_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_AOVTP_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_AOVTP_SIZE}, /* PORT_VLAN_AOVTP1 (# 616) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)AR9_P1_VLAN_REG_AOVTP_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_AOVTP_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_AOVTP_SIZE}, /* PORT_VLAN_AOVTP2 (# 617) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)AR9_P2_VLAN_REG_AOVTP_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_AOVTP_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_AOVTP_SIZE}, /* PORT_VLAN_AOVTP3 (# 618) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_AOVTP4 (# 619) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_AOVTP5 (# 620) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_AOVTP6 (# 621) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_BYPASS (# 622) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)AR9_P0_CTL_REG_BYPASS_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_BYPASS_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_BYPASS_SIZE}, /* PORT_VLAN_BYPASS1 (# 623) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)AR9_P1_CTL_REG_BYPASS_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_BYPASS_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_BYPASS_SIZE}, /* PORT_VLAN_BYPASS2 (# 624) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)AR9_P2_CTL_REG_BYPASS_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_BYPASS_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_BYPASS_SIZE}, /* PORT_VLAN_BYPASS3 (# 625) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_BYPASS4 (# 626) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_BYPASS5 (# 627) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_BYPASS6 (# 628) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DFID (# 629) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)AR9_P0_VLAN_REG_DFID_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_DFID_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_DFID_SIZE}, /* PORT_VLAN_DFID1 (# 630) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)AR9_P1_VLAN_REG_DFID_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_DFID_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_DFID_SIZE}, /* PORT_VLAN_DFID2 (# 631) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)AR9_P2_VLAN_REG_DFID_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_DFID_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_DFID_SIZE}, /* PORT_VLAN_DFID3 (# 632) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DFID4 (# 633) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DFID5 (# 634) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DFID6 (# 635) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DVPM (# 636) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)AR9_P0_VLAN_REG_DVPM_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_DVPM_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_DVPM_SIZE}, /* PORT_VLAN_DVPM1 (# 637) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)AR9_P1_VLAN_REG_DVPM_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_DVPM_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_DVPM_SIZE}, /* PORT_VLAN_DVPM2 (# 638) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)AR9_P2_VLAN_REG_DVPM_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_DVPM_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_DVPM_SIZE}, /* PORT_VLAN_DVPM3 (# 639) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DVPM4 (# 640) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DVPM5 (# 641) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_DVPM6 (# 642) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PP (# 643) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)AR9_P0_VLAN_REG_PP_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_PP_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_PP_SIZE}, /* PORT_VLAN_PP1 (# 644) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)AR9_P1_VLAN_REG_PP_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_PP_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_PP_SIZE}, /* PORT_VLAN_PP2 (# 645) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)AR9_P2_VLAN_REG_PP_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_PP_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_PP_SIZE}, /* PORT_VLAN_PP3 (# 646) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PP4 (# 647) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PP5 (# 648) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PP6 (# 649) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PPE (# 650) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)AR9_P0_VLAN_REG_PPE_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_PPE_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_PPE_SIZE}, /* PORT_VLAN_PPE1 (# 651) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)AR9_P1_VLAN_REG_PPE_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_PPE_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_PPE_SIZE}, /* PORT_VLAN_PPE2 (# 652) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)AR9_P2_VLAN_REG_PPE_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_PPE_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_PPE_SIZE}, /* PORT_VLAN_PPE3 (# 653) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PPE4 (# 654) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PPE5 (# 655) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PPE6 (# 656) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVID (# 657) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)AR9_P0_VLAN_REG_PVID_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_PVID_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_PVID_SIZE}, /* PORT_VLAN_PVID1 (# 658) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)AR9_P1_VLAN_REG_PVID_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_PVID_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_PVID_SIZE}, /* PORT_VLAN_PVID2 (# 659) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)AR9_P2_VLAN_REG_PVID_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_PVID_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_PVID_SIZE}, /* PORT_VLAN_PVID3 (# 660) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVID4 (# 661) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVID5 (# 662) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVID6 (# 663) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVTAGMP (# 664) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)AR9_P0_VLAN_REG_PVTAGMP_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_PVTAGMP_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP1 (# 665) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)AR9_P1_VLAN_REG_PVTAGMP_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_PVTAGMP_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP2 (# 666) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)AR9_P2_VLAN_REG_PVTAGMP_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_PVTAGMP_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP3 (# 667) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVTAGMP4 (# 668) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVTAGMP5 (# 669) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_PVTAGMP6 (# 670) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_TBVE (# 671) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)AR9_P0_VLAN_REG_TBVE_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_TBVE_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_TBVE_SIZE}, /* PORT_VLAN_TBVE1 (# 672) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)AR9_P1_VLAN_REG_TBVE_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_TBVE_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_TBVE_SIZE}, /* PORT_VLAN_TBVE2 (# 673) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)AR9_P2_VLAN_REG_TBVE_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_TBVE_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_TBVE_SIZE}, /* PORT_VLAN_TBVE3 (# 674) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_TBVE4 (# 675) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_TBVE5 (# 676) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_TBVE6 (# 677) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VC (# 678) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)AR9_P0_VLAN_REG_VC_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_VC_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_VC_SIZE}, /* PORT_VLAN_VC1 (# 679) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)AR9_P1_VLAN_REG_VC_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_VC_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_VC_SIZE}, /* PORT_VLAN_VC2 (# 680) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)AR9_P2_VLAN_REG_VC_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_VC_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_VC_SIZE}, /* PORT_VLAN_VC3 (# 681) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VC4 (# 682) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VC5 (# 683) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VC6 (# 684) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VMCE (# 685) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)AR9_P0_VLAN_REG_VMCE_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_VMCE_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_VMCE_SIZE}, /* PORT_VLAN_VMCE1 (# 686) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)AR9_P1_VLAN_REG_VMCE_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_VMCE_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_VMCE_SIZE}, /* PORT_VLAN_VMCE2 (# 687) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)AR9_P2_VLAN_REG_VMCE_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_VMCE_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_VMCE_SIZE}, /* PORT_VLAN_VMCE3 (# 688) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VMCE4 (# 689) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VMCE5 (# 690) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VMCE6 (# 691) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VSD (# 692) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)AR9_P0_VLAN_REG_VSD_OFFSET, (IFX_uint8_t)AR9_P0_VLAN_REG_VSD_SHIFT, (IFX_uint8_t)AR9_P0_VLAN_REG_VSD_SIZE}, /* PORT_VLAN_VSD1 (# 693) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)AR9_P1_VLAN_REG_VSD_OFFSET, (IFX_uint8_t)AR9_P1_VLAN_REG_VSD_SHIFT, (IFX_uint8_t)AR9_P1_VLAN_REG_VSD_SIZE}, /* PORT_VLAN_VSD2 (# 694) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)AR9_P2_VLAN_REG_VSD_OFFSET, (IFX_uint8_t)AR9_P2_VLAN_REG_VSD_SHIFT, (IFX_uint8_t)AR9_P2_VLAN_REG_VSD_SIZE}, /* PORT_VLAN_VSD3 (# 695) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VSD4 (# 696) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VSD5 (# 697) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VLAN_VSD6 (# 698) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VPE (# 699) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)AR9_P0_CTL_REG_VPE_OFFSET, (IFX_uint8_t)AR9_P0_CTL_REG_VPE_SHIFT, (IFX_uint8_t)AR9_P0_CTL_REG_VPE_SIZE}, /* PORT_VPE1 (# 700) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)AR9_P1_CTL_REG_VPE_OFFSET, (IFX_uint8_t)AR9_P1_CTL_REG_VPE_SHIFT, (IFX_uint8_t)AR9_P1_CTL_REG_VPE_SIZE}, /* PORT_VPE2 (# 701) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)AR9_P2_CTL_REG_VPE_OFFSET, (IFX_uint8_t)AR9_P2_CTL_REG_VPE_SHIFT, (IFX_uint8_t)AR9_P2_CTL_REG_VPE_SIZE}, /* PORT_VPE3 (# 702) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VPE4 (# 703) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VPE5 (# 704) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_VPE6 (# 705) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PPPOE_SID (# 706) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_APF (# 707) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF0_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF0_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF0_SIZE}, /* PROTOCOL_FILTER_APF1 (# 708) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF1_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF1_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF1_SIZE}, /* PROTOCOL_FILTER_APF2 (# 709) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF2_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF2_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF2_SIZE}, /* PROTOCOL_FILTER_APF3 (# 710) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF3_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF3_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF3_SIZE}, /* PROTOCOL_FILTER_APF4 (# 711) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF4_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF4_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF4_SIZE}, /* PROTOCOL_FILTER_APF5 (# 712) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF5_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF5_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF5_SIZE}, /* PROTOCOL_FILTER_APF6 (# 713) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF6_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF6_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF6_SIZE}, /* PROTOCOL_FILTER_APF7 (# 714) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)AR9_PRTCL_FLT_ACT_REG_APF7_OFFSET, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF7_SHIFT, (IFX_uint8_t)AR9_PRTCL_FLT_ACT_REG_APF7_SIZE}, /* PROTOCOL_FILTER_PFR0 (# 715) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)AR9_PRTCL_F0_REG_PFR0_OFFSET, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR0_SHIFT, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR01 (# 716) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)AR9_PRTCL_F1_REG_PFR0_OFFSET, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR0_SHIFT, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR02 (# 717) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR03 (# 718) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR1 (# 719) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)AR9_PRTCL_F0_REG_PFR1_OFFSET, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR1_SHIFT, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR11 (# 720) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)AR9_PRTCL_F1_REG_PFR1_OFFSET, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR1_SHIFT, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR12 (# 721) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR13 (# 722) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR2 (# 723) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR2, (IFX_uint16_t)AR9_PRTCL_F0_REG_PFR2_OFFSET, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR2_SHIFT, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR2_SIZE}, /* PROTOCOL_FILTER_PFR21 (# 724) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR2, (IFX_uint16_t)AR9_PRTCL_F1_REG_PFR2_OFFSET, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR2_SHIFT, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR2_SIZE}, /* PROTOCOL_FILTER_PFR3 (# 725) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR3, (IFX_uint16_t)AR9_PRTCL_F0_REG_PFR3_OFFSET, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR3_SHIFT, (IFX_uint8_t)AR9_PRTCL_F0_REG_PFR3_SIZE}, /* PROTOCOL_FILTER_PFR31 (# 726) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR3, (IFX_uint16_t)AR9_PRTCL_F1_REG_PFR3_OFFSET, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR3_SHIFT, (IFX_uint8_t)AR9_PRTCL_F1_REG_PFR3_SIZE}, /* RA00_ACT (# 727) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_ACT_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_ACT_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_ACT_SIZE}, /* RA00_ACT1 (# 728) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_ACT_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_ACT_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_ACT_SIZE}, /* RA00_ACT2 (# 729) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_ACT_SIZE}, /* RA00_ACT3 (# 730) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_ACT_SIZE}, /* RA00_ACT4 (# 731) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_ACT_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_ACT_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_ACT_SIZE}, /* RA00_ACT5 (# 732) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_ACT_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_ACT_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_ACT_SIZE}, /* RA00_ACT6 (# 733) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_ACT_SIZE}, /* RA00_ACT7 (# 734) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_ACT_SIZE}, /* RA00_ACT8 (# 735) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_ACT_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_ACT_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_ACT_SIZE}, /* RA00_ACT9 (# 736) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_ACT_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_ACT_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_ACT_SIZE}, /* RA00_ACT10 (# 737) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_ACT_SIZE}, /* RA00_ACT11 (# 738) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_ACT_SIZE}, /* RA00_ACT12 (# 739) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT13 (# 740) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT14 (# 741) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT15 (# 742) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT16 (# 743) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT17 (# 744) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT18 (# 745) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT19 (# 746) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT20 (# 747) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT21 (# 748) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT22 (# 749) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT23 (# 750) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV (# 751) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_CV_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_CV_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_CV_SIZE}, /* RA00_CV1 (# 752) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_CV_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_CV_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_CV_SIZE}, /* RA00_CV2 (# 753) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_CV_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_CV_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_CV_SIZE}, /* RA00_CV3 (# 754) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_CV_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_CV_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_CV_SIZE}, /* RA00_CV4 (# 755) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_CV_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_CV_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_CV_SIZE}, /* RA00_CV5 (# 756) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_CV_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_CV_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_CV_SIZE}, /* RA00_CV6 (# 757) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_CV_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_CV_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_CV_SIZE}, /* RA00_CV7 (# 758) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_CV_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_CV_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_CV_SIZE}, /* RA00_CV8 (# 759) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_CV_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_CV_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_CV_SIZE}, /* RA00_CV9 (# 760) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_CV_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_CV_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_CV_SIZE}, /* RA00_CV10 (# 761) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_CV_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_CV_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_CV_SIZE}, /* RA00_CV11 (# 762) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_CV_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_CV_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_CV_SIZE}, /* RA00_CV12 (# 763) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV13 (# 764) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV14 (# 765) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV15 (# 766) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV16 (# 767) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV17 (# 768) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV18 (# 769) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV19 (# 770) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV20 (# 771) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV21 (# 772) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV22 (# 773) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_CV23 (# 774) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG (# 775) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_MG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_MG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_MG_SIZE}, /* RA00_MG1 (# 776) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_MG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_MG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_MG_SIZE}, /* RA00_MG2 (# 777) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_MG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_MG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_MG_SIZE}, /* RA00_MG3 (# 778) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_MG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_MG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_MG_SIZE}, /* RA00_MG4 (# 779) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_MG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_MG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_MG_SIZE}, /* RA00_MG5 (# 780) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_MG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_MG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_MG_SIZE}, /* RA00_MG6 (# 781) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_MG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_MG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_MG_SIZE}, /* RA00_MG7 (# 782) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_MG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_MG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_MG_SIZE}, /* RA00_MG8 (# 783) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_MG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_MG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_MG_SIZE}, /* RA00_MG9 (# 784) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_MG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_MG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_MG_SIZE}, /* RA00_MG10 (# 785) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_MG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_MG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_MG_SIZE}, /* RA00_MG11 (# 786) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_MG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_MG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_MG_SIZE}, /* RA00_MG12 (# 787) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG13 (# 788) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG14 (# 789) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG15 (# 790) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG16 (# 791) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG17 (# 792) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG18 (# 793) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG19 (# 794) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG20 (# 795) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG21 (# 796) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG22 (# 797) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_MG23 (# 798) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN (# 799) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_SPAN_SIZE}, /* RA00_SPAN1 (# 800) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_SPAN_SIZE}, /* RA00_SPAN2 (# 801) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_SPAN_SIZE}, /* RA00_SPAN3 (# 802) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_SPAN_SIZE}, /* RA00_SPAN4 (# 803) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_SPAN_SIZE}, /* RA00_SPAN5 (# 804) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_SPAN_SIZE}, /* RA00_SPAN6 (# 805) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_SPAN_SIZE}, /* RA00_SPAN7 (# 806) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_SPAN_SIZE}, /* RA00_SPAN8 (# 807) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_SPAN_SIZE}, /* RA00_SPAN9 (# 808) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_SPAN_SIZE}, /* RA00_SPAN10 (# 809) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_SPAN_SIZE}, /* RA00_SPAN11 (# 810) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_SPAN_SIZE}, /* RA00_SPAN12 (# 811) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN13 (# 812) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN14 (# 813) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN15 (# 814) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN16 (# 815) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN17 (# 816) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN18 (# 817) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN19 (# 818) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN20 (# 819) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN21 (# 820) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN22 (# 821) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_SPAN23 (# 822) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG (# 823) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_TXTAG_SIZE}, /* RA00_TXTAG1 (# 824) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_TXTAG_SIZE}, /* RA00_TXTAG2 (# 825) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_TXTAG_SIZE}, /* RA00_TXTAG3 (# 826) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_TXTAG_SIZE}, /* RA00_TXTAG4 (# 827) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_TXTAG_SIZE}, /* RA00_TXTAG5 (# 828) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_TXTAG_SIZE}, /* RA00_TXTAG6 (# 829) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_TXTAG_SIZE}, /* RA00_TXTAG7 (# 830) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_TXTAG_SIZE}, /* RA00_TXTAG8 (# 831) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_TXTAG_SIZE}, /* RA00_TXTAG9 (# 832) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_TXTAG_SIZE}, /* RA00_TXTAG10 (# 833) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_TXTAG_SIZE}, /* RA00_TXTAG11 (# 834) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_TXTAG_SIZE}, /* RA00_TXTAG12 (# 835) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG13 (# 836) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG14 (# 837) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG15 (# 838) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG16 (# 839) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG17 (# 840) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG18 (# 841) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG19 (# 842) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG20 (# 843) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG21 (# 844) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG22 (# 845) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_TXTAG23 (# 846) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID (# 847) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_03_00_REG_RA00_VALID_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_VALID_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA00_VALID_SIZE}, /* RA00_VALID1 (# 848) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_07_04_REG_RA10_VALID_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_VALID_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA10_VALID_SIZE}, /* RA00_VALID2 (# 849) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_0B_08_REG_RA20_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA20_VALID_SIZE}, /* RA00_VALID3 (# 850) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA30_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA30_VALID_SIZE}, /* RA00_VALID4 (# 851) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_13_10_REG_RA40_VALID_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_VALID_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA40_VALID_SIZE}, /* RA00_VALID5 (# 852) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_17_14_REG_RA50_VALID_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_VALID_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA50_VALID_SIZE}, /* RA00_VALID6 (# 853) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_1B_18_REG_RA60_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA60_VALID_SIZE}, /* RA00_VALID7 (# 854) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA70_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA70_VALID_SIZE}, /* RA00_VALID8 (# 855) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_23_20_REG_RA80_VALID_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_VALID_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA80_VALID_SIZE}, /* RA00_VALID9 (# 856) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_27_24_REG_RA90_VALID_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_VALID_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA90_VALID_SIZE}, /* RA00_VALID10 (# 857) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_2B_28_REG_RA100_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA100_VALID_SIZE}, /* RA00_VALID11 (# 858) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA110_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA110_VALID_SIZE}, /* RA00_VALID12 (# 859) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID13 (# 860) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID14 (# 861) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID15 (# 862) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID16 (# 863) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID17 (# 864) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID18 (# 865) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID19 (# 866) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID20 (# 867) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID21 (# 868) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID22 (# 869) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_VALID23 (# 870) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT (# 871) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_ACT_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_ACT_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_ACT_SIZE}, /* RA01_ACT1 (# 872) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_ACT_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_ACT_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_ACT_SIZE}, /* RA01_ACT2 (# 873) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_ACT_SIZE}, /* RA01_ACT3 (# 874) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_ACT_SIZE}, /* RA01_ACT4 (# 875) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_ACT_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_ACT_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_ACT_SIZE}, /* RA01_ACT5 (# 876) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_ACT_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_ACT_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_ACT_SIZE}, /* RA01_ACT6 (# 877) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_ACT_SIZE}, /* RA01_ACT7 (# 878) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_ACT_SIZE}, /* RA01_ACT8 (# 879) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_ACT_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_ACT_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_ACT_SIZE}, /* RA01_ACT9 (# 880) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_ACT_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_ACT_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_ACT_SIZE}, /* RA01_ACT10 (# 881) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_ACT_SIZE}, /* RA01_ACT11 (# 882) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_ACT_SIZE}, /* RA01_ACT12 (# 883) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT13 (# 884) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT14 (# 885) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT15 (# 886) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT16 (# 887) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT17 (# 888) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT18 (# 889) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT19 (# 890) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT20 (# 891) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT21 (# 892) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT22 (# 893) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_ACT23 (# 894) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV (# 895) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_CV_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_CV_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_CV_SIZE}, /* RA01_CV1 (# 896) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_CV_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_CV_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_CV_SIZE}, /* RA01_CV2 (# 897) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_CV_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_CV_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_CV_SIZE}, /* RA01_CV3 (# 898) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_CV_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_CV_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_CV_SIZE}, /* RA01_CV4 (# 899) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_CV_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_CV_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_CV_SIZE}, /* RA01_CV5 (# 900) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_CV_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_CV_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_CV_SIZE}, /* RA01_CV6 (# 901) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_CV_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_CV_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_CV_SIZE}, /* RA01_CV7 (# 902) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_CV_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_CV_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_CV_SIZE}, /* RA01_CV8 (# 903) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_CV_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_CV_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_CV_SIZE}, /* RA01_CV9 (# 904) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_CV_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_CV_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_CV_SIZE}, /* RA01_CV10 (# 905) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_CV_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_CV_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_CV_SIZE}, /* RA01_CV11 (# 906) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_CV_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_CV_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_CV_SIZE}, /* RA01_CV12 (# 907) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV13 (# 908) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV14 (# 909) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV15 (# 910) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV16 (# 911) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV17 (# 912) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV18 (# 913) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV19 (# 914) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV20 (# 915) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV21 (# 916) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV22 (# 917) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_CV23 (# 918) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG (# 919) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_MG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_MG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_MG_SIZE}, /* RA01_MG1 (# 920) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_MG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_MG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_MG_SIZE}, /* RA01_MG2 (# 921) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_MG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_MG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_MG_SIZE}, /* RA01_MG3 (# 922) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_MG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_MG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_MG_SIZE}, /* RA01_MG4 (# 923) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_MG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_MG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_MG_SIZE}, /* RA01_MG5 (# 924) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_MG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_MG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_MG_SIZE}, /* RA01_MG6 (# 925) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_MG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_MG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_MG_SIZE}, /* RA01_MG7 (# 926) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_MG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_MG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_MG_SIZE}, /* RA01_MG8 (# 927) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_MG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_MG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_MG_SIZE}, /* RA01_MG9 (# 928) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_MG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_MG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_MG_SIZE}, /* RA01_MG10 (# 929) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_MG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_MG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_MG_SIZE}, /* RA01_MG11 (# 930) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_MG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_MG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_MG_SIZE}, /* RA01_MG12 (# 931) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG13 (# 932) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG14 (# 933) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG15 (# 934) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG16 (# 935) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG17 (# 936) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG18 (# 937) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG19 (# 938) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG20 (# 939) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG21 (# 940) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG22 (# 941) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_MG23 (# 942) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN (# 943) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_SPAN_SIZE}, /* RA01_SPAN1 (# 944) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_SPAN_SIZE}, /* RA01_SPAN2 (# 945) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_SPAN_SIZE}, /* RA01_SPAN3 (# 946) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_SPAN_SIZE}, /* RA01_SPAN4 (# 947) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_SPAN_SIZE}, /* RA01_SPAN5 (# 948) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_SPAN_SIZE}, /* RA01_SPAN6 (# 949) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_SPAN_SIZE}, /* RA01_SPAN7 (# 950) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_SPAN_SIZE}, /* RA01_SPAN8 (# 951) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_SPAN_SIZE}, /* RA01_SPAN9 (# 952) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_SPAN_SIZE}, /* RA01_SPAN10 (# 953) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_SPAN_SIZE}, /* RA01_SPAN11 (# 954) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_SPAN_SIZE}, /* RA01_SPAN12 (# 955) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN13 (# 956) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN14 (# 957) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN15 (# 958) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN16 (# 959) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN17 (# 960) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN18 (# 961) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN19 (# 962) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN20 (# 963) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN21 (# 964) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN22 (# 965) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_SPAN23 (# 966) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG (# 967) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_TXTAG_SIZE}, /* RA01_TXTAG1 (# 968) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_TXTAG_SIZE}, /* RA01_TXTAG2 (# 969) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_TXTAG_SIZE}, /* RA01_TXTAG3 (# 970) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_TXTAG_SIZE}, /* RA01_TXTAG4 (# 971) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_TXTAG_SIZE}, /* RA01_TXTAG5 (# 972) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_TXTAG_SIZE}, /* RA01_TXTAG6 (# 973) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_TXTAG_SIZE}, /* RA01_TXTAG7 (# 974) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_TXTAG_SIZE}, /* RA01_TXTAG8 (# 975) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_TXTAG_SIZE}, /* RA01_TXTAG9 (# 976) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_TXTAG_SIZE}, /* RA01_TXTAG10 (# 977) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_TXTAG_SIZE}, /* RA01_TXTAG11 (# 978) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_TXTAG_SIZE}, /* RA01_TXTAG12 (# 979) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG13 (# 980) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG14 (# 981) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG15 (# 982) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG16 (# 983) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG17 (# 984) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG18 (# 985) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG19 (# 986) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG20 (# 987) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG21 (# 988) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG22 (# 989) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_TXTAG23 (# 990) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID (# 991) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_03_00_REG_RA01_VALID_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_VALID_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA01_VALID_SIZE}, /* RA01_VALID1 (# 992) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_07_04_REG_RA11_VALID_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_VALID_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA11_VALID_SIZE}, /* RA01_VALID2 (# 993) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_0B_08_REG_RA21_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA21_VALID_SIZE}, /* RA01_VALID3 (# 994) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA31_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA31_VALID_SIZE}, /* RA01_VALID4 (# 995) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_13_10_REG_RA41_VALID_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_VALID_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA41_VALID_SIZE}, /* RA01_VALID5 (# 996) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_17_14_REG_RA51_VALID_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_VALID_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA51_VALID_SIZE}, /* RA01_VALID6 (# 997) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_1B_18_REG_RA61_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA61_VALID_SIZE}, /* RA01_VALID7 (# 998) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA71_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA71_VALID_SIZE}, /* RA01_VALID8 (# 999) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_23_20_REG_RA81_VALID_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_VALID_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA81_VALID_SIZE}, /* RA01_VALID9 (# 1000) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_27_24_REG_RA91_VALID_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_VALID_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA91_VALID_SIZE}, /* RA01_VALID10 (# 1001) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_2B_28_REG_RA101_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA101_VALID_SIZE}, /* RA01_VALID11 (# 1002) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA111_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA111_VALID_SIZE}, /* RA01_VALID12 (# 1003) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID13 (# 1004) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID14 (# 1005) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID15 (# 1006) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID16 (# 1007) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID17 (# 1008) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID18 (# 1009) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID19 (# 1010) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID20 (# 1011) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID21 (# 1012) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID22 (# 1013) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA01_VALID23 (# 1014) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT (# 1015) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_ACT_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_ACT_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_ACT_SIZE}, /* RA02_ACT1 (# 1016) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_ACT_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_ACT_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_ACT_SIZE}, /* RA02_ACT2 (# 1017) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_ACT_SIZE}, /* RA02_ACT3 (# 1018) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_ACT_SIZE}, /* RA02_ACT4 (# 1019) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_ACT_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_ACT_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_ACT_SIZE}, /* RA02_ACT5 (# 1020) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_ACT_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_ACT_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_ACT_SIZE}, /* RA02_ACT6 (# 1021) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_ACT_SIZE}, /* RA02_ACT7 (# 1022) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_ACT_SIZE}, /* RA02_ACT8 (# 1023) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_ACT_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_ACT_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_ACT_SIZE}, /* RA02_ACT9 (# 1024) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_ACT_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_ACT_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_ACT_SIZE}, /* RA02_ACT10 (# 1025) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_ACT_SIZE}, /* RA02_ACT11 (# 1026) */ { (IFX_uint16_t)RA02_ACT, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_ACT_SIZE}, /* RA02_CV (# 1027) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_CV_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_CV_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_CV_SIZE}, /* RA02_CV1 (# 1028) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_CV_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_CV_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_CV_SIZE}, /* RA02_CV2 (# 1029) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_CV_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_CV_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_CV_SIZE}, /* RA02_CV3 (# 1030) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_CV_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_CV_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_CV_SIZE}, /* RA02_CV4 (# 1031) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_CV_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_CV_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_CV_SIZE}, /* RA02_CV5 (# 1032) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_CV_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_CV_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_CV_SIZE}, /* RA02_CV6 (# 1033) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_CV_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_CV_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_CV_SIZE}, /* RA02_CV7 (# 1034) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_CV_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_CV_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_CV_SIZE}, /* RA02_CV8 (# 1035) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_CV_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_CV_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_CV_SIZE}, /* RA02_CV9 (# 1036) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_CV_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_CV_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_CV_SIZE}, /* RA02_CV10 (# 1037) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_CV_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_CV_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_CV_SIZE}, /* RA02_CV11 (# 1038) */ { (IFX_uint16_t)RA02_CV, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_CV_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_CV_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_CV_SIZE}, /* RA02_MG (# 1039) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_MG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_MG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_MG_SIZE}, /* RA02_MG1 (# 1040) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_MG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_MG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_MG_SIZE}, /* RA02_MG2 (# 1041) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_MG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_MG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_MG_SIZE}, /* RA02_MG3 (# 1042) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_MG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_MG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_MG_SIZE}, /* RA02_MG4 (# 1043) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_MG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_MG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_MG_SIZE}, /* RA02_MG5 (# 1044) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_MG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_MG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_MG_SIZE}, /* RA02_MG6 (# 1045) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_MG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_MG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_MG_SIZE}, /* RA02_MG7 (# 1046) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_MG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_MG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_MG_SIZE}, /* RA02_MG8 (# 1047) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_MG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_MG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_MG_SIZE}, /* RA02_MG9 (# 1048) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_MG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_MG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_MG_SIZE}, /* RA02_MG10 (# 1049) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_MG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_MG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_MG_SIZE}, /* RA02_MG11 (# 1050) */ { (IFX_uint16_t)RA02_MG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_MG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_MG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_MG_SIZE}, /* RA02_SPAN (# 1051) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_SPAN_SIZE}, /* RA02_SPAN1 (# 1052) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_SPAN_SIZE}, /* RA02_SPAN2 (# 1053) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_SPAN_SIZE}, /* RA02_SPAN3 (# 1054) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_SPAN_SIZE}, /* RA02_SPAN4 (# 1055) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_SPAN_SIZE}, /* RA02_SPAN5 (# 1056) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_SPAN_SIZE}, /* RA02_SPAN6 (# 1057) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_SPAN_SIZE}, /* RA02_SPAN7 (# 1058) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_SPAN_SIZE}, /* RA02_SPAN8 (# 1059) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_SPAN_SIZE}, /* RA02_SPAN9 (# 1060) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_SPAN_SIZE}, /* RA02_SPAN10 (# 1061) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_SPAN_SIZE}, /* RA02_SPAN11 (# 1062) */ { (IFX_uint16_t)RA02_SPAN, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_SPAN_SIZE}, /* RA02_TXTAG (# 1063) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_TXTAG_SIZE}, /* RA02_TXTAG1 (# 1064) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_TXTAG_SIZE}, /* RA02_TXTAG2 (# 1065) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_TXTAG_SIZE}, /* RA02_TXTAG3 (# 1066) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_TXTAG_SIZE}, /* RA02_TXTAG4 (# 1067) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_TXTAG_SIZE}, /* RA02_TXTAG5 (# 1068) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_TXTAG_SIZE}, /* RA02_TXTAG6 (# 1069) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_TXTAG_SIZE}, /* RA02_TXTAG7 (# 1070) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_TXTAG_SIZE}, /* RA02_TXTAG8 (# 1071) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_TXTAG_SIZE}, /* RA02_TXTAG9 (# 1072) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_TXTAG_SIZE}, /* RA02_TXTAG10 (# 1073) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_TXTAG_SIZE}, /* RA02_TXTAG11 (# 1074) */ { (IFX_uint16_t)RA02_TXTAG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_TXTAG_SIZE}, /* RA02_VALID (# 1075) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_03_00_REG_RA02_VALID_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_VALID_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA02_VALID_SIZE}, /* RA02_VALID1 (# 1076) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_07_04_REG_RA12_VALID_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_VALID_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA12_VALID_SIZE}, /* RA02_VALID2 (# 1077) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_0B_08_REG_RA22_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA22_VALID_SIZE}, /* RA02_VALID3 (# 1078) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA32_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA32_VALID_SIZE}, /* RA02_VALID4 (# 1079) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_13_10_REG_RA42_VALID_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_VALID_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA42_VALID_SIZE}, /* RA02_VALID5 (# 1080) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_17_14_REG_RA52_VALID_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_VALID_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA52_VALID_SIZE}, /* RA02_VALID6 (# 1081) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_1B_18_REG_RA62_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA62_VALID_SIZE}, /* RA02_VALID7 (# 1082) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA72_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA72_VALID_SIZE}, /* RA02_VALID8 (# 1083) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_23_20_REG_RA82_VALID_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_VALID_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA82_VALID_SIZE}, /* RA02_VALID9 (# 1084) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_27_24_REG_RA92_VALID_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_VALID_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA92_VALID_SIZE}, /* RA02_VALID10 (# 1085) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_2B_28_REG_RA102_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA102_VALID_SIZE}, /* RA02_VALID11 (# 1086) */ { (IFX_uint16_t)RA02_VALID, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA112_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA112_VALID_SIZE}, /* RA03_ACT (# 1087) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_ACT_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_ACT_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_ACT_SIZE}, /* RA03_ACT1 (# 1088) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_ACT_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_ACT_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_ACT_SIZE}, /* RA03_ACT2 (# 1089) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_ACT_SIZE}, /* RA03_ACT3 (# 1090) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_ACT_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_ACT_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_ACT_SIZE}, /* RA03_ACT4 (# 1091) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_ACT_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_ACT_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_ACT_SIZE}, /* RA03_ACT5 (# 1092) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_ACT_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_ACT_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_ACT_SIZE}, /* RA03_ACT6 (# 1093) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_ACT_SIZE}, /* RA03_ACT7 (# 1094) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_ACT_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_ACT_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_ACT_SIZE}, /* RA03_ACT8 (# 1095) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_ACT_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_ACT_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_ACT_SIZE}, /* RA03_ACT9 (# 1096) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_ACT_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_ACT_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_ACT_SIZE}, /* RA03_ACT10 (# 1097) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_ACT_SIZE}, /* RA03_ACT11 (# 1098) */ { (IFX_uint16_t)RA03_ACT, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_ACT_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_ACT_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_ACT_SIZE}, /* RA03_CV (# 1099) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_CV_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_CV_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_CV_SIZE}, /* RA03_CV1 (# 1100) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_CV_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_CV_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_CV_SIZE}, /* RA03_CV2 (# 1101) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_CV_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_CV_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_CV_SIZE}, /* RA03_CV3 (# 1102) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_CV_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_CV_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_CV_SIZE}, /* RA03_CV4 (# 1103) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_CV_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_CV_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_CV_SIZE}, /* RA03_CV5 (# 1104) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_CV_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_CV_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_CV_SIZE}, /* RA03_CV6 (# 1105) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_CV_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_CV_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_CV_SIZE}, /* RA03_CV7 (# 1106) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_CV_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_CV_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_CV_SIZE}, /* RA03_CV8 (# 1107) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_CV_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_CV_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_CV_SIZE}, /* RA03_CV9 (# 1108) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_CV_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_CV_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_CV_SIZE}, /* RA03_CV10 (# 1109) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_CV_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_CV_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_CV_SIZE}, /* RA03_CV11 (# 1110) */ { (IFX_uint16_t)RA03_CV, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_CV_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_CV_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_CV_SIZE}, /* RA03_MG (# 1111) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_MG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_MG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_MG_SIZE}, /* RA03_MG1 (# 1112) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_MG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_MG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_MG_SIZE}, /* RA03_MG2 (# 1113) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_MG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_MG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_MG_SIZE}, /* RA03_MG3 (# 1114) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_MG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_MG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_MG_SIZE}, /* RA03_MG4 (# 1115) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_MG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_MG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_MG_SIZE}, /* RA03_MG5 (# 1116) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_MG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_MG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_MG_SIZE}, /* RA03_MG6 (# 1117) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_MG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_MG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_MG_SIZE}, /* RA03_MG7 (# 1118) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_MG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_MG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_MG_SIZE}, /* RA03_MG8 (# 1119) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_MG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_MG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_MG_SIZE}, /* RA03_MG9 (# 1120) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_MG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_MG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_MG_SIZE}, /* RA03_MG10 (# 1121) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_MG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_MG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_MG_SIZE}, /* RA03_MG11 (# 1122) */ { (IFX_uint16_t)RA03_MG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_MG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_MG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_MG_SIZE}, /* RA03_SPAN (# 1123) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_SPAN_SIZE}, /* RA03_SPAN1 (# 1124) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_SPAN_SIZE}, /* RA03_SPAN2 (# 1125) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_SPAN_SIZE}, /* RA03_SPAN3 (# 1126) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_SPAN_SIZE}, /* RA03_SPAN4 (# 1127) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_SPAN_SIZE}, /* RA03_SPAN5 (# 1128) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_SPAN_SIZE}, /* RA03_SPAN6 (# 1129) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_SPAN_SIZE}, /* RA03_SPAN7 (# 1130) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_SPAN_SIZE}, /* RA03_SPAN8 (# 1131) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_SPAN_SIZE}, /* RA03_SPAN9 (# 1132) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_SPAN_SIZE}, /* RA03_SPAN10 (# 1133) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_SPAN_SIZE}, /* RA03_SPAN11 (# 1134) */ { (IFX_uint16_t)RA03_SPAN, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_SPAN_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_SPAN_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_SPAN_SIZE}, /* RA03_TXTAG (# 1135) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_TXTAG_SIZE}, /* RA03_TXTAG1 (# 1136) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_TXTAG_SIZE}, /* RA03_TXTAG2 (# 1137) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_TXTAG_SIZE}, /* RA03_TXTAG3 (# 1138) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_TXTAG_SIZE}, /* RA03_TXTAG4 (# 1139) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_TXTAG_SIZE}, /* RA03_TXTAG5 (# 1140) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_TXTAG_SIZE}, /* RA03_TXTAG6 (# 1141) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_TXTAG_SIZE}, /* RA03_TXTAG7 (# 1142) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_TXTAG_SIZE}, /* RA03_TXTAG8 (# 1143) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_TXTAG_SIZE}, /* RA03_TXTAG9 (# 1144) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_TXTAG_SIZE}, /* RA03_TXTAG10 (# 1145) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_TXTAG_SIZE}, /* RA03_TXTAG11 (# 1146) */ { (IFX_uint16_t)RA03_TXTAG, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_TXTAG_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_TXTAG_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_TXTAG_SIZE}, /* RA03_VALID (# 1147) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_03_00_REG_RA03_VALID_OFFSET, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_VALID_SHIFT, (IFX_uint8_t)AR9_RA_03_00_REG_RA03_VALID_SIZE}, /* RA03_VALID1 (# 1148) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_07_04_REG_RA13_VALID_OFFSET, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_VALID_SHIFT, (IFX_uint8_t)AR9_RA_07_04_REG_RA13_VALID_SIZE}, /* RA03_VALID2 (# 1149) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_0B_08_REG_RA23_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0B_08_REG_RA23_VALID_SIZE}, /* RA03_VALID3 (# 1150) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_0F_0C_REG_RA33_VALID_OFFSET, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_VALID_SHIFT, (IFX_uint8_t)AR9_RA_0F_0C_REG_RA33_VALID_SIZE}, /* RA03_VALID4 (# 1151) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_13_10_REG_RA43_VALID_OFFSET, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_VALID_SHIFT, (IFX_uint8_t)AR9_RA_13_10_REG_RA43_VALID_SIZE}, /* RA03_VALID5 (# 1152) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_17_14_REG_RA53_VALID_OFFSET, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_VALID_SHIFT, (IFX_uint8_t)AR9_RA_17_14_REG_RA53_VALID_SIZE}, /* RA03_VALID6 (# 1153) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_1B_18_REG_RA63_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1B_18_REG_RA63_VALID_SIZE}, /* RA03_VALID7 (# 1154) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_1F_1C_REG_RA73_VALID_OFFSET, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_VALID_SHIFT, (IFX_uint8_t)AR9_RA_1F_1C_REG_RA73_VALID_SIZE}, /* RA03_VALID8 (# 1155) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_23_20_REG_RA83_VALID_OFFSET, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_VALID_SHIFT, (IFX_uint8_t)AR9_RA_23_20_REG_RA83_VALID_SIZE}, /* RA03_VALID9 (# 1156) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_27_24_REG_RA93_VALID_OFFSET, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_VALID_SHIFT, (IFX_uint8_t)AR9_RA_27_24_REG_RA93_VALID_SIZE}, /* RA03_VALID10 (# 1157) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_2B_28_REG_RA103_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2B_28_REG_RA103_VALID_SIZE}, /* RA03_VALID11 (# 1158) */ { (IFX_uint16_t)RA03_VALID, (IFX_uint16_t)AR9_RA_2F_2C_REG_RA113_VALID_OFFSET, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_VALID_SHIFT, (IFX_uint8_t)AR9_RA_2F_2C_REG_RA113_VALID_SIZE}, /* RMON_BAS (# 1159) */ { (IFX_uint16_t)RMON_BAS, (IFX_uint16_t)AR9_RMON_CTL_REG_BAS_OFFSET, (IFX_uint8_t)AR9_RMON_CTL_REG_BAS_SHIFT, (IFX_uint8_t)AR9_RMON_CTL_REG_BAS_SIZE}, /* RMON_CAC (# 1160) */ { (IFX_uint16_t)RMON_CAC, (IFX_uint16_t)AR9_RMON_CTL_REG_CAC_OFFSET, (IFX_uint8_t)AR9_RMON_CTL_REG_CAC_SHIFT, (IFX_uint8_t)AR9_RMON_CTL_REG_CAC_SIZE}, /* RMON_COUNTER (# 1161) */ { (IFX_uint16_t)RMON_COUNTER, (IFX_uint16_t)AR9_RMON_ST_REG_COUNTER_OFFSET, (IFX_uint8_t)AR9_RMON_ST_REG_COUNTER_SHIFT, (IFX_uint8_t)AR9_RMON_ST_REG_COUNTER_SIZE}, /* RMON_HIGH_COUNTER (# 1162) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RMON_LOW_COUNTER (# 1163) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RMON_OFFSET (# 1164) */ { (IFX_uint16_t)RMON_OFFSET, (IFX_uint16_t)AR9_RMON_CTL_REG_OFFSET_OFFSET, (IFX_uint8_t)AR9_RMON_CTL_REG_OFFSET_SHIFT, (IFX_uint8_t)AR9_RMON_CTL_REG_OFFSET_SIZE}, /* RMON_PORTC (# 1165) */ { (IFX_uint16_t)RMON_PORTC, (IFX_uint16_t)AR9_RMON_CTL_REG_PORTC_OFFSET, (IFX_uint8_t)AR9_RMON_CTL_REG_PORTC_SHIFT, (IFX_uint8_t)AR9_RMON_CTL_REG_PORTC_SIZE}, /* TYPE_FILTER_ATF (# 1166) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF0_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF0_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF0_SIZE}, /* TYPE_FILTER_ATF1 (# 1167) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF1_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF1_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF1_SIZE}, /* TYPE_FILTER_ATF2 (# 1168) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF2_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF2_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF2_SIZE}, /* TYPE_FILTER_ATF3 (# 1169) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF3_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF3_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF3_SIZE}, /* TYPE_FILTER_ATF4 (# 1170) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF4_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF4_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF4_SIZE}, /* TYPE_FILTER_ATF5 (# 1171) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF5_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF5_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF5_SIZE}, /* TYPE_FILTER_ATF6 (# 1172) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF6_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF6_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF6_SIZE}, /* TYPE_FILTER_ATF7 (# 1173) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_ATF7_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF7_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_ATF7_SIZE}, /* TYPE_FILTER_QTF (# 1174) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF0_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF0_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF0_SIZE}, /* TYPE_FILTER_QTF1 (# 1175) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF1_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF1_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF1_SIZE}, /* TYPE_FILTER_QTF2 (# 1176) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF2_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF2_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF2_SIZE}, /* TYPE_FILTER_QTF3 (# 1177) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF3_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF3_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF3_SIZE}, /* TYPE_FILTER_QTF4 (# 1178) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF4_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF4_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF4_SIZE}, /* TYPE_FILTER_QTF5 (# 1179) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QTF5_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF5_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QTF5_SIZE}, /* TYPE_FILTER_QTF6 (# 1180) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QATF6_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QATF6_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QATF6_SIZE}, /* TYPE_FILTER_QTF7 (# 1181) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)AR9_TP_FLT_ACT_REG_QATF7_OFFSET, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QATF7_SHIFT, (IFX_uint8_t)AR9_TP_FLT_ACT_REG_QATF7_SIZE}, /* TYPE_FILTER_VCET0 (# 1182) */ { (IFX_uint16_t)TYPE_FILTER_VCET0, (IFX_uint16_t)AR9_TP_FLT10_REG_VCET0_OFFSET, (IFX_uint8_t)AR9_TP_FLT10_REG_VCET0_SHIFT, (IFX_uint8_t)AR9_TP_FLT10_REG_VCET0_SIZE}, /* TYPE_FILTER_VCET01 (# 1183) */ { (IFX_uint16_t)TYPE_FILTER_VCET0, (IFX_uint16_t)AR9_TP_FLT32_REG_VCET0_OFFSET, (IFX_uint8_t)AR9_TP_FLT32_REG_VCET0_SHIFT, (IFX_uint8_t)AR9_TP_FLT32_REG_VCET0_SIZE}, /* TYPE_FILTER_VCET02 (# 1184) */ { (IFX_uint16_t)TYPE_FILTER_VCET0, (IFX_uint16_t)AR9_TP_FLT54_REG_VCET0_OFFSET, (IFX_uint8_t)AR9_TP_FLT54_REG_VCET0_SHIFT, (IFX_uint8_t)AR9_TP_FLT54_REG_VCET0_SIZE}, /* TYPE_FILTER_VCET03 (# 1185) */ { (IFX_uint16_t)TYPE_FILTER_VCET0, (IFX_uint16_t)AR9_TP_FLT76_REG_VCET0_OFFSET, (IFX_uint8_t)AR9_TP_FLT76_REG_VCET0_SHIFT, (IFX_uint8_t)AR9_TP_FLT76_REG_VCET0_SIZE}, /* TYPE_FILTER_VCET1 (# 1186) */ { (IFX_uint16_t)TYPE_FILTER_VCET1, (IFX_uint16_t)AR9_TP_FLT10_REG_VCET1_OFFSET, (IFX_uint8_t)AR9_TP_FLT10_REG_VCET1_SHIFT, (IFX_uint8_t)AR9_TP_FLT10_REG_VCET1_SIZE}, /* TYPE_FILTER_VCET11 (# 1187) */ { (IFX_uint16_t)TYPE_FILTER_VCET1, (IFX_uint16_t)AR9_TP_FLT32_REG_VCET1_OFFSET, (IFX_uint8_t)AR9_TP_FLT32_REG_VCET1_SHIFT, (IFX_uint8_t)AR9_TP_FLT32_REG_VCET1_SIZE}, /* TYPE_FILTER_VCET12 (# 1188) */ { (IFX_uint16_t)TYPE_FILTER_VCET1, (IFX_uint16_t)AR9_TP_FLT54_REG_VCET1_OFFSET, (IFX_uint8_t)AR9_TP_FLT54_REG_VCET1_SHIFT, (IFX_uint8_t)AR9_TP_FLT54_REG_VCET1_SIZE}, /* TYPE_FILTER_VCET13 (# 1189) */ { (IFX_uint16_t)TYPE_FILTER_VCET1, (IFX_uint16_t)AR9_TP_FLT76_REG_VCET1_OFFSET, (IFX_uint8_t)AR9_TP_FLT76_REG_VCET1_SHIFT, (IFX_uint8_t)AR9_TP_FLT76_REG_VCET1_SIZE}, /* TYPE_FILTER_VCET_ALL (# 1190) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL1 (# 1191) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL2 (# 1192) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL3 (# 1193) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL4 (# 1194) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL5 (# 1195) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL6 (# 1196) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL7 (# 1197) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* VLAN_FILTER_M (# 1198) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT0_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_M_SIZE}, /* VLAN_FILTER_M1 (# 1199) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT1_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_M_SIZE}, /* VLAN_FILTER_M2 (# 1200) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT2_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_M_SIZE}, /* VLAN_FILTER_M3 (# 1201) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT3_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_M_SIZE}, /* VLAN_FILTER_M4 (# 1202) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT4_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_M_SIZE}, /* VLAN_FILTER_M5 (# 1203) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT5_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_M_SIZE}, /* VLAN_FILTER_M6 (# 1204) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT6_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_M_SIZE}, /* VLAN_FILTER_M7 (# 1205) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT7_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_M_SIZE}, /* VLAN_FILTER_M8 (# 1206) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT8_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_M_SIZE}, /* VLAN_FILTER_M9 (# 1207) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT9_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_M_SIZE}, /* VLAN_FILTER_M10 (# 1208) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT10_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_M_SIZE}, /* VLAN_FILTER_M11 (# 1209) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT11_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_M_SIZE}, /* VLAN_FILTER_M12 (# 1210) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT12_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_M_SIZE}, /* VLAN_FILTER_M13 (# 1211) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT13_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_M_SIZE}, /* VLAN_FILTER_M14 (# 1212) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT14_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_M_SIZE}, /* VLAN_FILTER_M15 (# 1213) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)AR9_VLAN_FLT15_REG_M_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_M_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_M_SIZE}, /* VLAN_FILTER_TM (# 1214) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT0_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_TM_SIZE}, /* VLAN_FILTER_TM1 (# 1215) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT1_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_TM_SIZE}, /* VLAN_FILTER_TM2 (# 1216) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT2_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_TM_SIZE}, /* VLAN_FILTER_TM3 (# 1217) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT3_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_TM_SIZE}, /* VLAN_FILTER_TM4 (# 1218) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT4_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_TM_SIZE}, /* VLAN_FILTER_TM5 (# 1219) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT5_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_TM_SIZE}, /* VLAN_FILTER_TM6 (# 1220) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT6_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_TM_SIZE}, /* VLAN_FILTER_TM7 (# 1221) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT7_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_TM_SIZE}, /* VLAN_FILTER_TM8 (# 1222) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT8_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_TM_SIZE}, /* VLAN_FILTER_TM9 (# 1223) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT9_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_TM_SIZE}, /* VLAN_FILTER_TM10 (# 1224) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT10_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_TM_SIZE}, /* VLAN_FILTER_TM11 (# 1225) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT11_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_TM_SIZE}, /* VLAN_FILTER_TM12 (# 1226) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT12_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_TM_SIZE}, /* VLAN_FILTER_TM13 (# 1227) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT13_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_TM_SIZE}, /* VLAN_FILTER_TM14 (# 1228) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT14_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_TM_SIZE}, /* VLAN_FILTER_TM15 (# 1229) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)AR9_VLAN_FLT15_REG_TM_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_TM_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_TM_SIZE}, /* VLAN_FILTER_VFID (# 1230) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT0_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_FID_SIZE}, /* VLAN_FILTER_VFID1 (# 1231) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT1_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_FID_SIZE}, /* VLAN_FILTER_VFID2 (# 1232) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT2_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_FID_SIZE}, /* VLAN_FILTER_VFID3 (# 1233) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT3_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_FID_SIZE}, /* VLAN_FILTER_VFID4 (# 1234) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT4_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_FID_SIZE}, /* VLAN_FILTER_VFID5 (# 1235) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT5_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_FID_SIZE}, /* VLAN_FILTER_VFID6 (# 1236) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT6_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_FID_SIZE}, /* VLAN_FILTER_VFID7 (# 1237) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT7_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_FID_SIZE}, /* VLAN_FILTER_VFID8 (# 1238) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT8_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_FID_SIZE}, /* VLAN_FILTER_VFID9 (# 1239) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT9_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_FID_SIZE}, /* VLAN_FILTER_VFID10 (# 1240) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT10_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_FID_SIZE}, /* VLAN_FILTER_VFID11 (# 1241) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT11_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_FID_SIZE}, /* VLAN_FILTER_VFID12 (# 1242) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT12_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_FID_SIZE}, /* VLAN_FILTER_VFID13 (# 1243) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT13_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_FID_SIZE}, /* VLAN_FILTER_VFID14 (# 1244) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT14_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_FID_SIZE}, /* VLAN_FILTER_VFID15 (# 1245) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)AR9_VLAN_FLT15_REG_FID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_FID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_FID_SIZE}, /* VLAN_FILTER_VID (# 1246) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT0_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VID_SIZE}, /* VLAN_FILTER_VID1 (# 1247) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT1_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VID_SIZE}, /* VLAN_FILTER_VID2 (# 1248) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT2_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VID_SIZE}, /* VLAN_FILTER_VID3 (# 1249) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT3_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VID_SIZE}, /* VLAN_FILTER_VID4 (# 1250) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT4_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VID_SIZE}, /* VLAN_FILTER_VID5 (# 1251) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT5_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VID_SIZE}, /* VLAN_FILTER_VID6 (# 1252) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT6_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VID_SIZE}, /* VLAN_FILTER_VID7 (# 1253) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT7_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VID_SIZE}, /* VLAN_FILTER_VID8 (# 1254) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT8_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VID_SIZE}, /* VLAN_FILTER_VID9 (# 1255) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT9_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VID_SIZE}, /* VLAN_FILTER_VID10 (# 1256) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT10_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VID_SIZE}, /* VLAN_FILTER_VID11 (# 1257) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT11_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VID_SIZE}, /* VLAN_FILTER_VID12 (# 1258) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT12_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VID_SIZE}, /* VLAN_FILTER_VID13 (# 1259) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT13_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VID_SIZE}, /* VLAN_FILTER_VID14 (# 1260) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT14_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VID_SIZE}, /* VLAN_FILTER_VID15 (# 1261) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)AR9_VLAN_FLT15_REG_VID_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VID_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VID_SIZE}, /* VLAN_FILTER_VP (# 1262) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT0_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VP_SIZE}, /* VLAN_FILTER_VP1 (# 1263) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT1_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VP_SIZE}, /* VLAN_FILTER_VP2 (# 1264) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT2_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VP_SIZE}, /* VLAN_FILTER_VP3 (# 1265) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT3_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VP_SIZE}, /* VLAN_FILTER_VP4 (# 1266) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT4_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VP_SIZE}, /* VLAN_FILTER_VP5 (# 1267) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT5_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VP_SIZE}, /* VLAN_FILTER_VP6 (# 1268) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT6_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VP_SIZE}, /* VLAN_FILTER_VP7 (# 1269) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT7_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VP_SIZE}, /* VLAN_FILTER_VP8 (# 1270) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT8_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VP_SIZE}, /* VLAN_FILTER_VP9 (# 1271) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT9_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VP_SIZE}, /* VLAN_FILTER_VP10 (# 1272) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT10_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VP_SIZE}, /* VLAN_FILTER_VP11 (# 1273) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT11_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VP_SIZE}, /* VLAN_FILTER_VP12 (# 1274) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT12_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VP_SIZE}, /* VLAN_FILTER_VP13 (# 1275) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT13_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VP_SIZE}, /* VLAN_FILTER_VP14 (# 1276) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT14_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VP_SIZE}, /* VLAN_FILTER_VP15 (# 1277) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)AR9_VLAN_FLT15_REG_VP_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VP_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VP_SIZE}, /* VLAN_FILTER_VV (# 1278) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT0_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT0_REG_VV_SIZE}, /* VLAN_FILTER_VV1 (# 1279) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT1_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT1_REG_VV_SIZE}, /* VLAN_FILTER_VV2 (# 1280) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT2_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT2_REG_VV_SIZE}, /* VLAN_FILTER_VV3 (# 1281) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT3_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT3_REG_VV_SIZE}, /* VLAN_FILTER_VV4 (# 1282) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT4_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT4_REG_VV_SIZE}, /* VLAN_FILTER_VV5 (# 1283) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT5_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT5_REG_VV_SIZE}, /* VLAN_FILTER_VV6 (# 1284) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT6_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT6_REG_VV_SIZE}, /* VLAN_FILTER_VV7 (# 1285) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT7_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT7_REG_VV_SIZE}, /* VLAN_FILTER_VV8 (# 1286) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT8_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT8_REG_VV_SIZE}, /* VLAN_FILTER_VV9 (# 1287) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT9_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT9_REG_VV_SIZE}, /* VLAN_FILTER_VV10 (# 1288) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT10_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT10_REG_VV_SIZE}, /* VLAN_FILTER_VV11 (# 1289) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT11_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT11_REG_VV_SIZE}, /* VLAN_FILTER_VV12 (# 1290) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT12_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT12_REG_VV_SIZE}, /* VLAN_FILTER_VV13 (# 1291) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT13_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT13_REG_VV_SIZE}, /* VLAN_FILTER_VV14 (# 1292) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT14_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT14_REG_VV_SIZE}, /* VLAN_FILTER_VV15 (# 1293) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)AR9_VLAN_FLT15_REG_VV_OFFSET, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VV_SHIFT, (IFX_uint8_t)AR9_VLAN_FLT15_REG_VV_SIZE}, /* Last Element (# 1294) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0} }; #ifdef IFX_ETHSW_DEBUG char regMapper_AR9_Names = [] = { "ARP_REG.APT" /* ARP_APT (# 0) */, "ARP_REG.MACA" /* ARP_MACA (# 1) */, "ARP_REG.RAPA" /* ARP_RAPA (# 2) */, "ARP_REG.RAPOTH" /* ARP_RAPOTH (# 3) */, "ARP_REG.RAPP" /* ARP_RAPP (# 4) */, "ARP_REG.RAPPE" /* ARP_RAPPE (# 5) */, "ARP_REG.RAPTM" /* ARP_RAPTM (# 6) */, "ARP_REG.RPT" /* ARP_RPT (# 7) */, "ARP_REG.TAP" /* ARP_TAP (# 8) */, "ARP_REG.TAPTS" /* ARP_TAPTS (# 9) */, "ARP_REG.TRP" /* ARP_TRP (# 10) */, "ARP_REG.UPT" /* ARP_UPT (# 11) */, NULL /* BIST_CTBR (# 12) */, NULL /* BIST_DBBR (# 13) */, "SW_GCTL1_REG.BISTDN" /* BIST_DONE (# 14) */, NULL /* BIST_HIGTBR (# 15) */, NULL /* BIST_HISTBR (# 16) */, NULL /* BIST_LLTBR (# 17) */, NULL /* BIST_LTBR (# 18) */, "BF_TH_REG.PFA" /* BUFFER_PFA (# 19) */, "BF_TH_REG.PFO0" /* BUFFER_PFO0 (# 20) */, "BF_TH_REG.PFO1" /* BUFFER_PFO1 (# 21) */, "BF_TH_REG.PFO2" /* BUFFER_PFO2 (# 22) */, "BF_TH_REG.PUA" /* BUFFER_PUA (# 23) */, "BF_TH_REG.PUO0" /* BUFFER_PUO0 (# 24) */, "BF_TH_REG.PUO1" /* BUFFER_PUO1 (# 25) */, "BF_TH_REG.PUO2" /* BUFFER_PUO2 (# 26) */, "BF_TH_REG.THA" /* BUFFER_THA (# 27) */, "BF_TH_REG.THO" /* BUFFER_THO (# 28) */, "BF_TH_REG.TLA" /* BUFFER_TLA (# 29) */, "BF_TH_REG.TLO" /* BUFFER_TLO (# 30) */, NULL /* CHIPID_BOND (# 31) */, NULL /* CHIPID_PC (# 32) */, NULL /* CHIPID_VN (# 33) */, "SW_GCTL1_REG.EDSTX" /* CONGESTION_EDSTX (# 34) */, "SW_GCTL1_REG.IJT" /* CONGESTION_IJT (# 35) */, NULL /* CONGESTION_IRSJA (# 36) */, "STRM_CTL_REG.STORM_100_TH" /* CONGESTION_STORM_100_TH (# 37) */, "STRM_CTL_REG.STORM_10_TH" /* CONGESTION_STORM_10_TH (# 38) */, "STRM_CTL_REG.STORM_B" /* CONGESTION_STORM_B (# 39) */, "STRM_CTL_REG.STORM_M" /* CONGESTION_STORM_M (# 40) */, "STRM_CTL_REG.STORM_U" /* CONGESTION_STORM_U (# 41) */, "DFSRV_MAP0_REG.PQ0" /* DIFFSERV_PQA (# 42) */, "DFSRV_MAP0_REG.PQ1" /* DIFFSERV_PQA01 (# 43) */, "DFSRV_MAP0_REG.PQ2" /* DIFFSERV_PQA02 (# 44) */, "DFSRV_MAP0_REG.PQ3" /* DIFFSERV_PQA03 (# 45) */, "DFSRV_MAP0_REG.PQ4" /* DIFFSERV_PQA04 (# 46) */, "DFSRV_MAP0_REG.PQ5" /* DIFFSERV_PQA05 (# 47) */, "DFSRV_MAP0_REG.PQ6" /* DIFFSERV_PQA06 (# 48) */, "DFSRV_MAP0_REG.PQ7" /* DIFFSERV_PQA07 (# 49) */, "DFSRV_MAP0_REG.PQ8" /* DIFFSERV_PQA08 (# 50) */, "DFSRV_MAP0_REG.PQ9" /* DIFFSERV_PQA09 (# 51) */, "DFSRV_MAP0_REG.PQA" /* DIFFSERV_PQA10 (# 52) */, "DFSRV_MAP0_REG.PQB" /* DIFFSERV_PQA11 (# 53) */, "DFSRV_MAP0_REG.PQC" /* DIFFSERV_PQA12 (# 54) */, "DFSRV_MAP0_REG.PQD" /* DIFFSERV_PQA13 (# 55) */, "DFSRV_MAP0_REG.PQE" /* DIFFSERV_PQA14 (# 56) */, "DFSRV_MAP0_REG.PQF" /* DIFFSERV_PQA15 (# 57) */, "DFSRV_MAP1_REG.PQ10" /* DIFFSERV_PQB (# 58) */, "DFSRV_MAP1_REG.PQ11" /* DIFFSERV_PQB01 (# 59) */, "DFSRV_MAP1_REG.PQ12" /* DIFFSERV_PQB02 (# 60) */, "DFSRV_MAP1_REG.PQ13" /* DIFFSERV_PQB03 (# 61) */, "DFSRV_MAP1_REG.PQ14" /* DIFFSERV_PQB04 (# 62) */, "DFSRV_MAP1_REG.PQ15" /* DIFFSERV_PQB05 (# 63) */, "DFSRV_MAP1_REG.PQ16" /* DIFFSERV_PQB06 (# 64) */, "DFSRV_MAP1_REG.PQ17" /* DIFFSERV_PQB07 (# 65) */, "DFSRV_MAP1_REG.PQ18" /* DIFFSERV_PQB08 (# 66) */, "DFSRV_MAP1_REG.PQ19" /* DIFFSERV_PQB09 (# 67) */, "DFSRV_MAP1_REG.PQ1A" /* DIFFSERV_PQB10 (# 68) */, "DFSRV_MAP1_REG.PQ1B" /* DIFFSERV_PQB11 (# 69) */, "DFSRV_MAP1_REG.PQ1C" /* DIFFSERV_PQB12 (# 70) */, "DFSRV_MAP1_REG.PQ1D" /* DIFFSERV_PQB13 (# 71) */, "DFSRV_MAP1_REG.PQ1E" /* DIFFSERV_PQB14 (# 72) */, "DFSRV_MAP1_REG.PQ1F" /* DIFFSERV_PQB15 (# 73) */, "DFSRV_MAP2_REG.PQ20" /* DIFFSERV_PQC (# 74) */, "DFSRV_MAP2_REG.PQ21" /* DIFFSERV_PQC01 (# 75) */, "DFSRV_MAP2_REG.PQ22" /* DIFFSERV_PQC02 (# 76) */, "DFSRV_MAP2_REG.PQ23" /* DIFFSERV_PQC03 (# 77) */, "DFSRV_MAP2_REG.PQ24" /* DIFFSERV_PQC04 (# 78) */, "DFSRV_MAP2_REG.PQ25" /* DIFFSERV_PQC05 (# 79) */, "DFSRV_MAP2_REG.PQ26" /* DIFFSERV_PQC06 (# 80) */, "DFSRV_MAP2_REG.PQ27" /* DIFFSERV_PQC07 (# 81) */, "DFSRV_MAP2_REG.PQ28" /* DIFFSERV_PQC08 (# 82) */, "DFSRV_MAP2_REG.PQ29" /* DIFFSERV_PQC09 (# 83) */, "DFSRV_MAP2_REG.PQ2A" /* DIFFSERV_PQC10 (# 84) */, "DFSRV_MAP2_REG.PQ2B" /* DIFFSERV_PQC11 (# 85) */, "DFSRV_MAP2_REG.PQ2C" /* DIFFSERV_PQC12 (# 86) */, "DFSRV_MAP2_REG.PQ2D" /* DIFFSERV_PQC13 (# 87) */, "DFSRV_MAP2_REG.PQ2E" /* DIFFSERV_PQC14 (# 88) */, "DFSRV_MAP2_REG.PQ2F" /* DIFFSERV_PQC15 (# 89) */, "DFSRV_MAP3_REG.PQ30" /* DIFFSERV_PQD (# 90) */, "DFSRV_MAP3_REG.PQ31" /* DIFFSERV_PQD01 (# 91) */, "DFSRV_MAP3_REG.PQ32" /* DIFFSERV_PQD02 (# 92) */, "DFSRV_MAP3_REG.PQ33" /* DIFFSERV_PQD03 (# 93) */, "DFSRV_MAP3_REG.PQ34" /* DIFFSERV_PQD04 (# 94) */, "DFSRV_MAP3_REG.PQ35" /* DIFFSERV_PQD05 (# 95) */, "DFSRV_MAP3_REG.PQ36" /* DIFFSERV_PQD06 (# 96) */, "DFSRV_MAP3_REG.PQ37" /* DIFFSERV_PQD07 (# 97) */, "DFSRV_MAP3_REG.PQ38" /* DIFFSERV_PQD08 (# 98) */, "DFSRV_MAP3_REG.PQ39" /* DIFFSERV_PQD09 (# 99) */, "DFSRV_MAP3_REG.PQ3A" /* DIFFSERV_PQD10 (# 100) */, "DFSRV_MAP3_REG.PQ3B" /* DIFFSERV_PQD11 (# 101) */, "DFSRV_MAP3_REG.PQ3C" /* DIFFSERV_PQD12 (# 102) */, "DFSRV_MAP3_REG.PQ3D" /* DIFFSERV_PQD13 (# 103) */, "DFSRV_MAP3_REG.PQ3E" /* DIFFSERV_PQD14 (# 104) */, "DFSRV_MAP3_REG.PQ3F" /* DIFFSERV_PQD15 (# 105) */, "1P_PRT_REG.1PPQ0" /* DOT1X_PRIORITY_1PPQ (# 106) */, "1P_PRT_REG.1PPQ1" /* DOT1X_PRIORITY_1PPQ1 (# 107) */, "1P_PRT_REG.1PPQ2" /* DOT1X_PRIORITY_1PPQ2 (# 108) */, "1P_PRT_REG.1PPQ3" /* DOT1X_PRIORITY_1PPQ3 (# 109) */, "1P_PRT_REG.1PPQ4" /* DOT1X_PRIORITY_1PPQ4 (# 110) */, "1P_PRT_REG.1PPQ5" /* DOT1X_PRIORITY_1PPQ5 (# 111) */, "1P_PRT_REG.1PPQ6" /* DOT1X_PRIORITY_1PPQ6 (# 112) */, "1P_PRT_REG.1PPQ7" /* DOT1X_PRIORITY_1PPQ7 (# 113) */, "SW_GCTL0_REG.ATS" /* GLOBAL_ATS (# 114) */, "SW_GCTL1_REG.CTTX" /* GLOBAL_CTTX (# 115) */, "SW_GCTL1_REG.DIE" /* GLOBAL_DIE (# 116) */, "SW_GCTL1_REG.DII6P" /* GLOBAL_DII6P (# 117) */, "SW_GCTL1_REG.DIIP" /* GLOBAL_DIIP (# 118) */, "SW_GCTL1_REG.DIIPS" /* GLOBAL_DIIPS (# 119) */, "SW_GCTL1_REG.DIS" /* GLOBAL_DIS (# 120) */, "SW_GCTL1_REG.DIVS" /* GLOBAL_DIVS (# 121) */, "SW_GCTL0_REG.DMQ0" /* GLOBAL_DMQ0 (# 122) */, "SW_GCTL0_REG.DMQ1" /* GLOBAL_DMQ1 (# 123) */, "SW_GCTL0_REG.DMQ2" /* GLOBAL_DMQ2 (# 124) */, "SW_GCTL0_REG.DMQ3" /* GLOBAL_DMQ3 (# 125) */, "SW_GCTL0_REG.DPWECH" /* GLOBAL_DPWECH (# 126) */, NULL /* GLOBAL_DUPCOLSP (# 127) */, "SW_GCTL0_REG.ICRCCD" /* GLOBAL_ICRCCD (# 128) */, NULL /* GLOBAL_ITENLMT (# 129) */, NULL /* GLOBAL_ITRUNK (# 130) */, "SW_GCTL0_REG.LPE" /* GLOBAL_LPE (# 131) */, "SW_GCTL0_REG.MPL" /* GLOBAL_MPL (# 132) */, NULL /* GLOBAL_P4M (# 133) */, NULL /* GLOBAL_P5M (# 134) */, NULL /* GLOBAL_P6M (# 135) */, "SW_GCTL0_REG.PCE" /* GLOBAL_PCE (# 136) */, "SW_GCTL0_REG.PCR" /* GLOBAL_PCR (# 137) */, "SW_GCTL0_REG.PHYBA" /* GLOBAL_PHYBA (# 138) */, "SW_GCTL0_REG.RVID0" /* GLOBAL_RVID0 (# 139) */, "SW_GCTL0_REG.RVID1" /* GLOBAL_RVID1 (# 140) */, "SW_GCTL0_REG.RVIDFFF" /* GLOBAL_RVIDFFF (# 141) */, "SW_GCTL0_REG.SE" /* GLOBAL_SE (# 142) */, "SW_GCTL0_REG.TSIPGE" /* GLOBAL_TSIPGE (# 143) */, "PAUSE_OFF_WM.B" /* INGRESS_FLOW_CTRL_B (# 144) */, NULL /* INGRESS_FLOW_CTRL_BASE15_0 (# 145) */, NULL /* INGRESS_FLOW_CTRL_BASE17_16 (# 146) */, NULL /* INGRESS_FLOW_CTRL_EBASE15_0 (# 147) */, NULL /* INGRESS_FLOW_CTRL_EBASE17_16 (# 148) */, "PAUSE_ON_WM.F" /* INGRESS_FLOW_CTRL_F (# 149) */, "INT_ST_REG.DBF" /* IRQ_DBF (# 150) */, "INT_ENA_REG.DBFIE" /* IRQ_DBFIE (# 151) */, "INT_ST_REG.DBNF" /* IRQ_DBNF (# 152) */, "INT_ENA_REG.DBNFIE" /* IRQ_DBNFIE (# 153) */, "INT_ST_REG.LTAD" /* IRQ_LTAD (# 154) */, "INT_ENA_REG.LTADIE" /* IRQ_LTADIE (# 155) */, "INT_ST_REG.LTF" /* IRQ_LTF (# 156) */, "INT_ENA_REG.LTFIE" /* IRQ_LTFIE (# 157) */, "INT_ST_REG.PSC" /* IRQ_PSC (# 158) */, "INT_ENA_REG.PSCIE" /* IRQ_PSCIE (# 159) */, "INT_ST_REG.PSV" /* IRQ_PSV (# 160) */, "INT_ENA_REG.PSVIE" /* IRQ_PSVIE (# 161) */, NULL /* MAC_TABLE_ADDR15_0 (# 162) */, "ADR_TB_CTL0_REG.ADDR31_0" /* MAC_TABLE_ADDR31_0 (# 163) */, NULL /* MAC_TABLE_ADDR31_16 (# 164) */, "ADR_TB_CTL1_REG.ADDR47_32" /* MAC_TABLE_ADDR47_32 (# 165) */, NULL /* MAC_TABLE_ADDRS15_0 (# 166) */, "ADR_TB_ST0_REG.ADDRS31_0" /* MAC_TABLE_ADDRS31_0 (# 167) */, NULL /* MAC_TABLE_ADDRS31_16 (# 168) */, "ADR_TB_ST1_REG.ADDRS47_32" /* MAC_TABLE_ADDRS47_32 (# 169) */, "ADR_TB_ST2_REG.BAD" /* MAC_TABLE_BAD (# 170) */, "ADR_TB_ST2_REG.BUSY" /* MAC_TABLE_BUSY (# 171) */, "ADR_TB_CTL2_REG.AC" /* MAC_TABLE_C_AC (# 172) */, "ADR_TB_CTL2_REG.CMD" /* MAC_TABLE_C_CMD (# 173) */, "ADR_TB_CTL2_REG.IFCE" /* MAC_TABLE_C_FCE (# 174) */, "ADR_TB_CTL1_REG.FID" /* MAC_TABLE_FID (# 175) */, "ADR_TB_ST1_REG.FIDS" /* MAC_TABLE_FIDS (# 176) */, "ADR_TB_CTL2_REG.INFOT" /* MAC_TABLE_INFOT (# 177) */, "ADR_TB_ST2_REG.INFOTS" /* MAC_TABLE_INFOTS (# 178) */, "ADR_TB_CTL2_REG.ITAT" /* MAC_TABLE_ITAT (# 179) */, "ADR_TB_ST2_REG.ITATS" /* MAC_TABLE_ITATS (# 180) */, "ADR_TB_ST2_REG.OCP" /* MAC_TABLE_OCP (# 181) */, "ADR_TB_CTL1_REG.PMAP" /* MAC_TABLE_PMAP (# 182) */, "ADR_TB_ST1_REG.PMAPS" /* MAC_TABLE_PMAPS (# 183) */, "ADR_TB_ST2_REG.RSLT" /* MAC_TABLE_RSLT (# 184) */, "ADR_TB_ST2_REG.AC" /* MAC_TABLE_S_AC (# 185) */, "ADR_TB_ST2_REG.CMD" /* MAC_TABLE_S_CMD (# 186) */, NULL /* MAC_TABLE_S_FCE (# 187) */, "RGMII_CTL_REG.MCS" /* MCS (# 188) */, "MDIO_CTL_REG.MBUSY" /* MDIO_MBUSY (# 189) */, "MDIO_CTL_REG.OP" /* MDIO_OP (# 190) */, "MDIO_CTL_REG.PHYAD" /* MDIO_PHYAD (# 191) */, "MDIO_DATA_REG.RD" /* MDIO_RD (# 192) */, "MDIO_CTL_REG.REGAD" /* MDIO_REGAD (# 193) */, "MDIO_CTL_REG.WD" /* MDIO_WD (# 194) */, NULL /* MIRROR_CCCRC (# 195) */, NULL /* MIRROR_CPN (# 196) */, NULL /* MIRROR_IGSTA (# 197) */, "SW_GCTL0_REG.MCA" /* MIRROR_MCA (# 198) */, "SW_GCTL0_REG.MLA" /* MIRROR_MLA (# 199) */, "SW_GCTL0_REG.MPA" /* MIRROR_MPA (# 200) */, "SW_GCTL0_REG.MRA" /* MIRROR_MRA (# 201) */, "SW_GCTL0_REG.MSA" /* MIRROR_MSA (# 202) */, NULL /* MIRROR_PAST (# 203) */, "SW_GCTL0_REG.SNIFFPN" /* MIRROR_SNIFFPN (# 204) */, NULL /* MIRROR_STRE (# 205) */, NULL /* MIRROR_STTE (# 206) */, NULL /* MULTICAST_ASC (# 207) */, NULL /* MULTICAST_B01 (# 208) */, NULL /* MULTICAST_B224 (# 209) */, NULL /* MULTICAST_B33 (# 210) */, NULL /* MULTICAST_DAIPS (# 211) */, NULL /* MULTICAST_DRP (# 212) */, NULL /* MULTICAST_FMODE (# 213) */, NULL /* MULTICAST_GID15_0 (# 214) */, NULL /* MULTICAST_GID31_16 (# 215) */, NULL /* MULTICAST_HIPI (# 216) */, NULL /* MULTICAST_HISE (# 217) */, NULL /* MULTICAST_HISFL (# 218) */, NULL /* MULTICAST_ICMD (# 219) */, NULL /* MULTICAST_IGMPV3E (# 220) */, NULL /* MULTICAST_INVC (# 221) */, NULL /* MULTICAST_IPMPT (# 222) */, NULL /* MULTICAST_PORT (# 223) */, NULL /* MULTICAST_PPPOEHR (# 224) */, NULL /* MULTICAST_QI (# 225) */, NULL /* MULTICAST_RV (# 226) */, NULL /* MULTICAST_S3PMI (# 227) */, NULL /* MULTICAST_S3PMV (# 228) */, NULL /* MULTICAST_S4BUSY (# 229) */, NULL /* MULTICAST_S4R (# 230) */, NULL /* MULTICAST_SARE (# 231) */, NULL /* MULTICAST_SCPA (# 232) */, NULL /* MULTICAST_SCPP (# 233) */, NULL /* MULTICAST_SCPPE (# 234) */, NULL /* MULTICAST_SCPTCP (# 235) */, NULL /* MULTICAST_SCPTMP (# 236) */, NULL /* MULTICAST_SCPTSP (# 237) */, NULL /* MULTICAST_SCPTTH (# 238) */, NULL /* MULTICAST_SIP15_0 (# 239) */, NULL /* MULTICAST_SIP31_16 (# 240) */, NULL /* MULTICAST_SIP47_32 (# 241) */, NULL /* MULTICAST_SIPGID0 (# 242) */, NULL /* MULTICAST_SIPGID1 (# 243) */, NULL /* MULTICAST_SIPGID2 (# 244) */, NULL /* MULTICAST_TIMERC (# 245) */, NULL /* PAUSE_ADDR15_0 (# 246) */, NULL /* PAUSE_ADDR31_16 (# 247) */, NULL /* PAUSE_ADDR39_32 (# 248) */, NULL /* PAUSE_ADDR47_41 (# 249) */, NULL /* PAUSE_PAC (# 250) */, NULL /* PHY_INIT_PHYIE0 (# 251) */, NULL /* PHY_INIT_PHYIE01 (# 252) */, NULL /* PHY_INIT_PHYIE02 (# 253) */, NULL /* PHY_INIT_PHYIE03 (# 254) */, NULL /* PHY_INIT_PHYIE1 (# 255) */, NULL /* PHY_INIT_PHYIE11 (# 256) */, NULL /* PHY_INIT_PHYIE12 (# 257) */, NULL /* PHY_INIT_PHYIE13 (# 258) */, NULL /* PHY_INIT_PHYIE2 (# 259) */, NULL /* PHY_INIT_PHYIE21 (# 260) */, NULL /* PHY_INIT_PHYIE22 (# 261) */, NULL /* PHY_INIT_PHYIE23 (# 262) */, NULL /* PHY_INIT_PHYIE3 (# 263) */, NULL /* PHY_INIT_PHYIE31 (# 264) */, NULL /* PHY_INIT_PHYIE32 (# 265) */, NULL /* PHY_INIT_PHYIE33 (# 266) */, NULL /* PHY_INIT_PHYIE4 (# 267) */, NULL /* PHY_INIT_PHYIE41 (# 268) */, NULL /* PHY_INIT_PHYIE42 (# 269) */, NULL /* PHY_INIT_PHYIE43 (# 270) */, NULL /* PHY_INIT_PHYIE5 (# 271) */, NULL /* PHY_INIT_PHYIE51 (# 272) */, NULL /* PHY_INIT_PHYIE52 (# 273) */, NULL /* PHY_INIT_PHYIE53 (# 274) */, NULL /* PHY_INIT_PHYIE6 (# 275) */, NULL /* PHY_INIT_PHYIE61 (# 276) */, NULL /* PHY_INIT_PHYIE62 (# 277) */, NULL /* PHY_INIT_PHYIE63 (# 278) */, NULL /* PHY_INIT_REGA (# 279) */, NULL /* PHY_INIT_REGA1 (# 280) */, NULL /* PHY_INIT_REGA2 (# 281) */, NULL /* PHY_INIT_REGA3 (# 282) */, NULL /* PHY_INIT_REGD (# 283) */, NULL /* PHY_INIT_REGD1 (# 284) */, NULL /* PHY_INIT_REGD2 (# 285) */, NULL /* PHY_INIT_REGD3 (# 286) */, "PMAC_HD_CTL.ADD" /* PMAC_ADD (# 287) */, "PMAC_HD_CTL.AC" /* PMAC_ADD_CRC (# 288) */, "PMAC_HD_CTL.AS" /* PMAC_AS (# 289) */, "PMAC_VLAN.CFI" /* PMAC_CFI (# 290) */, "PMAC_DA2.DA_31_0" /* PMAC_DA_31_0 (# 291) */, "PMAC_DA1.DA_47_32" /* PMAC_DA_47_32 (# 292) */, "PMAC_RX_IPG.IDIS_REQ_WM" /* PMAC_IDIS_REQ_WM (# 293) */, "PMAC_RX_IPG.IPG_CNT" /* PMAC_IPG_RX_CNT (# 294) */, "PMAC_TX_IPG.IPG_CNT" /* PMAC_IPG_TX_CNT (# 295) */, "PMAC_RX_IPG.IREQ_WM" /* PMAC_IREQ_WM (# 296) */, "PMAC_VLAN.PRI" /* PMAC_PRI (# 297) */, "PMAC_HD_CTL.RC" /* PMAC_RC (# 298) */, "PMAC_HD_CTL.RL2" /* PMAC_RL2 (# 299) */, "PMAC_HD_CTL.RXSH" /* PMAC_RXSH (# 300) */, "PMAC_SA2.SA_31_0" /* PMAC_SA_31_0 (# 301) */, "PMAC_SA1.SA_47_32" /* PMAC_SA_47_32 (# 302) */, "PMAC_HD_CTL.TAG" /* PMAC_TAG (# 303) */, "PMAC_HD_CTL.TYPE_LEN" /* PMAC_TYPE_LEN (# 304) */, "PMAC_VLAN.VLAN ID" /* PMAC_VLAN ID (# 305) */, "P0_CTL_REG.AD" /* PORT_AD (# 306) */, "P1_CTL_REG.AD" /* PORT_AD1 (# 307) */, "P2_CTL_REG.AD" /* PORT_AD2 (# 308) */, NULL /* PORT_AD3 (# 309) */, NULL /* PORT_AD4 (# 310) */, NULL /* PORT_AD5 (# 311) */, NULL /* PORT_AD6 (# 312) */, "DF_PORTMAP_REG.BP" /* PORT_BP (# 313) */, "P0_CTL_REG.DFWD" /* PORT_DFWD (# 314) */, "P1_CTL_REG.DFWD" /* PORT_DFWD1 (# 315) */, "P2_CTL_REG.DFWD" /* PORT_DFWD2 (# 316) */, "P0_CTL_REG.DSV8021x" /* PORT_DSV821X (# 317) */, "P1_CTL_REG.DSV8021x" /* PORT_DSV821X1 (# 318) */, "P2_CTL_REG.DSV8021x" /* PORT_DSV821X2 (# 319) */, "P0_ECS_Q10_REG.P0SPQ0TR" /* PORT_EGRESS_PSPQ0TR (# 320) */, "P1_ECS_Q10_REG.P0SPQ0TR" /* PORT_EGRESS_PSPQ0TR1 (# 321) */, "P2_ECS_Q10_REG.P0SPQ0TR" /* PORT_EGRESS_PSPQ0TR2 (# 322) */, NULL /* PORT_EGRESS_PSPQ0TR3 (# 323) */, NULL /* PORT_EGRESS_PSPQ0TR4 (# 324) */, NULL /* PORT_EGRESS_PSPQ0TR5 (# 325) */, NULL /* PORT_EGRESS_PSPQ0TR6 (# 326) */, NULL /* PORT_EGRESS_PSPQ1TR (# 327) */, "P0_ECS_Q10_REG.P0SPQ1TR" /* PORT_EGRESS_PSPQ1TR1 (# 328) */, "P2_ECS_Q10_REG.P0SPQ1TR" /* PORT_EGRESS_PSPQ1TR2 (# 329) */, NULL /* PORT_EGRESS_PSPQ1TR3 (# 330) */, NULL /* PORT_EGRESS_PSPQ1TR4 (# 331) */, NULL /* PORT_EGRESS_PSPQ1TR5 (# 332) */, NULL /* PORT_EGRESS_PSPQ1TR6 (# 333) */, "P0_ECS_Q32_REG.P0SPQ2TR" /* PORT_EGRESS_PSPQ2TR (# 334) */, "P1_ECS_Q32_REG.P0SPQ2TR" /* PORT_EGRESS_PSPQ2TR1 (# 335) */, "P2_ECS_Q32_REG.P0SPQ2TR" /* PORT_EGRESS_PSPQ2TR2 (# 336) */, NULL /* PORT_EGRESS_PSPQ2TR3 (# 337) */, NULL /* PORT_EGRESS_PSPQ2TR4 (# 338) */, NULL /* PORT_EGRESS_PSPQ2TR5 (# 339) */, NULL /* PORT_EGRESS_PSPQ2TR6 (# 340) */, "P0_ECS_Q32_REG.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR (# 341) */, "P1_ECS_Q32_REG.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR1 (# 342) */, "P2_ECS_Q32_REG.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR2 (# 343) */, NULL /* PORT_EGRESS_PSPQ3TR3 (# 344) */, NULL /* PORT_EGRESS_PSPQ3TR4 (# 345) */, NULL /* PORT_EGRESS_PSPQ3TR5 (# 346) */, NULL /* PORT_EGRESS_PSPQ3TR6 (# 347) */, "P0_ECW_Q10_REG.P0WQ0TR" /* PORT_EGRESS_PWQ0TR (# 348) */, "P1_ECW_Q10_REG.P1WQ0TR" /* PORT_EGRESS_PWQ0TR1 (# 349) */, "P2_ECW_Q10_REG.P2WQ0TR" /* PORT_EGRESS_PWQ0TR2 (# 350) */, NULL /* PORT_EGRESS_PWQ0TR3 (# 351) */, NULL /* PORT_EGRESS_PWQ0TR4 (# 352) */, NULL /* PORT_EGRESS_PWQ0TR5 (# 353) */, NULL /* PORT_EGRESS_PWQ0TR6 (# 354) */, NULL /* PORT_EGRESS_PWQ1TR (# 355) */, "P0_ECW_Q10_REG.P0WQ1TR" /* PORT_EGRESS_PWQ1TR1 (# 356) */, "P2_ECW_Q10_REG.P2WQ1TR" /* PORT_EGRESS_PWQ1TR2 (# 357) */, NULL /* PORT_EGRESS_PWQ1TR3 (# 358) */, NULL /* PORT_EGRESS_PWQ1TR4 (# 359) */, NULL /* PORT_EGRESS_PWQ1TR5 (# 360) */, NULL /* PORT_EGRESS_PWQ1TR6 (# 361) */, "P0_ECW_Q32_REG.P0WQ2TR" /* PORT_EGRESS_PWQ2TR (# 362) */, "P1_ECW_Q32_REG.P1WQ2TR" /* PORT_EGRESS_PWQ2TR1 (# 363) */, "P2_ECW_Q32_REG.P2WQ2TR" /* PORT_EGRESS_PWQ2TR2 (# 364) */, NULL /* PORT_EGRESS_PWQ2TR3 (# 365) */, NULL /* PORT_EGRESS_PWQ2TR4 (# 366) */, NULL /* PORT_EGRESS_PWQ2TR5 (# 367) */, NULL /* PORT_EGRESS_PWQ2TR6 (# 368) */, "P0_ECW_Q32_REG.P0WQ3TR" /* PORT_EGRESS_PWQ3TR (# 369) */, "P1_ECW_Q32_REG.P1WQ3TR" /* PORT_EGRESS_PWQ3TR1 (# 370) */, "P2_ECW_Q32_REG.P2WQ3TR" /* PORT_EGRESS_PWQ3TR2 (# 371) */, NULL /* PORT_EGRESS_PWQ3TR3 (# 372) */, NULL /* PORT_EGRESS_PWQ3TR4 (# 373) */, NULL /* PORT_EGRESS_PWQ3TR5 (# 374) */, NULL /* PORT_EGRESS_PWQ3TR6 (# 375) */, "TCP_PF0_REG.ATUF0" /* PORT_FILTER_ATUF (# 376) */, "TCP_PF1_REG.ATUF1" /* PORT_FILTER_ATUF1 (# 377) */, "TCP_PF2_REG.ATUF2" /* PORT_FILTER_ATUF2 (# 378) */, "TCP_PF3_REG.ATUF3" /* PORT_FILTER_ATUF3 (# 379) */, "TCP_PF4_REG.ATUF4" /* PORT_FILTER_ATUF4 (# 380) */, "TCP_PF5_REG.ATUF5" /* PORT_FILTER_ATUF5 (# 381) */, "TCP_PF6_REG.ATUF6" /* PORT_FILTER_ATUF6 (# 382) */, "TCP_PF7_REG.ATUF7" /* PORT_FILTER_ATUF7 (# 383) */, "TCP_PF0_REG.BASEPT0" /* PORT_FILTER_BASEPT (# 384) */, "TCP_PF1_REG.BASEPT1" /* PORT_FILTER_BASEPT1 (# 385) */, "TCP_PF2_REG.BASEPT2" /* PORT_FILTER_BASEPT2 (# 386) */, "TCP_PF3_REG.BASEPT3" /* PORT_FILTER_BASEPT3 (# 387) */, "TCP_PF4_REG.BASEPT4" /* PORT_FILTER_BASEPT4 (# 388) */, "TCP_PF5_REG.BASEPT5" /* PORT_FILTER_BASEPT5 (# 389) */, "TCP_PF6_REG.BASEPT6" /* PORT_FILTER_BASEPT6 (# 390) */, "TCP_PF7_REG.BASEPT7" /* PORT_FILTER_BASEPT7 (# 391) */, "TCP_PF0_REG.COMP0" /* PORT_FILTER_COMP (# 392) */, "TCP_PF1_REG.COMP1" /* PORT_FILTER_COMP1 (# 393) */, "TCP_PF2_REG.COMP2" /* PORT_FILTER_COMP2 (# 394) */, "TCP_PF3_REG.COMP3" /* PORT_FILTER_COMP3 (# 395) */, "TCP_PF4_REG.COMP4" /* PORT_FILTER_COMP4 (# 396) */, "TCP_PF5_REG.COMP5" /* PORT_FILTER_COMP5 (# 397) */, "TCP_PF6_REG.COMP6" /* PORT_FILTER_COMP6 (# 398) */, "TCP_PF7_REG.COMP7" /* PORT_FILTER_COMP7 (# 399) */, "TCP_PF0_REG.PRANGE0" /* PORT_FILTER_PRANGE (# 400) */, "TCP_PF1_REG.PRANGE1" /* PORT_FILTER_PRANGE1 (# 401) */, "TCP_PF2_REG.PRANGE2" /* PORT_FILTER_PRANGE2 (# 402) */, "TCP_PF3_REG.PRANGE3" /* PORT_FILTER_PRANGE3 (# 403) */, "TCP_PF4_REG.PRANGE4" /* PORT_FILTER_PRANGE4 (# 404) */, "TCP_PF5_REG.PRANGE5" /* PORT_FILTER_PRANGE5 (# 405) */, "TCP_PF6_REG.PRANGE6" /* PORT_FILTER_PRANGE6 (# 406) */, "TCP_PF7_REG.PRANGE7" /* PORT_FILTER_PRANGE7 (# 407) */, "TCP_PF0_REG.TUPF0" /* PORT_FILTER_TUPF (# 408) */, "TCP_PF1_REG.TUPF1" /* PORT_FILTER_TUPF1 (# 409) */, "TCP_PF2_REG.TUPF2" /* PORT_FILTER_TUPF2 (# 410) */, "TCP_PF3_REG.TUPF3" /* PORT_FILTER_TUPF3 (# 411) */, "TCP_PF4_REG.TUPF4" /* PORT_FILTER_TUPF4 (# 412) */, "TCP_PF5_REG.TUPF5" /* PORT_FILTER_TUPF5 (# 413) */, "TCP_PF6_REG.TUPF6" /* PORT_FILTER_TUPF6 (# 414) */, "TCP_PF7_REG.TUPF7" /* PORT_FILTER_TUPF7 (# 415) */, "P0_CTL_REG.FLD" /* PORT_FLD (# 416) */, "P1_CTL_REG.FLD" /* PORT_FLD1 (# 417) */, "P2_CTL_REG.FLD" /* PORT_FLD2 (# 418) */, NULL /* PORT_FLD3 (# 419) */, NULL /* PORT_FLD4 (# 420) */, NULL /* PORT_FLD5 (# 421) */, NULL /* PORT_FLD6 (# 422) */, "P0_CTL_REG.FLP" /* PORT_FLP (# 423) */, "P1_CTL_REG.FLP" /* PORT_FLP1 (# 424) */, "P2_CTL_REG.FLP" /* PORT_FLP2 (# 425) */, NULL /* PORT_FLP3 (# 426) */, NULL /* PORT_FLP4 (# 427) */, NULL /* PORT_FLP5 (# 428) */, NULL /* PORT_FLP6 (# 429) */, "P0_VLAN_REG.IFNTE" /* PORT_IFNTE (# 430) */, "P1_VLAN_REG.IFNTE" /* PORT_IFNTE1 (# 431) */, "P2_VLAN_REG.IFNTE" /* PORT_IFNTE2 (# 432) */, NULL /* PORT_IFNTE3 (# 433) */, NULL /* PORT_IFNTE4 (# 434) */, NULL /* PORT_IFNTE5 (# 435) */, NULL /* PORT_IFNTE6 (# 436) */, NULL /* PORT_IMTE (# 437) */, NULL /* PORT_IMTE1 (# 438) */, NULL /* PORT_IMTE2 (# 439) */, NULL /* PORT_IMTE3 (# 440) */, NULL /* PORT_IMTE4 (# 441) */, NULL /* PORT_IMTE5 (# 442) */, NULL /* PORT_IMTE6 (# 443) */, "P0_INCTL_REG.P0ITR" /* PORT_INGRESS_PITR (# 444) */, "P1_INCTL_REG.P1ITR" /* PORT_INGRESS_PITR1 (# 445) */, "P2_INCTL_REG.P2ITR" /* PORT_INGRESS_PITR2 (# 446) */, NULL /* PORT_INGRESS_PITR3 (# 447) */, NULL /* PORT_INGRESS_PITR4 (# 448) */, NULL /* PORT_INGRESS_PITR5 (# 449) */, NULL /* PORT_INGRESS_PITR6 (# 450) */, "P0_INCTL_REG.P0ITT" /* PORT_INGRESS_PITT (# 451) */, "P1_INCTL_REG.P1ITT" /* PORT_INGRESS_PITT1 (# 452) */, "P2_INCTL_REG.P2ITT" /* PORT_INGRESS_PITT2 (# 453) */, NULL /* PORT_INGRESS_PITT3 (# 454) */, NULL /* PORT_INGRESS_PITT4 (# 455) */, NULL /* PORT_INGRESS_PITT5 (# 456) */, NULL /* PORT_INGRESS_PITT6 (# 457) */, "P0_CTL_REG.IPMO" /* PORT_IPMO (# 458) */, "P1_CTL_REG.IPMO" /* PORT_IPMO1 (# 459) */, "P2_CTL_REG.IPMO" /* PORT_IPMO2 (# 460) */, NULL /* PORT_IPMO3 (# 461) */, NULL /* PORT_IPMO4 (# 462) */, NULL /* PORT_IPMO5 (# 463) */, NULL /* PORT_IPMO6 (# 464) */, "P0_CTL_REG.IPOVTU" /* PORT_IPOVTU (# 465) */, "P1_CTL_REG.IPOVTU" /* PORT_IPOVTU1 (# 466) */, "P2_CTL_REG.IPOVTU" /* PORT_IPOVTU2 (# 467) */, NULL /* PORT_IPOVTU3 (# 468) */, NULL /* PORT_IPOVTU4 (# 469) */, NULL /* PORT_IPOVTU5 (# 470) */, NULL /* PORT_IPOVTU6 (# 471) */, "P0_CTL_REG.IPVLAN" /* PORT_IPVLAN (# 472) */, "P1_CTL_REG.IPVLAN" /* PORT_IPVLAN1 (# 473) */, "P2_CTL_REG.IPVLAN" /* PORT_IPVLAN2 (# 474) */, NULL /* PORT_IPVLAN3 (# 475) */, NULL /* PORT_IPVLAN4 (# 476) */, NULL /* PORT_IPVLAN5 (# 477) */, NULL /* PORT_IPVLAN6 (# 478) */, "P0_CTL_REG.LD" /* PORT_LD (# 479) */, "P1_CTL_REG.LD" /* PORT_LD1 (# 480) */, "P2_CTL_REG.LD" /* PORT_LD2 (# 481) */, NULL /* PORT_LD3 (# 482) */, NULL /* PORT_LD4 (# 483) */, NULL /* PORT_LD5 (# 484) */, NULL /* PORT_LD6 (# 485) */, "P0_CTL_REG.MNA024" /* PORT_MNA24 (# 486) */, "P1_CTL_REG.MNA024" /* PORT_MNA241 (# 487) */, "P2_CTL_REG.MNA024" /* PORT_MNA242 (# 488) */, NULL /* PORT_MNA243 (# 489) */, NULL /* PORT_MNA244 (# 490) */, NULL /* PORT_MNA245 (# 491) */, NULL /* PORT_MNA246 (# 492) */, "DF_PORTMAP_REG.MP" /* PORT_MP (# 493) */, "P0_CTL_REG.PAS" /* PORT_PAS (# 494) */, "P1_CTL_REG.PAS" /* PORT_PAS1 (# 495) */, "P2_CTL_REG.PAS" /* PORT_PAS2 (# 496) */, NULL /* PORT_PAS3 (# 497) */, NULL /* PORT_PAS4 (# 498) */, NULL /* PORT_PAS5 (# 499) */, NULL /* PORT_PAS6 (# 500) */, "PS_REG.P0DS" /* PORT_PDS (# 501) */, "PS_REG.P1DS" /* PORT_PDS1 (# 502) */, NULL /* PORT_PDS2 (# 503) */, NULL /* PORT_PDS3 (# 504) */, NULL /* PORT_PDS4 (# 505) */, NULL /* PORT_PDS5 (# 506) */, NULL /* PORT_PDS6 (# 507) */, "PS_REG.P0FCS" /* PORT_PFCS (# 508) */, "PS_REG.P1FCS" /* PORT_PFCS1 (# 509) */, NULL /* PORT_PFCS2 (# 510) */, NULL /* PORT_PFCS3 (# 511) */, NULL /* PORT_PFCS4 (# 512) */, NULL /* PORT_PFCS5 (# 513) */, NULL /* PORT_PFCS6 (# 514) */, "PS_REG.P0LS" /* PORT_PLS (# 515) */, "PS_REG.P1LS" /* PORT_PLS1 (# 516) */, NULL /* PORT_PLS2 (# 517) */, NULL /* PORT_PLS3 (# 518) */, NULL /* PORT_PLS4 (# 519) */, NULL /* PORT_PLS5 (# 520) */, NULL /* PORT_PLS6 (# 521) */, "P0_CTL_REG.PM" /* PORT_PM (# 522) */, "P1_CTL_REG.PM" /* PORT_PM1 (# 523) */, "P2_CTL_REG.PM" /* PORT_PM2 (# 524) */, NULL /* PORT_PM3 (# 525) */, NULL /* PORT_PM4 (# 526) */, NULL /* PORT_PM5 (# 527) */, NULL /* PORT_PM6 (# 528) */, "P0_CTL_REG.PPPOEP" /* PORT_PPPOEP (# 529) */, "P1_CTL_REG.PPPOEP" /* PORT_PPPOEP1 (# 530) */, "P2_CTL_REG.PPPOEP" /* PORT_PPPOEP2 (# 531) */, NULL /* PORT_PPPOEP3 (# 532) */, NULL /* PORT_PPPOEP4 (# 533) */, NULL /* PORT_PPPOEP5 (# 534) */, NULL /* PORT_PPPOEP6 (# 535) */, "PS_REG.P0SHS" /* PORT_PSHS (# 536) */, "PS_REG.P1SHS" /* PORT_PSHS1 (# 537) */, NULL /* PORT_PSHS2 (# 538) */, NULL /* PORT_PSHS3 (# 539) */, NULL /* PORT_PSHS4 (# 540) */, NULL /* PORT_PSHS5 (# 541) */, NULL /* PORT_PSHS6 (# 542) */, "PS_REG.P0SS" /* PORT_PSS (# 543) */, "PS_REG.P1SS" /* PORT_PSS1 (# 544) */, NULL /* PORT_PSS2 (# 545) */, NULL /* PORT_PSS3 (# 546) */, NULL /* PORT_PSS4 (# 547) */, NULL /* PORT_PSS5 (# 548) */, NULL /* PORT_PSS6 (# 549) */, "P0_CTL_REG.REDIR" /* PORT_REDIR (# 550) */, "P1_CTL_REG.REDIR" /* PORT_REDIR1 (# 551) */, "P2_CTL_REG.REDIR" /* PORT_REDIR2 (# 552) */, "RGMII_CTL_REG.P0CKIO" /* PORT_RGMII_GMII_P0CKIO (# 553) */, "RGMII_CTL_REG.P0DUP" /* PORT_RGMII_GMII_P0DUP (# 554) */, "RGMII_CTL_REG.P0FCE" /* PORT_RGMII_GMII_P0FCE (# 555) */, "RGMII_CTL_REG.P0Feq" /* PORT_RGMII_GMII_P0FEQ (# 556) */, "RGMII_CTL_REG.P0IS" /* PORT_RGMII_GMII_P0IS (# 557) */, "RGMII_CTL_REG.P0RDLY" /* PORT_RGMII_GMII_P0RDLY (# 558) */, "RGMII_CTL_REG.P0SPD" /* PORT_RGMII_GMII_P0SPD (# 559) */, "RGMII_CTL_REG.P0TDLY" /* PORT_RGMII_GMII_P0TDLY (# 560) */, "RGMII_CTL_REG.P1CKIO" /* PORT_RGMII_GMII_P1CKIO (# 561) */, "RGMII_CTL_REG.P1DUP" /* PORT_RGMII_GMII_P1DUP (# 562) */, "RGMII_CTL_REG.P1FCE" /* PORT_RGMII_GMII_P1FCE (# 563) */, "RGMII_CTL_REG.P1Feq" /* PORT_RGMII_GMII_P1FEQ (# 564) */, "RGMII_CTL_REG.P1IS" /* PORT_RGMII_GMII_P1IS (# 565) */, "RGMII_CTL_REG.P1RDLY" /* PORT_RGMII_GMII_P1RDLY (# 566) */, "RGMII_CTL_REG.P1SPD" /* PORT_RGMII_GMII_P1SPD (# 567) */, "RGMII_CTL_REG.P1TDLY" /* PORT_RGMII_GMII_P1TDLY (# 568) */, NULL /* PORT_RGMII_GMII_P4DUP (# 569) */, NULL /* PORT_RGMII_GMII_P4FCE (# 570) */, NULL /* PORT_RGMII_GMII_P4SPD (# 571) */, NULL /* PORT_RGMII_GMII_P5DUP (# 572) */, NULL /* PORT_RGMII_GMII_P5FCE (# 573) */, NULL /* PORT_RGMII_GMII_P5SPD (# 574) */, NULL /* PORT_RGMII_GMII_P6DUP (# 575) */, NULL /* PORT_RGMII_GMII_P6FCE (# 576) */, NULL /* PORT_RGMII_GMII_P6SPD (# 577) */, "P0_CTL_REG.RMWFQ" /* PORT_RMWFQ (# 578) */, "P1_CTL_REG.RMWFQ" /* PORT_RMWFQ1 (# 579) */, "P2_CTL_REG.RMWFQ" /* PORT_RMWFQ2 (# 580) */, NULL /* PORT_RMWFQ3 (# 581) */, NULL /* PORT_RMWFQ4 (# 582) */, NULL /* PORT_RMWFQ5 (# 583) */, NULL /* PORT_RMWFQ6 (# 584) */, "DF_PORTMAP_REG.RP" /* PORT_RP (# 585) */, "P0_CTL_REG.SPE" /* PORT_SPE (# 586) */, "P1_CTL_REG.SPE" /* PORT_SPE1 (# 587) */, "P2_CTL_REG.SPE" /* PORT_SPE2 (# 588) */, NULL /* PORT_SPE3 (# 589) */, NULL /* PORT_SPE4 (# 590) */, NULL /* PORT_SPE5 (# 591) */, NULL /* PORT_SPE6 (# 592) */, "P0_CTL_REG.SPS" /* PORT_SPS (# 593) */, "P1_CTL_REG.SPS" /* PORT_SPS1 (# 594) */, "P2_CTL_REG.SPS" /* PORT_SPS2 (# 595) */, NULL /* PORT_SPS3 (# 596) */, NULL /* PORT_SPS4 (# 597) */, NULL /* PORT_SPS5 (# 598) */, NULL /* PORT_SPS6 (# 599) */, "P0_CTL_REG.TCPE" /* PORT_TCPE (# 600) */, "P1_CTL_REG.TCPE" /* PORT_TCPE1 (# 601) */, "P2_CTL_REG.TCPE" /* PORT_TCPE2 (# 602) */, NULL /* PORT_TCPE3 (# 603) */, NULL /* PORT_TCPE4 (# 604) */, NULL /* PORT_TCPE5 (# 605) */, NULL /* PORT_TCPE6 (# 606) */, "P0_CTL_REG.TPE" /* PORT_TPE (# 607) */, "P1_CTL_REG.TPE" /* PORT_TPE1 (# 608) */, "P2_CTL_REG.TPE" /* PORT_TPE2 (# 609) */, NULL /* PORT_TPE3 (# 610) */, NULL /* PORT_TPE4 (# 611) */, NULL /* PORT_TPE5 (# 612) */, NULL /* PORT_TPE6 (# 613) */, "DF_PORTMAP_REG.UP" /* PORT_UP (# 614) */, "P0_VLAN_REG.AOVTP" /* PORT_VLAN_AOVTP (# 615) */, "P1_VLAN_REG.AOVTP" /* PORT_VLAN_AOVTP1 (# 616) */, "P2_VLAN_REG.AOVTP" /* PORT_VLAN_AOVTP2 (# 617) */, NULL /* PORT_VLAN_AOVTP3 (# 618) */, NULL /* PORT_VLAN_AOVTP4 (# 619) */, NULL /* PORT_VLAN_AOVTP5 (# 620) */, NULL /* PORT_VLAN_AOVTP6 (# 621) */, "P0_CTL_REG.BYPASS" /* PORT_VLAN_BYPASS (# 622) */, "P1_CTL_REG.BYPASS" /* PORT_VLAN_BYPASS1 (# 623) */, "P2_CTL_REG.BYPASS" /* PORT_VLAN_BYPASS2 (# 624) */, NULL /* PORT_VLAN_BYPASS3 (# 625) */, NULL /* PORT_VLAN_BYPASS4 (# 626) */, NULL /* PORT_VLAN_BYPASS5 (# 627) */, NULL /* PORT_VLAN_BYPASS6 (# 628) */, "P0_VLAN_REG.DFID" /* PORT_VLAN_DFID (# 629) */, "P1_VLAN_REG.DFID" /* PORT_VLAN_DFID1 (# 630) */, "P2_VLAN_REG.DFID" /* PORT_VLAN_DFID2 (# 631) */, NULL /* PORT_VLAN_DFID3 (# 632) */, NULL /* PORT_VLAN_DFID4 (# 633) */, NULL /* PORT_VLAN_DFID5 (# 634) */, NULL /* PORT_VLAN_DFID6 (# 635) */, "P0_VLAN_REG.DVPM" /* PORT_VLAN_DVPM (# 636) */, "P1_VLAN_REG.DVPM" /* PORT_VLAN_DVPM1 (# 637) */, "P2_VLAN_REG.DVPM" /* PORT_VLAN_DVPM2 (# 638) */, NULL /* PORT_VLAN_DVPM3 (# 639) */, NULL /* PORT_VLAN_DVPM4 (# 640) */, NULL /* PORT_VLAN_DVPM5 (# 641) */, NULL /* PORT_VLAN_DVPM6 (# 642) */, "P0_VLAN_REG.PP" /* PORT_VLAN_PP (# 643) */, "P1_VLAN_REG.PP" /* PORT_VLAN_PP1 (# 644) */, "P2_VLAN_REG.PP" /* PORT_VLAN_PP2 (# 645) */, NULL /* PORT_VLAN_PP3 (# 646) */, NULL /* PORT_VLAN_PP4 (# 647) */, NULL /* PORT_VLAN_PP5 (# 648) */, NULL /* PORT_VLAN_PP6 (# 649) */, "P0_VLAN_REG.PPE" /* PORT_VLAN_PPE (# 650) */, "P1_VLAN_REG.PPE" /* PORT_VLAN_PPE1 (# 651) */, "P2_VLAN_REG.PPE" /* PORT_VLAN_PPE2 (# 652) */, NULL /* PORT_VLAN_PPE3 (# 653) */, NULL /* PORT_VLAN_PPE4 (# 654) */, NULL /* PORT_VLAN_PPE5 (# 655) */, NULL /* PORT_VLAN_PPE6 (# 656) */, "P0_VLAN_REG.PVID" /* PORT_VLAN_PVID (# 657) */, "P1_VLAN_REG.PVID" /* PORT_VLAN_PVID1 (# 658) */, "P2_VLAN_REG.PVID" /* PORT_VLAN_PVID2 (# 659) */, NULL /* PORT_VLAN_PVID3 (# 660) */, NULL /* PORT_VLAN_PVID4 (# 661) */, NULL /* PORT_VLAN_PVID5 (# 662) */, NULL /* PORT_VLAN_PVID6 (# 663) */, "P0_VLAN_REG.PVTAGMP" /* PORT_VLAN_PVTAGMP (# 664) */, "P1_VLAN_REG.PVTAGMP" /* PORT_VLAN_PVTAGMP1 (# 665) */, "P2_VLAN_REG.PVTAGMP" /* PORT_VLAN_PVTAGMP2 (# 666) */, NULL /* PORT_VLAN_PVTAGMP3 (# 667) */, NULL /* PORT_VLAN_PVTAGMP4 (# 668) */, NULL /* PORT_VLAN_PVTAGMP5 (# 669) */, NULL /* PORT_VLAN_PVTAGMP6 (# 670) */, "P0_VLAN_REG.TBVE" /* PORT_VLAN_TBVE (# 671) */, "P1_VLAN_REG.TBVE" /* PORT_VLAN_TBVE1 (# 672) */, "P2_VLAN_REG.TBVE" /* PORT_VLAN_TBVE2 (# 673) */, NULL /* PORT_VLAN_TBVE3 (# 674) */, NULL /* PORT_VLAN_TBVE4 (# 675) */, NULL /* PORT_VLAN_TBVE5 (# 676) */, NULL /* PORT_VLAN_TBVE6 (# 677) */, "P0_VLAN_REG.VC" /* PORT_VLAN_VC (# 678) */, "P1_VLAN_REG.VC" /* PORT_VLAN_VC1 (# 679) */, "P2_VLAN_REG.VC" /* PORT_VLAN_VC2 (# 680) */, NULL /* PORT_VLAN_VC3 (# 681) */, NULL /* PORT_VLAN_VC4 (# 682) */, NULL /* PORT_VLAN_VC5 (# 683) */, NULL /* PORT_VLAN_VC6 (# 684) */, "P0_VLAN_REG.VMCE" /* PORT_VLAN_VMCE (# 685) */, "P1_VLAN_REG.VMCE" /* PORT_VLAN_VMCE1 (# 686) */, "P2_VLAN_REG.VMCE" /* PORT_VLAN_VMCE2 (# 687) */, NULL /* PORT_VLAN_VMCE3 (# 688) */, NULL /* PORT_VLAN_VMCE4 (# 689) */, NULL /* PORT_VLAN_VMCE5 (# 690) */, NULL /* PORT_VLAN_VMCE6 (# 691) */, "P0_VLAN_REG.VSD" /* PORT_VLAN_VSD (# 692) */, "P1_VLAN_REG.VSD" /* PORT_VLAN_VSD1 (# 693) */, "P2_VLAN_REG.VSD" /* PORT_VLAN_VSD2 (# 694) */, NULL /* PORT_VLAN_VSD3 (# 695) */, NULL /* PORT_VLAN_VSD4 (# 696) */, NULL /* PORT_VLAN_VSD5 (# 697) */, NULL /* PORT_VLAN_VSD6 (# 698) */, "P0_CTL_REG.VPE" /* PORT_VPE (# 699) */, "P1_CTL_REG.VPE" /* PORT_VPE1 (# 700) */, "P2_CTL_REG.VPE" /* PORT_VPE2 (# 701) */, NULL /* PORT_VPE3 (# 702) */, NULL /* PORT_VPE4 (# 703) */, NULL /* PORT_VPE5 (# 704) */, NULL /* PORT_VPE6 (# 705) */, NULL /* PPPOE_SID (# 706) */, "PRTCL_FLT_ACT_REG.APF0" /* PROTOCOL_FILTER_APF (# 707) */, "PRTCL_FLT_ACT_REG.APF1" /* PROTOCOL_FILTER_APF1 (# 708) */, "PRTCL_FLT_ACT_REG.APF2" /* PROTOCOL_FILTER_APF2 (# 709) */, "PRTCL_FLT_ACT_REG.APF3" /* PROTOCOL_FILTER_APF3 (# 710) */, "PRTCL_FLT_ACT_REG.APF4" /* PROTOCOL_FILTER_APF4 (# 711) */, "PRTCL_FLT_ACT_REG.APF5" /* PROTOCOL_FILTER_APF5 (# 712) */, "PRTCL_FLT_ACT_REG.APF6" /* PROTOCOL_FILTER_APF6 (# 713) */, "PRTCL_FLT_ACT_REG.APF7" /* PROTOCOL_FILTER_APF7 (# 714) */, "PRTCL_F0_REG.PFR0" /* PROTOCOL_FILTER_PFR0 (# 715) */, "PRTCL_F1_REG.PFR0" /* PROTOCOL_FILTER_PFR01 (# 716) */, NULL /* PROTOCOL_FILTER_PFR02 (# 717) */, NULL /* PROTOCOL_FILTER_PFR03 (# 718) */, "PRTCL_F0_REG.PFR1" /* PROTOCOL_FILTER_PFR1 (# 719) */, "PRTCL_F1_REG.PFR1" /* PROTOCOL_FILTER_PFR11 (# 720) */, NULL /* PROTOCOL_FILTER_PFR12 (# 721) */, NULL /* PROTOCOL_FILTER_PFR13 (# 722) */, "PRTCL_F0_REG.PFR2" /* PROTOCOL_FILTER_PFR2 (# 723) */, "PRTCL_F1_REG.PFR2" /* PROTOCOL_FILTER_PFR21 (# 724) */, "PRTCL_F0_REG.PFR3" /* PROTOCOL_FILTER_PFR3 (# 725) */, "PRTCL_F1_REG.PFR3" /* PROTOCOL_FILTER_PFR31 (# 726) */, "RA_03_00_REG.RA00_ACT" /* RA00_ACT (# 727) */, "RA_07_04_REG.RA10_ACT" /* RA00_ACT1 (# 728) */, "RA_0B_08_REG.RA20_ACT" /* RA00_ACT2 (# 729) */, "RA_0F_0C_REG.RA30_ACT" /* RA00_ACT3 (# 730) */, "RA_13_10_REG.RA40_ACT" /* RA00_ACT4 (# 731) */, "RA_17_14_REG.RA50_ACT" /* RA00_ACT5 (# 732) */, "RA_1B_18_REG.RA60_ACT" /* RA00_ACT6 (# 733) */, "RA_1F_1C_REG.RA70_ACT" /* RA00_ACT7 (# 734) */, "RA_23_20_REG.RA80_ACT" /* RA00_ACT8 (# 735) */, "RA_27_24_REG.RA90_ACT" /* RA00_ACT9 (# 736) */, "RA_2B_28_REG.RA100_ACT" /* RA00_ACT10 (# 737) */, "RA_2F_2C_REG.RA110_ACT" /* RA00_ACT11 (# 738) */, NULL /* RA00_ACT12 (# 739) */, NULL /* RA00_ACT13 (# 740) */, NULL /* RA00_ACT14 (# 741) */, NULL /* RA00_ACT15 (# 742) */, NULL /* RA00_ACT16 (# 743) */, NULL /* RA00_ACT17 (# 744) */, NULL /* RA00_ACT18 (# 745) */, NULL /* RA00_ACT19 (# 746) */, NULL /* RA00_ACT20 (# 747) */, NULL /* RA00_ACT21 (# 748) */, NULL /* RA00_ACT22 (# 749) */, NULL /* RA00_ACT23 (# 750) */, "RA_03_00_REG.RA00_CV" /* RA00_CV (# 751) */, "RA_07_04_REG.RA10_CV" /* RA00_CV1 (# 752) */, "RA_0B_08_REG.RA20_CV" /* RA00_CV2 (# 753) */, "RA_0F_0C_REG.RA30_CV" /* RA00_CV3 (# 754) */, "RA_13_10_REG.RA40_CV" /* RA00_CV4 (# 755) */, "RA_17_14_REG.RA50_CV" /* RA00_CV5 (# 756) */, "RA_1B_18_REG.RA60_CV" /* RA00_CV6 (# 757) */, "RA_1F_1C_REG.RA70_CV" /* RA00_CV7 (# 758) */, "RA_23_20_REG.RA80_CV" /* RA00_CV8 (# 759) */, "RA_27_24_REG.RA90_CV" /* RA00_CV9 (# 760) */, "RA_2B_28_REG.RA100_CV" /* RA00_CV10 (# 761) */, "RA_2F_2C_REG.RA110_CV" /* RA00_CV11 (# 762) */, NULL /* RA00_CV12 (# 763) */, NULL /* RA00_CV13 (# 764) */, NULL /* RA00_CV14 (# 765) */, NULL /* RA00_CV15 (# 766) */, NULL /* RA00_CV16 (# 767) */, NULL /* RA00_CV17 (# 768) */, NULL /* RA00_CV18 (# 769) */, NULL /* RA00_CV19 (# 770) */, NULL /* RA00_CV20 (# 771) */, NULL /* RA00_CV21 (# 772) */, NULL /* RA00_CV22 (# 773) */, NULL /* RA00_CV23 (# 774) */, "RA_03_00_REG.RA00_MG" /* RA00_MG (# 775) */, "RA_07_04_REG.RA10_MG" /* RA00_MG1 (# 776) */, "RA_0B_08_REG.RA20_MG" /* RA00_MG2 (# 777) */, "RA_0F_0C_REG.RA30_MG" /* RA00_MG3 (# 778) */, "RA_13_10_REG.RA40_MG" /* RA00_MG4 (# 779) */, "RA_17_14_REG.RA50_MG" /* RA00_MG5 (# 780) */, "RA_1B_18_REG.RA60_MG" /* RA00_MG6 (# 781) */, "RA_1F_1C_REG.RA70_MG" /* RA00_MG7 (# 782) */, "RA_23_20_REG.RA80_MG" /* RA00_MG8 (# 783) */, "RA_27_24_REG.RA90_MG" /* RA00_MG9 (# 784) */, "RA_2B_28_REG.RA100_MG" /* RA00_MG10 (# 785) */, "RA_2F_2C_REG.RA110_MG" /* RA00_MG11 (# 786) */, NULL /* RA00_MG12 (# 787) */, NULL /* RA00_MG13 (# 788) */, NULL /* RA00_MG14 (# 789) */, NULL /* RA00_MG15 (# 790) */, NULL /* RA00_MG16 (# 791) */, NULL /* RA00_MG17 (# 792) */, NULL /* RA00_MG18 (# 793) */, NULL /* RA00_MG19 (# 794) */, NULL /* RA00_MG20 (# 795) */, NULL /* RA00_MG21 (# 796) */, NULL /* RA00_MG22 (# 797) */, NULL /* RA00_MG23 (# 798) */, "RA_03_00_REG.RA00_SPAN" /* RA00_SPAN (# 799) */, "RA_07_04_REG.RA10_SPAN" /* RA00_SPAN1 (# 800) */, "RA_0B_08_REG.RA20_SPAN" /* RA00_SPAN2 (# 801) */, "RA_0F_0C_REG.RA30_SPAN" /* RA00_SPAN3 (# 802) */, "RA_13_10_REG.RA40_SPAN" /* RA00_SPAN4 (# 803) */, "RA_17_14_REG.RA50_SPAN" /* RA00_SPAN5 (# 804) */, "RA_1B_18_REG.RA60_SPAN" /* RA00_SPAN6 (# 805) */, "RA_1F_1C_REG.RA70_SPAN" /* RA00_SPAN7 (# 806) */, "RA_23_20_REG.RA80_SPAN" /* RA00_SPAN8 (# 807) */, "RA_27_24_REG.RA90_SPAN" /* RA00_SPAN9 (# 808) */, "RA_2B_28_REG.RA100_SPAN" /* RA00_SPAN10 (# 809) */, "RA_2F_2C_REG.RA110_SPAN" /* RA00_SPAN11 (# 810) */, NULL /* RA00_SPAN12 (# 811) */, NULL /* RA00_SPAN13 (# 812) */, NULL /* RA00_SPAN14 (# 813) */, NULL /* RA00_SPAN15 (# 814) */, NULL /* RA00_SPAN16 (# 815) */, NULL /* RA00_SPAN17 (# 816) */, NULL /* RA00_SPAN18 (# 817) */, NULL /* RA00_SPAN19 (# 818) */, NULL /* RA00_SPAN20 (# 819) */, NULL /* RA00_SPAN21 (# 820) */, NULL /* RA00_SPAN22 (# 821) */, NULL /* RA00_SPAN23 (# 822) */, "RA_03_00_REG.RA00_TXTAG" /* RA00_TXTAG (# 823) */, "RA_07_04_REG.RA10_TXTAG" /* RA00_TXTAG1 (# 824) */, "RA_0B_08_REG.RA20_TXTAG" /* RA00_TXTAG2 (# 825) */, "RA_0F_0C_REG.RA30_TXTAG" /* RA00_TXTAG3 (# 826) */, "RA_13_10_REG.RA40_TXTAG" /* RA00_TXTAG4 (# 827) */, "RA_17_14_REG.RA50_TXTAG" /* RA00_TXTAG5 (# 828) */, "RA_1B_18_REG.RA60_TXTAG" /* RA00_TXTAG6 (# 829) */, "RA_1F_1C_REG.RA70_TXTAG" /* RA00_TXTAG7 (# 830) */, "RA_23_20_REG.RA80_TXTAG" /* RA00_TXTAG8 (# 831) */, "RA_27_24_REG.RA90_TXTAG" /* RA00_TXTAG9 (# 832) */, "RA_2B_28_REG.RA100_TXTAG" /* RA00_TXTAG10 (# 833) */, "RA_2F_2C_REG.RA110_TXTAG" /* RA00_TXTAG11 (# 834) */, NULL /* RA00_TXTAG12 (# 835) */, NULL /* RA00_TXTAG13 (# 836) */, NULL /* RA00_TXTAG14 (# 837) */, NULL /* RA00_TXTAG15 (# 838) */, NULL /* RA00_TXTAG16 (# 839) */, NULL /* RA00_TXTAG17 (# 840) */, NULL /* RA00_TXTAG18 (# 841) */, NULL /* RA00_TXTAG19 (# 842) */, NULL /* RA00_TXTAG20 (# 843) */, NULL /* RA00_TXTAG21 (# 844) */, NULL /* RA00_TXTAG22 (# 845) */, NULL /* RA00_TXTAG23 (# 846) */, "RA_03_00_REG.RA00_VALID" /* RA00_VALID (# 847) */, "RA_07_04_REG.RA10_VALID" /* RA00_VALID1 (# 848) */, "RA_0B_08_REG.RA20_VALID" /* RA00_VALID2 (# 849) */, "RA_0F_0C_REG.RA30_VALID" /* RA00_VALID3 (# 850) */, "RA_13_10_REG.RA40_VALID" /* RA00_VALID4 (# 851) */, "RA_17_14_REG.RA50_VALID" /* RA00_VALID5 (# 852) */, "RA_1B_18_REG.RA60_VALID" /* RA00_VALID6 (# 853) */, "RA_1F_1C_REG.RA70_VALID" /* RA00_VALID7 (# 854) */, "RA_23_20_REG.RA80_VALID" /* RA00_VALID8 (# 855) */, "RA_27_24_REG.RA90_VALID" /* RA00_VALID9 (# 856) */, "RA_2B_28_REG.RA100_VALID" /* RA00_VALID10 (# 857) */, "RA_2F_2C_REG.RA110_VALID" /* RA00_VALID11 (# 858) */, NULL /* RA00_VALID12 (# 859) */, NULL /* RA00_VALID13 (# 860) */, NULL /* RA00_VALID14 (# 861) */, NULL /* RA00_VALID15 (# 862) */, NULL /* RA00_VALID16 (# 863) */, NULL /* RA00_VALID17 (# 864) */, NULL /* RA00_VALID18 (# 865) */, NULL /* RA00_VALID19 (# 866) */, NULL /* RA00_VALID20 (# 867) */, NULL /* RA00_VALID21 (# 868) */, NULL /* RA00_VALID22 (# 869) */, NULL /* RA00_VALID23 (# 870) */, "RA_03_00_REG.RA01_ACT" /* RA01_ACT (# 871) */, "RA_07_04_REG.RA11_ACT" /* RA01_ACT1 (# 872) */, "RA_0B_08_REG.RA21_ACT" /* RA01_ACT2 (# 873) */, "RA_0F_0C_REG.RA31_ACT" /* RA01_ACT3 (# 874) */, "RA_13_10_REG.RA41_ACT" /* RA01_ACT4 (# 875) */, "RA_17_14_REG.RA51_ACT" /* RA01_ACT5 (# 876) */, "RA_1B_18_REG.RA61_ACT" /* RA01_ACT6 (# 877) */, "RA_1F_1C_REG.RA71_ACT" /* RA01_ACT7 (# 878) */, "RA_23_20_REG.RA81_ACT" /* RA01_ACT8 (# 879) */, "RA_27_24_REG.RA91_ACT" /* RA01_ACT9 (# 880) */, "RA_2B_28_REG.RA101_ACT" /* RA01_ACT10 (# 881) */, "RA_2F_2C_REG.RA111_ACT" /* RA01_ACT11 (# 882) */, NULL /* RA01_ACT12 (# 883) */, NULL /* RA01_ACT13 (# 884) */, NULL /* RA01_ACT14 (# 885) */, NULL /* RA01_ACT15 (# 886) */, NULL /* RA01_ACT16 (# 887) */, NULL /* RA01_ACT17 (# 888) */, NULL /* RA01_ACT18 (# 889) */, NULL /* RA01_ACT19 (# 890) */, NULL /* RA01_ACT20 (# 891) */, NULL /* RA01_ACT21 (# 892) */, NULL /* RA01_ACT22 (# 893) */, NULL /* RA01_ACT23 (# 894) */, "RA_03_00_REG.RA01_CV" /* RA01_CV (# 895) */, "RA_07_04_REG.RA11_CV" /* RA01_CV1 (# 896) */, "RA_0B_08_REG.RA21_CV" /* RA01_CV2 (# 897) */, "RA_0F_0C_REG.RA31_CV" /* RA01_CV3 (# 898) */, "RA_13_10_REG.RA41_CV" /* RA01_CV4 (# 899) */, "RA_17_14_REG.RA51_CV" /* RA01_CV5 (# 900) */, "RA_1B_18_REG.RA61_CV" /* RA01_CV6 (# 901) */, "RA_1F_1C_REG.RA71_CV" /* RA01_CV7 (# 902) */, "RA_23_20_REG.RA81_CV" /* RA01_CV8 (# 903) */, "RA_27_24_REG.RA91_CV" /* RA01_CV9 (# 904) */, "RA_2B_28_REG.RA101_CV" /* RA01_CV10 (# 905) */, "RA_2F_2C_REG.RA111_CV" /* RA01_CV11 (# 906) */, NULL /* RA01_CV12 (# 907) */, NULL /* RA01_CV13 (# 908) */, NULL /* RA01_CV14 (# 909) */, NULL /* RA01_CV15 (# 910) */, NULL /* RA01_CV16 (# 911) */, NULL /* RA01_CV17 (# 912) */, NULL /* RA01_CV18 (# 913) */, NULL /* RA01_CV19 (# 914) */, NULL /* RA01_CV20 (# 915) */, NULL /* RA01_CV21 (# 916) */, NULL /* RA01_CV22 (# 917) */, NULL /* RA01_CV23 (# 918) */, "RA_03_00_REG.RA01_MG" /* RA01_MG (# 919) */, "RA_07_04_REG.RA11_MG" /* RA01_MG1 (# 920) */, "RA_0B_08_REG.RA21_MG" /* RA01_MG2 (# 921) */, "RA_0F_0C_REG.RA31_MG" /* RA01_MG3 (# 922) */, "RA_13_10_REG.RA41_MG" /* RA01_MG4 (# 923) */, "RA_17_14_REG.RA51_MG" /* RA01_MG5 (# 924) */, "RA_1B_18_REG.RA61_MG" /* RA01_MG6 (# 925) */, "RA_1F_1C_REG.RA71_MG" /* RA01_MG7 (# 926) */, "RA_23_20_REG.RA81_MG" /* RA01_MG8 (# 927) */, "RA_27_24_REG.RA91_MG" /* RA01_MG9 (# 928) */, "RA_2B_28_REG.RA101_MG" /* RA01_MG10 (# 929) */, "RA_2F_2C_REG.RA111_MG" /* RA01_MG11 (# 930) */, NULL /* RA01_MG12 (# 931) */, NULL /* RA01_MG13 (# 932) */, NULL /* RA01_MG14 (# 933) */, NULL /* RA01_MG15 (# 934) */, NULL /* RA01_MG16 (# 935) */, NULL /* RA01_MG17 (# 936) */, NULL /* RA01_MG18 (# 937) */, NULL /* RA01_MG19 (# 938) */, NULL /* RA01_MG20 (# 939) */, NULL /* RA01_MG21 (# 940) */, NULL /* RA01_MG22 (# 941) */, NULL /* RA01_MG23 (# 942) */, "RA_03_00_REG.RA01_SPAN" /* RA01_SPAN (# 943) */, "RA_07_04_REG.RA11_SPAN" /* RA01_SPAN1 (# 944) */, "RA_0B_08_REG.RA21_SPAN" /* RA01_SPAN2 (# 945) */, "RA_0F_0C_REG.RA31_SPAN" /* RA01_SPAN3 (# 946) */, "RA_13_10_REG.RA41_SPAN" /* RA01_SPAN4 (# 947) */, "RA_17_14_REG.RA51_SPAN" /* RA01_SPAN5 (# 948) */, "RA_1B_18_REG.RA61_SPAN" /* RA01_SPAN6 (# 949) */, "RA_1F_1C_REG.RA71_SPAN" /* RA01_SPAN7 (# 950) */, "RA_23_20_REG.RA81_SPAN" /* RA01_SPAN8 (# 951) */, "RA_27_24_REG.RA91_SPAN" /* RA01_SPAN9 (# 952) */, "RA_2B_28_REG.RA101_SPAN" /* RA01_SPAN10 (# 953) */, "RA_2F_2C_REG.RA111_SPAN" /* RA01_SPAN11 (# 954) */, NULL /* RA01_SPAN12 (# 955) */, NULL /* RA01_SPAN13 (# 956) */, NULL /* RA01_SPAN14 (# 957) */, NULL /* RA01_SPAN15 (# 958) */, NULL /* RA01_SPAN16 (# 959) */, NULL /* RA01_SPAN17 (# 960) */, NULL /* RA01_SPAN18 (# 961) */, NULL /* RA01_SPAN19 (# 962) */, NULL /* RA01_SPAN20 (# 963) */, NULL /* RA01_SPAN21 (# 964) */, NULL /* RA01_SPAN22 (# 965) */, NULL /* RA01_SPAN23 (# 966) */, "RA_03_00_REG.RA01_TXTAG" /* RA01_TXTAG (# 967) */, "RA_07_04_REG.RA11_TXTAG" /* RA01_TXTAG1 (# 968) */, "RA_0B_08_REG.RA21_TXTAG" /* RA01_TXTAG2 (# 969) */, "RA_0F_0C_REG.RA31_TXTAG" /* RA01_TXTAG3 (# 970) */, "RA_13_10_REG.RA41_TXTAG" /* RA01_TXTAG4 (# 971) */, "RA_17_14_REG.RA51_TXTAG" /* RA01_TXTAG5 (# 972) */, "RA_1B_18_REG.RA61_TXTAG" /* RA01_TXTAG6 (# 973) */, "RA_1F_1C_REG.RA71_TXTAG" /* RA01_TXTAG7 (# 974) */, "RA_23_20_REG.RA81_TXTAG" /* RA01_TXTAG8 (# 975) */, "RA_27_24_REG.RA91_TXTAG" /* RA01_TXTAG9 (# 976) */, "RA_2B_28_REG.RA101_TXTAG" /* RA01_TXTAG10 (# 977) */, "RA_2F_2C_REG.RA111_TXTAG" /* RA01_TXTAG11 (# 978) */, NULL /* RA01_TXTAG12 (# 979) */, NULL /* RA01_TXTAG13 (# 980) */, NULL /* RA01_TXTAG14 (# 981) */, NULL /* RA01_TXTAG15 (# 982) */, NULL /* RA01_TXTAG16 (# 983) */, NULL /* RA01_TXTAG17 (# 984) */, NULL /* RA01_TXTAG18 (# 985) */, NULL /* RA01_TXTAG19 (# 986) */, NULL /* RA01_TXTAG20 (# 987) */, NULL /* RA01_TXTAG21 (# 988) */, NULL /* RA01_TXTAG22 (# 989) */, NULL /* RA01_TXTAG23 (# 990) */, "RA_03_00_REG.RA01_VALID" /* RA01_VALID (# 991) */, "RA_07_04_REG.RA11_VALID" /* RA01_VALID1 (# 992) */, "RA_0B_08_REG.RA21_VALID" /* RA01_VALID2 (# 993) */, "RA_0F_0C_REG.RA31_VALID" /* RA01_VALID3 (# 994) */, "RA_13_10_REG.RA41_VALID" /* RA01_VALID4 (# 995) */, "RA_17_14_REG.RA51_VALID" /* RA01_VALID5 (# 996) */, "RA_1B_18_REG.RA61_VALID" /* RA01_VALID6 (# 997) */, "RA_1F_1C_REG.RA71_VALID" /* RA01_VALID7 (# 998) */, "RA_23_20_REG.RA81_VALID" /* RA01_VALID8 (# 999) */, "RA_27_24_REG.RA91_VALID" /* RA01_VALID9 (# 1000) */, "RA_2B_28_REG.RA101_VALID" /* RA01_VALID10 (# 1001) */, "RA_2F_2C_REG.RA111_VALID" /* RA01_VALID11 (# 1002) */, NULL /* RA01_VALID12 (# 1003) */, NULL /* RA01_VALID13 (# 1004) */, NULL /* RA01_VALID14 (# 1005) */, NULL /* RA01_VALID15 (# 1006) */, NULL /* RA01_VALID16 (# 1007) */, NULL /* RA01_VALID17 (# 1008) */, NULL /* RA01_VALID18 (# 1009) */, NULL /* RA01_VALID19 (# 1010) */, NULL /* RA01_VALID20 (# 1011) */, NULL /* RA01_VALID21 (# 1012) */, NULL /* RA01_VALID22 (# 1013) */, NULL /* RA01_VALID23 (# 1014) */, "RA_03_00_REG.RA02_ACT" /* RA02_ACT (# 1015) */, "RA_07_04_REG.RA12_ACT" /* RA02_ACT1 (# 1016) */, "RA_0B_08_REG.RA22_ACT" /* RA02_ACT2 (# 1017) */, "RA_0F_0C_REG.RA32_ACT" /* RA02_ACT3 (# 1018) */, "RA_13_10_REG.RA42_ACT" /* RA02_ACT4 (# 1019) */, "RA_17_14_REG.RA52_ACT" /* RA02_ACT5 (# 1020) */, "RA_1B_18_REG.RA62_ACT" /* RA02_ACT6 (# 1021) */, "RA_1F_1C_REG.RA72_ACT" /* RA02_ACT7 (# 1022) */, "RA_23_20_REG.RA82_ACT" /* RA02_ACT8 (# 1023) */, "RA_27_24_REG.RA92_ACT" /* RA02_ACT9 (# 1024) */, "RA_2B_28_REG.RA102_ACT" /* RA02_ACT10 (# 1025) */, "RA_2F_2C_REG.RA112_ACT" /* RA02_ACT11 (# 1026) */, "RA_03_00_REG.RA02_CV" /* RA02_CV (# 1027) */, "RA_07_04_REG.RA12_CV" /* RA02_CV1 (# 1028) */, "RA_0B_08_REG.RA22_CV" /* RA02_CV2 (# 1029) */, "RA_0F_0C_REG.RA32_CV" /* RA02_CV3 (# 1030) */, "RA_13_10_REG.RA42_CV" /* RA02_CV4 (# 1031) */, "RA_17_14_REG.RA52_CV" /* RA02_CV5 (# 1032) */, "RA_1B_18_REG.RA62_CV" /* RA02_CV6 (# 1033) */, "RA_1F_1C_REG.RA72_CV" /* RA02_CV7 (# 1034) */, "RA_23_20_REG.RA82_CV" /* RA02_CV8 (# 1035) */, "RA_27_24_REG.RA92_CV" /* RA02_CV9 (# 1036) */, "RA_2B_28_REG.RA102_CV" /* RA02_CV10 (# 1037) */, "RA_2F_2C_REG.RA112_CV" /* RA02_CV11 (# 1038) */, "RA_03_00_REG.RA02_MG" /* RA02_MG (# 1039) */, "RA_07_04_REG.RA12_MG" /* RA02_MG1 (# 1040) */, "RA_0B_08_REG.RA22_MG" /* RA02_MG2 (# 1041) */, "RA_0F_0C_REG.RA32_MG" /* RA02_MG3 (# 1042) */, "RA_13_10_REG.RA42_MG" /* RA02_MG4 (# 1043) */, "RA_17_14_REG.RA52_MG" /* RA02_MG5 (# 1044) */, "RA_1B_18_REG.RA62_MG" /* RA02_MG6 (# 1045) */, "RA_1F_1C_REG.RA72_MG" /* RA02_MG7 (# 1046) */, "RA_23_20_REG.RA82_MG" /* RA02_MG8 (# 1047) */, "RA_27_24_REG.RA92_MG" /* RA02_MG9 (# 1048) */, "RA_2B_28_REG.RA102_MG" /* RA02_MG10 (# 1049) */, "RA_2F_2C_REG.RA112_MG" /* RA02_MG11 (# 1050) */, "RA_03_00_REG.RA02_SPAN" /* RA02_SPAN (# 1051) */, "RA_07_04_REG.RA12_SPAN" /* RA02_SPAN1 (# 1052) */, "RA_0B_08_REG.RA22_SPAN" /* RA02_SPAN2 (# 1053) */, "RA_0F_0C_REG.RA32_SPAN" /* RA02_SPAN3 (# 1054) */, "RA_13_10_REG.RA42_SPAN" /* RA02_SPAN4 (# 1055) */, "RA_17_14_REG.RA52_SPAN" /* RA02_SPAN5 (# 1056) */, "RA_1B_18_REG.RA62_SPAN" /* RA02_SPAN6 (# 1057) */, "RA_1F_1C_REG.RA72_SPAN" /* RA02_SPAN7 (# 1058) */, "RA_23_20_REG.RA82_SPAN" /* RA02_SPAN8 (# 1059) */, "RA_27_24_REG.RA92_SPAN" /* RA02_SPAN9 (# 1060) */, "RA_2B_28_REG.RA102_SPAN" /* RA02_SPAN10 (# 1061) */, "RA_2F_2C_REG.RA112_SPAN" /* RA02_SPAN11 (# 1062) */, "RA_03_00_REG.RA02_TXTAG" /* RA02_TXTAG (# 1063) */, "RA_07_04_REG.RA12_TXTAG" /* RA02_TXTAG1 (# 1064) */, "RA_0B_08_REG.RA22_TXTAG" /* RA02_TXTAG2 (# 1065) */, "RA_0F_0C_REG.RA32_TXTAG" /* RA02_TXTAG3 (# 1066) */, "RA_13_10_REG.RA42_TXTAG" /* RA02_TXTAG4 (# 1067) */, "RA_17_14_REG.RA52_TXTAG" /* RA02_TXTAG5 (# 1068) */, "RA_1B_18_REG.RA62_TXTAG" /* RA02_TXTAG6 (# 1069) */, "RA_1F_1C_REG.RA72_TXTAG" /* RA02_TXTAG7 (# 1070) */, "RA_23_20_REG.RA82_TXTAG" /* RA02_TXTAG8 (# 1071) */, "RA_27_24_REG.RA92_TXTAG" /* RA02_TXTAG9 (# 1072) */, "RA_2B_28_REG.RA102_TXTAG" /* RA02_TXTAG10 (# 1073) */, "RA_2F_2C_REG.RA112_TXTAG" /* RA02_TXTAG11 (# 1074) */, "RA_03_00_REG.RA02_VALID" /* RA02_VALID (# 1075) */, "RA_07_04_REG.RA12_VALID" /* RA02_VALID1 (# 1076) */, "RA_0B_08_REG.RA22_VALID" /* RA02_VALID2 (# 1077) */, "RA_0F_0C_REG.RA32_VALID" /* RA02_VALID3 (# 1078) */, "RA_13_10_REG.RA42_VALID" /* RA02_VALID4 (# 1079) */, "RA_17_14_REG.RA52_VALID" /* RA02_VALID5 (# 1080) */, "RA_1B_18_REG.RA62_VALID" /* RA02_VALID6 (# 1081) */, "RA_1F_1C_REG.RA72_VALID" /* RA02_VALID7 (# 1082) */, "RA_23_20_REG.RA82_VALID" /* RA02_VALID8 (# 1083) */, "RA_27_24_REG.RA92_VALID" /* RA02_VALID9 (# 1084) */, "RA_2B_28_REG.RA102_VALID" /* RA02_VALID10 (# 1085) */, "RA_2F_2C_REG.RA112_VALID" /* RA02_VALID11 (# 1086) */, "RA_03_00_REG.RA03_ACT" /* RA03_ACT (# 1087) */, "RA_07_04_REG.RA13_ACT" /* RA03_ACT1 (# 1088) */, "RA_0B_08_REG.RA23_ACT" /* RA03_ACT2 (# 1089) */, "RA_0F_0C_REG.RA33_ACT" /* RA03_ACT3 (# 1090) */, "RA_13_10_REG.RA43_ACT" /* RA03_ACT4 (# 1091) */, "RA_17_14_REG.RA53_ACT" /* RA03_ACT5 (# 1092) */, "RA_1B_18_REG.RA63_ACT" /* RA03_ACT6 (# 1093) */, "RA_1F_1C_REG.RA73_ACT" /* RA03_ACT7 (# 1094) */, "RA_23_20_REG.RA83_ACT" /* RA03_ACT8 (# 1095) */, "RA_27_24_REG.RA93_ACT" /* RA03_ACT9 (# 1096) */, "RA_2B_28_REG.RA103_ACT" /* RA03_ACT10 (# 1097) */, "RA_2F_2C_REG.RA113_ACT" /* RA03_ACT11 (# 1098) */, "RA_03_00_REG.RA03_CV" /* RA03_CV (# 1099) */, "RA_07_04_REG.RA13_CV" /* RA03_CV1 (# 1100) */, "RA_0B_08_REG.RA23_CV" /* RA03_CV2 (# 1101) */, "RA_0F_0C_REG.RA33_CV" /* RA03_CV3 (# 1102) */, "RA_13_10_REG.RA43_CV" /* RA03_CV4 (# 1103) */, "RA_17_14_REG.RA53_CV" /* RA03_CV5 (# 1104) */, "RA_1B_18_REG.RA63_CV" /* RA03_CV6 (# 1105) */, "RA_1F_1C_REG.RA73_CV" /* RA03_CV7 (# 1106) */, "RA_23_20_REG.RA83_CV" /* RA03_CV8 (# 1107) */, "RA_27_24_REG.RA93_CV" /* RA03_CV9 (# 1108) */, "RA_2B_28_REG.RA103_CV" /* RA03_CV10 (# 1109) */, "RA_2F_2C_REG.RA113_CV" /* RA03_CV11 (# 1110) */, "RA_03_00_REG.RA03_MG" /* RA03_MG (# 1111) */, "RA_07_04_REG.RA13_MG" /* RA03_MG1 (# 1112) */, "RA_0B_08_REG.RA23_MG" /* RA03_MG2 (# 1113) */, "RA_0F_0C_REG.RA33_MG" /* RA03_MG3 (# 1114) */, "RA_13_10_REG.RA43_MG" /* RA03_MG4 (# 1115) */, "RA_17_14_REG.RA53_MG" /* RA03_MG5 (# 1116) */, "RA_1B_18_REG.RA63_MG" /* RA03_MG6 (# 1117) */, "RA_1F_1C_REG.RA73_MG" /* RA03_MG7 (# 1118) */, "RA_23_20_REG.RA83_MG" /* RA03_MG8 (# 1119) */, "RA_27_24_REG.RA93_MG" /* RA03_MG9 (# 1120) */, "RA_2B_28_REG.RA103_MG" /* RA03_MG10 (# 1121) */, "RA_2F_2C_REG.RA113_MG" /* RA03_MG11 (# 1122) */, "RA_03_00_REG.RA03_SPAN" /* RA03_SPAN (# 1123) */, "RA_07_04_REG.RA13_SPAN" /* RA03_SPAN1 (# 1124) */, "RA_0B_08_REG.RA23_SPAN" /* RA03_SPAN2 (# 1125) */, "RA_0F_0C_REG.RA33_SPAN" /* RA03_SPAN3 (# 1126) */, "RA_13_10_REG.RA43_SPAN" /* RA03_SPAN4 (# 1127) */, "RA_17_14_REG.RA53_SPAN" /* RA03_SPAN5 (# 1128) */, "RA_1B_18_REG.RA63_SPAN" /* RA03_SPAN6 (# 1129) */, "RA_1F_1C_REG.RA73_SPAN" /* RA03_SPAN7 (# 1130) */, "RA_23_20_REG.RA83_SPAN" /* RA03_SPAN8 (# 1131) */, "RA_27_24_REG.RA93_SPAN" /* RA03_SPAN9 (# 1132) */, "RA_2B_28_REG.RA103_SPAN" /* RA03_SPAN10 (# 1133) */, "RA_2F_2C_REG.RA113_SPAN" /* RA03_SPAN11 (# 1134) */, "RA_03_00_REG.RA03_TXTAG" /* RA03_TXTAG (# 1135) */, "RA_07_04_REG.RA13_TXTAG" /* RA03_TXTAG1 (# 1136) */, "RA_0B_08_REG.RA23_TXTAG" /* RA03_TXTAG2 (# 1137) */, "RA_0F_0C_REG.RA33_TXTAG" /* RA03_TXTAG3 (# 1138) */, "RA_13_10_REG.RA43_TXTAG" /* RA03_TXTAG4 (# 1139) */, "RA_17_14_REG.RA53_TXTAG" /* RA03_TXTAG5 (# 1140) */, "RA_1B_18_REG.RA63_TXTAG" /* RA03_TXTAG6 (# 1141) */, "RA_1F_1C_REG.RA73_TXTAG" /* RA03_TXTAG7 (# 1142) */, "RA_23_20_REG.RA83_TXTAG" /* RA03_TXTAG8 (# 1143) */, "RA_27_24_REG.RA93_TXTAG" /* RA03_TXTAG9 (# 1144) */, "RA_2B_28_REG.RA103_TXTAG" /* RA03_TXTAG10 (# 1145) */, "RA_2F_2C_REG.RA113_TXTAG" /* RA03_TXTAG11 (# 1146) */, "RA_03_00_REG.RA03_VALID" /* RA03_VALID (# 1147) */, "RA_07_04_REG.RA13_VALID" /* RA03_VALID1 (# 1148) */, "RA_0B_08_REG.RA23_VALID" /* RA03_VALID2 (# 1149) */, "RA_0F_0C_REG.RA33_VALID" /* RA03_VALID3 (# 1150) */, "RA_13_10_REG.RA43_VALID" /* RA03_VALID4 (# 1151) */, "RA_17_14_REG.RA53_VALID" /* RA03_VALID5 (# 1152) */, "RA_1B_18_REG.RA63_VALID" /* RA03_VALID6 (# 1153) */, "RA_1F_1C_REG.RA73_VALID" /* RA03_VALID7 (# 1154) */, "RA_23_20_REG.RA83_VALID" /* RA03_VALID8 (# 1155) */, "RA_27_24_REG.RA93_VALID" /* RA03_VALID9 (# 1156) */, "RA_2B_28_REG.RA103_VALID" /* RA03_VALID10 (# 1157) */, "RA_2F_2C_REG.RA113_VALID" /* RA03_VALID11 (# 1158) */, "RMON_CTL_REG.BAS" /* RMON_BAS (# 1159) */, "RMON_CTL_REG.CAC" /* RMON_CAC (# 1160) */, "RMON_ST_REG.COUNTER" /* RMON_COUNTER (# 1161) */, NULL /* RMON_HIGH_COUNTER (# 1162) */, NULL /* RMON_LOW_COUNTER (# 1163) */, "RMON_CTL_REG.OFFSET" /* RMON_OFFSET (# 1164) */, "RMON_CTL_REG.PORTC" /* RMON_PORTC (# 1165) */, "TP_FLT_ACT_REG.ATF0" /* TYPE_FILTER_ATF (# 1166) */, "TP_FLT_ACT_REG.ATF1" /* TYPE_FILTER_ATF1 (# 1167) */, "TP_FLT_ACT_REG.ATF2" /* TYPE_FILTER_ATF2 (# 1168) */, "TP_FLT_ACT_REG.ATF3" /* TYPE_FILTER_ATF3 (# 1169) */, "TP_FLT_ACT_REG.ATF4" /* TYPE_FILTER_ATF4 (# 1170) */, "TP_FLT_ACT_REG.ATF5" /* TYPE_FILTER_ATF5 (# 1171) */, "TP_FLT_ACT_REG.ATF6" /* TYPE_FILTER_ATF6 (# 1172) */, "TP_FLT_ACT_REG.ATF7" /* TYPE_FILTER_ATF7 (# 1173) */, "TP_FLT_ACT_REG.QTF0" /* TYPE_FILTER_QTF (# 1174) */, "TP_FLT_ACT_REG.QTF1" /* TYPE_FILTER_QTF1 (# 1175) */, "TP_FLT_ACT_REG.QTF2" /* TYPE_FILTER_QTF2 (# 1176) */, "TP_FLT_ACT_REG.QTF3" /* TYPE_FILTER_QTF3 (# 1177) */, "TP_FLT_ACT_REG.QTF4" /* TYPE_FILTER_QTF4 (# 1178) */, "TP_FLT_ACT_REG.QTF5" /* TYPE_FILTER_QTF5 (# 1179) */, "TP_FLT_ACT_REG.QATF6" /* TYPE_FILTER_QTF6 (# 1180) */, "TP_FLT_ACT_REG.QATF7" /* TYPE_FILTER_QTF7 (# 1181) */, "TP_FLT10_REG.VCET0" /* TYPE_FILTER_VCET0 (# 1182) */, "TP_FLT32_REG.VCET0" /* TYPE_FILTER_VCET01 (# 1183) */, "TP_FLT54_REG.VCET0" /* TYPE_FILTER_VCET02 (# 1184) */, "TP_FLT76_REG.VCET0" /* TYPE_FILTER_VCET03 (# 1185) */, "TP_FLT10_REG.VCET1" /* TYPE_FILTER_VCET1 (# 1186) */, "TP_FLT32_REG.VCET1" /* TYPE_FILTER_VCET11 (# 1187) */, "TP_FLT54_REG.VCET1" /* TYPE_FILTER_VCET12 (# 1188) */, "TP_FLT76_REG.VCET1" /* TYPE_FILTER_VCET13 (# 1189) */, NULL /* TYPE_FILTER_VCET_ALL (# 1190) */, NULL /* TYPE_FILTER_VCET_ALL1 (# 1191) */, NULL /* TYPE_FILTER_VCET_ALL2 (# 1192) */, NULL /* TYPE_FILTER_VCET_ALL3 (# 1193) */, NULL /* TYPE_FILTER_VCET_ALL4 (# 1194) */, NULL /* TYPE_FILTER_VCET_ALL5 (# 1195) */, NULL /* TYPE_FILTER_VCET_ALL6 (# 1196) */, NULL /* TYPE_FILTER_VCET_ALL7 (# 1197) */, "VLAN_FLT0_REG.M" /* VLAN_FILTER_M (# 1198) */, "VLAN_FLT1_REG.M" /* VLAN_FILTER_M1 (# 1199) */, "VLAN_FLT2_REG.M" /* VLAN_FILTER_M2 (# 1200) */, "VLAN_FLT3_REG.M" /* VLAN_FILTER_M3 (# 1201) */, "VLAN_FLT4_REG.M" /* VLAN_FILTER_M4 (# 1202) */, "VLAN_FLT5_REG.M" /* VLAN_FILTER_M5 (# 1203) */, "VLAN_FLT6_REG.M" /* VLAN_FILTER_M6 (# 1204) */, "VLAN_FLT7_REG.M" /* VLAN_FILTER_M7 (# 1205) */, "VLAN_FLT8_REG.M" /* VLAN_FILTER_M8 (# 1206) */, "VLAN_FLT9_REG.M" /* VLAN_FILTER_M9 (# 1207) */, "VLAN_FLT10_REG.M" /* VLAN_FILTER_M10 (# 1208) */, "VLAN_FLT11_REG.M" /* VLAN_FILTER_M11 (# 1209) */, "VLAN_FLT12_REG.M" /* VLAN_FILTER_M12 (# 1210) */, "VLAN_FLT13_REG.M" /* VLAN_FILTER_M13 (# 1211) */, "VLAN_FLT14_REG.M" /* VLAN_FILTER_M14 (# 1212) */, "VLAN_FLT15_REG.M" /* VLAN_FILTER_M15 (# 1213) */, "VLAN_FLT0_REG.TM" /* VLAN_FILTER_TM (# 1214) */, "VLAN_FLT1_REG.TM" /* VLAN_FILTER_TM1 (# 1215) */, "VLAN_FLT2_REG.TM" /* VLAN_FILTER_TM2 (# 1216) */, "VLAN_FLT3_REG.TM" /* VLAN_FILTER_TM3 (# 1217) */, "VLAN_FLT4_REG.TM" /* VLAN_FILTER_TM4 (# 1218) */, "VLAN_FLT5_REG.TM" /* VLAN_FILTER_TM5 (# 1219) */, "VLAN_FLT6_REG.TM" /* VLAN_FILTER_TM6 (# 1220) */, "VLAN_FLT7_REG.TM" /* VLAN_FILTER_TM7 (# 1221) */, "VLAN_FLT8_REG.TM" /* VLAN_FILTER_TM8 (# 1222) */, "VLAN_FLT9_REG.TM" /* VLAN_FILTER_TM9 (# 1223) */, "VLAN_FLT10_REG.TM" /* VLAN_FILTER_TM10 (# 1224) */, "VLAN_FLT11_REG.TM" /* VLAN_FILTER_TM11 (# 1225) */, "VLAN_FLT12_REG.TM" /* VLAN_FILTER_TM12 (# 1226) */, "VLAN_FLT13_REG.TM" /* VLAN_FILTER_TM13 (# 1227) */, "VLAN_FLT14_REG.TM" /* VLAN_FILTER_TM14 (# 1228) */, "VLAN_FLT15_REG.TM" /* VLAN_FILTER_TM15 (# 1229) */, "VLAN_FLT0_REG.FID" /* VLAN_FILTER_VFID (# 1230) */, "VLAN_FLT1_REG.FID" /* VLAN_FILTER_VFID1 (# 1231) */, "VLAN_FLT2_REG.FID" /* VLAN_FILTER_VFID2 (# 1232) */, "VLAN_FLT3_REG.FID" /* VLAN_FILTER_VFID3 (# 1233) */, "VLAN_FLT4_REG.FID" /* VLAN_FILTER_VFID4 (# 1234) */, "VLAN_FLT5_REG.FID" /* VLAN_FILTER_VFID5 (# 1235) */, "VLAN_FLT6_REG.FID" /* VLAN_FILTER_VFID6 (# 1236) */, "VLAN_FLT7_REG.FID" /* VLAN_FILTER_VFID7 (# 1237) */, "VLAN_FLT8_REG.FID" /* VLAN_FILTER_VFID8 (# 1238) */, "VLAN_FLT9_REG.FID" /* VLAN_FILTER_VFID9 (# 1239) */, "VLAN_FLT10_REG.FID" /* VLAN_FILTER_VFID10 (# 1240) */, "VLAN_FLT11_REG.FID" /* VLAN_FILTER_VFID11 (# 1241) */, "VLAN_FLT12_REG.FID" /* VLAN_FILTER_VFID12 (# 1242) */, "VLAN_FLT13_REG.FID" /* VLAN_FILTER_VFID13 (# 1243) */, "VLAN_FLT14_REG.FID" /* VLAN_FILTER_VFID14 (# 1244) */, "VLAN_FLT15_REG.FID" /* VLAN_FILTER_VFID15 (# 1245) */, "VLAN_FLT0_REG.VID" /* VLAN_FILTER_VID (# 1246) */, "VLAN_FLT1_REG.VID" /* VLAN_FILTER_VID1 (# 1247) */, "VLAN_FLT2_REG.VID" /* VLAN_FILTER_VID2 (# 1248) */, "VLAN_FLT3_REG.VID" /* VLAN_FILTER_VID3 (# 1249) */, "VLAN_FLT4_REG.VID" /* VLAN_FILTER_VID4 (# 1250) */, "VLAN_FLT5_REG.VID" /* VLAN_FILTER_VID5 (# 1251) */, "VLAN_FLT6_REG.VID" /* VLAN_FILTER_VID6 (# 1252) */, "VLAN_FLT7_REG.VID" /* VLAN_FILTER_VID7 (# 1253) */, "VLAN_FLT8_REG.VID" /* VLAN_FILTER_VID8 (# 1254) */, "VLAN_FLT9_REG.VID" /* VLAN_FILTER_VID9 (# 1255) */, "VLAN_FLT10_REG.VID" /* VLAN_FILTER_VID10 (# 1256) */, "VLAN_FLT11_REG.VID" /* VLAN_FILTER_VID11 (# 1257) */, "VLAN_FLT12_REG.VID" /* VLAN_FILTER_VID12 (# 1258) */, "VLAN_FLT13_REG.VID" /* VLAN_FILTER_VID13 (# 1259) */, "VLAN_FLT14_REG.VID" /* VLAN_FILTER_VID14 (# 1260) */, "VLAN_FLT15_REG.VID" /* VLAN_FILTER_VID15 (# 1261) */, "VLAN_FLT0_REG.VP" /* VLAN_FILTER_VP (# 1262) */, "VLAN_FLT1_REG.VP" /* VLAN_FILTER_VP1 (# 1263) */, "VLAN_FLT2_REG.VP" /* VLAN_FILTER_VP2 (# 1264) */, "VLAN_FLT3_REG.VP" /* VLAN_FILTER_VP3 (# 1265) */, "VLAN_FLT4_REG.VP" /* VLAN_FILTER_VP4 (# 1266) */, "VLAN_FLT5_REG.VP" /* VLAN_FILTER_VP5 (# 1267) */, "VLAN_FLT6_REG.VP" /* VLAN_FILTER_VP6 (# 1268) */, "VLAN_FLT7_REG.VP" /* VLAN_FILTER_VP7 (# 1269) */, "VLAN_FLT8_REG.VP" /* VLAN_FILTER_VP8 (# 1270) */, "VLAN_FLT9_REG.VP" /* VLAN_FILTER_VP9 (# 1271) */, "VLAN_FLT10_REG.VP" /* VLAN_FILTER_VP10 (# 1272) */, "VLAN_FLT11_REG.VP" /* VLAN_FILTER_VP11 (# 1273) */, "VLAN_FLT12_REG.VP" /* VLAN_FILTER_VP12 (# 1274) */, "VLAN_FLT13_REG.VP" /* VLAN_FILTER_VP13 (# 1275) */, "VLAN_FLT14_REG.VP" /* VLAN_FILTER_VP14 (# 1276) */, "VLAN_FLT15_REG.VP" /* VLAN_FILTER_VP15 (# 1277) */, "VLAN_FLT0_REG.VV" /* VLAN_FILTER_VV (# 1278) */, "VLAN_FLT1_REG.VV" /* VLAN_FILTER_VV1 (# 1279) */, "VLAN_FLT2_REG.VV" /* VLAN_FILTER_VV2 (# 1280) */, "VLAN_FLT3_REG.VV" /* VLAN_FILTER_VV3 (# 1281) */, "VLAN_FLT4_REG.VV" /* VLAN_FILTER_VV4 (# 1282) */, "VLAN_FLT5_REG.VV" /* VLAN_FILTER_VV5 (# 1283) */, "VLAN_FLT6_REG.VV" /* VLAN_FILTER_VV6 (# 1284) */, "VLAN_FLT7_REG.VV" /* VLAN_FILTER_VV7 (# 1285) */, "VLAN_FLT8_REG.VV" /* VLAN_FILTER_VV8 (# 1286) */, "VLAN_FLT9_REG.VV" /* VLAN_FILTER_VV9 (# 1287) */, "VLAN_FLT10_REG.VV" /* VLAN_FILTER_VV10 (# 1288) */, "VLAN_FLT11_REG.VV" /* VLAN_FILTER_VV11 (# 1289) */, "VLAN_FLT12_REG.VV" /* VLAN_FILTER_VV12 (# 1290) */, "VLAN_FLT13_REG.VV" /* VLAN_FILTER_VV13 (# 1291) */, "VLAN_FLT14_REG.VV" /* VLAN_FILTER_VV14 (# 1292) */, "VLAN_FLT15_REG.VV" /* VLAN_FILTER_VV15 (# 1293) */, /* Last Element (# 1294) */ NULL }; #endif /* #ifdef IFX_ETHSW_DEBUG */