/****************************************************************************** Copyright (c) 2010 Lantiq Deutschland GmbH Am Campeon 3; 85579 Neubiberg, Germany For licensing information, see the file 'LICENSE' in the root folder of this software module. ******************************************************************************/ #include "commonReg.h" #include "Tantos3G.h" #include "regmapper.h" IFX_ETHSW_regMapper_t regMapper_TANTOS_3G[] = { /* ARP_APT (# 0) */ { (IFX_uint16_t)ARP_APT, (IFX_uint16_t)TANTOS_3G_AR_APT_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_APT_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_APT_SIZE}, /* ARP_MACA (# 1) */ { (IFX_uint16_t)ARP_MACA, (IFX_uint16_t)TANTOS_3G_AR_MACA_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_MACA_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_MACA_SIZE}, /* ARP_RAPA (# 2) */ { (IFX_uint16_t)ARP_RAPA, (IFX_uint16_t)TANTOS_3G_AR_RAPA_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RAPA_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RAPA_SIZE}, /* ARP_RAPOTH (# 3) */ { (IFX_uint16_t)ARP_RAPOTH, (IFX_uint16_t)TANTOS_3G_AR_RAPOTH_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RAPOTH_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RAPOTH_SIZE}, /* ARP_RAPP (# 4) */ { (IFX_uint16_t)ARP_RAPP, (IFX_uint16_t)TANTOS_3G_AR_RAPP_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RAPP_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RAPP_SIZE}, /* ARP_RAPPE (# 5) */ { (IFX_uint16_t)ARP_RAPPE, (IFX_uint16_t)TANTOS_3G_AR_RAPPE_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RAPPE_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RAPPE_SIZE}, /* ARP_RAPTM (# 6) */ { (IFX_uint16_t)ARP_RAPTM, (IFX_uint16_t)TANTOS_3G_AR_RAPTM_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RAPTM_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RAPTM_SIZE}, /* ARP_RPT (# 7) */ { (IFX_uint16_t)ARP_RPT, (IFX_uint16_t)TANTOS_3G_AR_RPT_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_RPT_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_RPT_SIZE}, /* ARP_TAP (# 8) */ { (IFX_uint16_t)ARP_TAP, (IFX_uint16_t)TANTOS_3G_AR_TAP_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_TAP_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_TAP_SIZE}, /* ARP_TAPTS (# 9) */ { (IFX_uint16_t)ARP_TAPTS, (IFX_uint16_t)TANTOS_3G_AR_TAPTS_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_TAPTS_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_TAPTS_SIZE}, /* ARP_TRP (# 10) */ { (IFX_uint16_t)ARP_TRP, (IFX_uint16_t)TANTOS_3G_AR_TRP_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_TRP_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_TRP_SIZE}, /* ARP_UPT (# 11) */ { (IFX_uint16_t)ARP_UPT, (IFX_uint16_t)TANTOS_3G_AR_UPT_OFFSET, (IFX_uint8_t)TANTOS_3G_AR_UPT_SHIFT, (IFX_uint8_t)TANTOS_3G_AR_UPT_SIZE}, /* BIST_CTBR (# 12) */ { (IFX_uint16_t)BIST_CTBR, (IFX_uint16_t)TANTOS_3G_GSHS_CTBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_CTBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_CTBR_SIZE}, /* BIST_DBBR (# 13) */ { (IFX_uint16_t)BIST_DBBR, (IFX_uint16_t)TANTOS_3G_GSHS_DBBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_DBBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_DBBR_SIZE}, /* BIST_DONE (# 14) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BIST_HIGTBR (# 15) */ { (IFX_uint16_t)BIST_HIGTBR, (IFX_uint16_t)TANTOS_3G_GSHS_HIGTBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_HIGTBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_HIGTBR_SIZE}, /* BIST_HISTBR (# 16) */ { (IFX_uint16_t)BIST_HISTBR, (IFX_uint16_t)TANTOS_3G_GSHS_HISTBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_HISTBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_HISTBR_SIZE}, /* BIST_LLTBR (# 17) */ { (IFX_uint16_t)BIST_LLTBR, (IFX_uint16_t)TANTOS_3G_GSHS_LLTBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_LLTBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_LLTBR_SIZE}, /* BIST_LTBR (# 18) */ { (IFX_uint16_t)BIST_LTBR, (IFX_uint16_t)TANTOS_3G_GSHS_LTBR_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_LTBR_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_LTBR_SIZE}, /* BUFFER_PFA (# 19) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PFO0 (# 20) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PFO1 (# 21) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PFO2 (# 22) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PUA (# 23) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PUO0 (# 24) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PUO1 (# 25) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_PUO2 (# 26) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_THA (# 27) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_THO (# 28) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_TLA (# 29) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* BUFFER_TLO (# 30) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* CHIPID_BOND (# 31) */ { (IFX_uint16_t)CHIPID_BOND, (IFX_uint16_t)TANTOS_3G_CI0_BOND_OFFSET, (IFX_uint8_t)TANTOS_3G_CI0_BOND_SHIFT, (IFX_uint8_t)TANTOS_3G_CI0_BOND_SIZE}, /* CHIPID_PC (# 32) */ { (IFX_uint16_t)CHIPID_PC, (IFX_uint16_t)TANTOS_3G_CI1_PC_OFFSET, (IFX_uint8_t)TANTOS_3G_CI1_PC_SHIFT, (IFX_uint8_t)TANTOS_3G_CI1_PC_SIZE}, /* CHIPID_VN (# 33) */ { (IFX_uint16_t)CHIPID_VN, (IFX_uint16_t)TANTOS_3G_CI0_VN_OFFSET, (IFX_uint8_t)TANTOS_3G_CI0_VN_SHIFT, (IFX_uint8_t)TANTOS_3G_CI0_VN_SIZE}, /* CONGESTION_EDSTX (# 34) */ { (IFX_uint16_t)CONGESTION_EDSTX, (IFX_uint16_t)TANTOS_3G_CCR_EDSTX_OFFSET, (IFX_uint8_t)TANTOS_3G_CCR_EDSTX_SHIFT, (IFX_uint8_t)TANTOS_3G_CCR_EDSTX_SIZE}, /* CONGESTION_IJT (# 35) */ { (IFX_uint16_t)CONGESTION_IJT, (IFX_uint16_t)TANTOS_3G_CCR_IJT_OFFSET, (IFX_uint8_t)TANTOS_3G_CCR_IJT_SHIFT, (IFX_uint8_t)TANTOS_3G_CCR_IJT_SIZE}, /* CONGESTION_IRSJA (# 36) */ { (IFX_uint16_t)CONGESTION_IRSJA, (IFX_uint16_t)TANTOS_3G_CCR_IRSJA_OFFSET, (IFX_uint8_t)TANTOS_3G_CCR_IRSJA_SHIFT, (IFX_uint8_t)TANTOS_3G_CCR_IRSJA_SIZE}, /* CONGESTION_STORM_100_TH (# 37) */ { (IFX_uint16_t)CONGESTION_STORM_100_TH, (IFX_uint16_t)TANTOS_3G_SCR0_STORM_100_TH_OFFSET, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_100_TH_SHIFT, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_100_TH_SIZE}, /* CONGESTION_STORM_10_TH (# 38) */ { (IFX_uint16_t)CONGESTION_STORM_10_TH, (IFX_uint16_t)TANTOS_3G_SCR1_STORM_10_TH_OFFSET, (IFX_uint8_t)TANTOS_3G_SCR1_STORM_10_TH_SHIFT, (IFX_uint8_t)TANTOS_3G_SCR1_STORM_10_TH_SIZE}, /* CONGESTION_STORM_B (# 39) */ { (IFX_uint16_t)CONGESTION_STORM_B, (IFX_uint16_t)TANTOS_3G_SCR0_STORM_B_OFFSET, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_B_SHIFT, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_B_SIZE}, /* CONGESTION_STORM_M (# 40) */ { (IFX_uint16_t)CONGESTION_STORM_M, (IFX_uint16_t)TANTOS_3G_SCR0_STORM_M_OFFSET, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_M_SHIFT, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_M_SIZE}, /* CONGESTION_STORM_U (# 41) */ { (IFX_uint16_t)CONGESTION_STORM_U, (IFX_uint16_t)TANTOS_3G_SCR0_STORM_U_OFFSET, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_U_SHIFT, (IFX_uint8_t)TANTOS_3G_SCR0_STORM_U_SIZE}, /* DIFFSERV_PQA (# 42) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ0_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ0_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ0_SIZE}, /* DIFFSERV_PQA01 (# 43) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ1_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ1_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ1_SIZE}, /* DIFFSERV_PQA02 (# 44) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ2_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ2_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ2_SIZE}, /* DIFFSERV_PQA03 (# 45) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ3_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ3_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ3_SIZE}, /* DIFFSERV_PQA04 (# 46) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ4_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ4_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ4_SIZE}, /* DIFFSERV_PQA05 (# 47) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ5_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ5_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ5_SIZE}, /* DIFFSERV_PQA06 (# 48) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ6_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ6_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ6_SIZE}, /* DIFFSERV_PQA07 (# 49) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM0_PQ7_OFFSET, (IFX_uint8_t)TANTOS_3G_DM0_PQ7_SHIFT, (IFX_uint8_t)TANTOS_3G_DM0_PQ7_SIZE}, /* DIFFSERV_PQA08 (# 50) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQ8_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQ8_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQ8_SIZE}, /* DIFFSERV_PQA09 (# 51) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQ9_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQ9_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQ9_SIZE}, /* DIFFSERV_PQA10 (# 52) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQA_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQA_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQA_SIZE}, /* DIFFSERV_PQA11 (# 53) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQB_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQB_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQB_SIZE}, /* DIFFSERV_PQA12 (# 54) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQC_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQC_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQC_SIZE}, /* DIFFSERV_PQA13 (# 55) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQD_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQD_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQD_SIZE}, /* DIFFSERV_PQA14 (# 56) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQE_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQE_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQE_SIZE}, /* DIFFSERV_PQA15 (# 57) */ { (IFX_uint16_t)DIFFSERV_PQA, (IFX_uint16_t)TANTOS_3G_DM1_PQF_OFFSET, (IFX_uint8_t)TANTOS_3G_DM1_PQF_SHIFT, (IFX_uint8_t)TANTOS_3G_DM1_PQF_SIZE}, /* DIFFSERV_PQB (# 58) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ10_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ10_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ10_SIZE}, /* DIFFSERV_PQB01 (# 59) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ11_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ11_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ11_SIZE}, /* DIFFSERV_PQB02 (# 60) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ12_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ12_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ12_SIZE}, /* DIFFSERV_PQB03 (# 61) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ13_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ13_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ13_SIZE}, /* DIFFSERV_PQB04 (# 62) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ14_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ14_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ14_SIZE}, /* DIFFSERV_PQB05 (# 63) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ15_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ15_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ15_SIZE}, /* DIFFSERV_PQB06 (# 64) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ16_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ16_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ16_SIZE}, /* DIFFSERV_PQB07 (# 65) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM2_PQ17_OFFSET, (IFX_uint8_t)TANTOS_3G_DM2_PQ17_SHIFT, (IFX_uint8_t)TANTOS_3G_DM2_PQ17_SIZE}, /* DIFFSERV_PQB08 (# 66) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ18_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ18_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ18_SIZE}, /* DIFFSERV_PQB09 (# 67) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ19_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ19_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ19_SIZE}, /* DIFFSERV_PQB10 (# 68) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1A_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1A_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1A_SIZE}, /* DIFFSERV_PQB11 (# 69) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1B_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1B_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1B_SIZE}, /* DIFFSERV_PQB12 (# 70) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1C_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1C_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1C_SIZE}, /* DIFFSERV_PQB13 (# 71) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1D_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1D_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1D_SIZE}, /* DIFFSERV_PQB14 (# 72) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1E_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1E_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1E_SIZE}, /* DIFFSERV_PQB15 (# 73) */ { (IFX_uint16_t)DIFFSERV_PQB, (IFX_uint16_t)TANTOS_3G_DM3_PQ1F_OFFSET, (IFX_uint8_t)TANTOS_3G_DM3_PQ1F_SHIFT, (IFX_uint8_t)TANTOS_3G_DM3_PQ1F_SIZE}, /* DIFFSERV_PQC (# 74) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ20_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ20_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ20_SIZE}, /* DIFFSERV_PQC01 (# 75) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ21_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ21_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ21_SIZE}, /* DIFFSERV_PQC02 (# 76) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ22_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ22_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ22_SIZE}, /* DIFFSERV_PQC03 (# 77) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ23_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ23_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ23_SIZE}, /* DIFFSERV_PQC04 (# 78) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ24_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ24_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ24_SIZE}, /* DIFFSERV_PQC05 (# 79) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ25_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ25_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ25_SIZE}, /* DIFFSERV_PQC06 (# 80) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ26_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ26_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ26_SIZE}, /* DIFFSERV_PQC07 (# 81) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM4_PQ27_OFFSET, (IFX_uint8_t)TANTOS_3G_DM4_PQ27_SHIFT, (IFX_uint8_t)TANTOS_3G_DM4_PQ27_SIZE}, /* DIFFSERV_PQC08 (# 82) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ28_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ28_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ28_SIZE}, /* DIFFSERV_PQC09 (# 83) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ29_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ29_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ29_SIZE}, /* DIFFSERV_PQC10 (# 84) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2A_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2A_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2A_SIZE}, /* DIFFSERV_PQC11 (# 85) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2B_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2B_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2B_SIZE}, /* DIFFSERV_PQC12 (# 86) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2C_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2C_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2C_SIZE}, /* DIFFSERV_PQC13 (# 87) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2D_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2D_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2D_SIZE}, /* DIFFSERV_PQC14 (# 88) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2E_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2E_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2E_SIZE}, /* DIFFSERV_PQC15 (# 89) */ { (IFX_uint16_t)DIFFSERV_PQC, (IFX_uint16_t)TANTOS_3G_DM5_PQ2F_OFFSET, (IFX_uint8_t)TANTOS_3G_DM5_PQ2F_SHIFT, (IFX_uint8_t)TANTOS_3G_DM5_PQ2F_SIZE}, /* DIFFSERV_PQD (# 90) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ30_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ30_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ30_SIZE}, /* DIFFSERV_PQD01 (# 91) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ31_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ31_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ31_SIZE}, /* DIFFSERV_PQD02 (# 92) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ32_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ32_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ32_SIZE}, /* DIFFSERV_PQD03 (# 93) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ33_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ33_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ33_SIZE}, /* DIFFSERV_PQD04 (# 94) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ34_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ34_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ34_SIZE}, /* DIFFSERV_PQD05 (# 95) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ35_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ35_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ35_SIZE}, /* DIFFSERV_PQD06 (# 96) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ36_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ36_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ36_SIZE}, /* DIFFSERV_PQD07 (# 97) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM6_PQ37_OFFSET, (IFX_uint8_t)TANTOS_3G_DM6_PQ37_SHIFT, (IFX_uint8_t)TANTOS_3G_DM6_PQ37_SIZE}, /* DIFFSERV_PQD08 (# 98) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ38_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ38_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ38_SIZE}, /* DIFFSERV_PQD09 (# 99) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ39_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ39_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ39_SIZE}, /* DIFFSERV_PQD10 (# 100) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3A_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3A_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3A_SIZE}, /* DIFFSERV_PQD11 (# 101) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3B_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3B_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3B_SIZE}, /* DIFFSERV_PQD12 (# 102) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3C_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3C_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3C_SIZE}, /* DIFFSERV_PQD13 (# 103) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3D_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3D_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3D_SIZE}, /* DIFFSERV_PQD14 (# 104) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3E_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3E_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3E_SIZE}, /* DIFFSERV_PQD15 (# 105) */ { (IFX_uint16_t)DIFFSERV_PQD, (IFX_uint16_t)TANTOS_3G_DM7_PQ3F_OFFSET, (IFX_uint8_t)TANTOS_3G_DM7_PQ3F_SHIFT, (IFX_uint8_t)TANTOS_3G_DM7_PQ3F_SIZE}, /* DOT1X_PRIORITY_1PPQ (# 106) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ0_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ0_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ0_SIZE}, /* DOT1X_PRIORITY_1PPQ1 (# 107) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ1_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ1_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ1_SIZE}, /* DOT1X_PRIORITY_1PPQ2 (# 108) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ2_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ2_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ2_SIZE}, /* DOT1X_PRIORITY_1PPQ3 (# 109) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ3_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ3_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ3_SIZE}, /* DOT1X_PRIORITY_1PPQ4 (# 110) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ4_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ4_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ4_SIZE}, /* DOT1X_PRIORITY_1PPQ5 (# 111) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ5_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ5_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ5_SIZE}, /* DOT1X_PRIORITY_1PPQ6 (# 112) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ6_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ6_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ6_SIZE}, /* DOT1X_PRIORITY_1PPQ7 (# 113) */ { (IFX_uint16_t)DOT1X_PRIORITY_1PPQ, (IFX_uint16_t)TANTOS_3G_1PPM_1PPQ7_OFFSET, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ7_SHIFT, (IFX_uint8_t)TANTOS_3G_1PPM_1PPQ7_SIZE}, /* GLOBAL_ATS (# 114) */ { (IFX_uint16_t)GLOBAL_ATS, (IFX_uint16_t)TANTOS_3G_SGC1_ATS_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_ATS_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_ATS_SIZE}, /* GLOBAL_CTTX (# 115) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_DIE (# 116) */ { (IFX_uint16_t)GLOBAL_DIE, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DIE_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIE_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIE_SIZE}, /* GLOBAL_DII6P (# 117) */ { (IFX_uint16_t)GLOBAL_DII6P, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DII6P_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DII6P_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DII6P_SIZE}, /* GLOBAL_DIIP (# 118) */ { (IFX_uint16_t)GLOBAL_DIIP, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DIIP_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIIP_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIIP_SIZE}, /* GLOBAL_DIIPS (# 119) */ { (IFX_uint16_t)GLOBAL_DIIPS, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DIIPS_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIIPS_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIIPS_SIZE}, /* GLOBAL_DIS (# 120) */ { (IFX_uint16_t)GLOBAL_DIS, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DIS_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIS_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIS_SIZE}, /* GLOBAL_DIVS (# 121) */ { (IFX_uint16_t)GLOBAL_DIVS, (IFX_uint16_t)TANTOS_3G_PIOFGPM_DIVS_OFFSET, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIVS_SHIFT, (IFX_uint8_t)TANTOS_3G_PIOFGPM_DIVS_SIZE}, /* GLOBAL_DMQ0 (# 122) */ { (IFX_uint16_t)GLOBAL_DMQ0, (IFX_uint16_t)TANTOS_3G_SGC1_DMQ0_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ0_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ0_SIZE}, /* GLOBAL_DMQ1 (# 123) */ { (IFX_uint16_t)GLOBAL_DMQ1, (IFX_uint16_t)TANTOS_3G_SGC1_DMQ1_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ1_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ1_SIZE}, /* GLOBAL_DMQ2 (# 124) */ { (IFX_uint16_t)GLOBAL_DMQ2, (IFX_uint16_t)TANTOS_3G_SGC1_DMQ2_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ2_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ2_SIZE}, /* GLOBAL_DMQ3 (# 125) */ { (IFX_uint16_t)GLOBAL_DMQ3, (IFX_uint16_t)TANTOS_3G_SGC1_DMQ3_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ3_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_DMQ3_SIZE}, /* GLOBAL_DPWECH (# 126) */ { (IFX_uint16_t)GLOBAL_DPWECH, (IFX_uint16_t)TANTOS_3G_SGC1_DPWECH_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_DPWECH_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_DPWECH_SIZE}, /* GLOBAL_DUPCOLSP (# 127) */ { (IFX_uint16_t)GLOBAL_DUPCOLSP, (IFX_uint16_t)TANTOS_3G_SGC2_DUPCOLSP_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_DUPCOLSP_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_DUPCOLSP_SIZE}, /* GLOBAL_ICRCCD (# 128) */ { (IFX_uint16_t)GLOBAL_ICRCCD, (IFX_uint16_t)TANTOS_3G_SGC2_ICRCCD_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_ICRCCD_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_ICRCCD_SIZE}, /* GLOBAL_ITENLMT (# 129) */ { (IFX_uint16_t)GLOBAL_ITENLMT, (IFX_uint16_t)TANTOS_3G_SGC2_ITENLMT_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_ITENLMT_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_ITENLMT_SIZE}, /* GLOBAL_ITRUNK (# 130) */ { (IFX_uint16_t)GLOBAL_ITRUNK, (IFX_uint16_t)TANTOS_3G_SGC2_ITRUNK_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_ITRUNK_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_ITRUNK_SIZE}, /* GLOBAL_LPE (# 131) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* GLOBAL_MPL (# 132) */ { (IFX_uint16_t)GLOBAL_MPL, (IFX_uint16_t)TANTOS_3G_SGC1_MPL_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_MPL_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_MPL_SIZE}, /* GLOBAL_P4M (# 133) */ { (IFX_uint16_t)GLOBAL_P4M, (IFX_uint16_t)TANTOS_3G_GSHS_P4M_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_P4M_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_P4M_SIZE}, /* GLOBAL_P5M (# 134) */ { (IFX_uint16_t)GLOBAL_P5M, (IFX_uint16_t)TANTOS_3G_GSHS_P5M_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_P5M_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_P5M_SIZE}, /* GLOBAL_P6M (# 135) */ { (IFX_uint16_t)GLOBAL_P6M, (IFX_uint16_t)TANTOS_3G_GSHS_P6M_OFFSET, (IFX_uint8_t)TANTOS_3G_GSHS_P6M_SHIFT, (IFX_uint8_t)TANTOS_3G_GSHS_P6M_SIZE}, /* GLOBAL_PCE (# 136) */ { (IFX_uint16_t)GLOBAL_PCE, (IFX_uint16_t)TANTOS_3G_SGC2_PCE_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_PCE_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_PCE_SIZE}, /* GLOBAL_PCR (# 137) */ { (IFX_uint16_t)GLOBAL_PCR, (IFX_uint16_t)TANTOS_3G_SGC2_PCR_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_PCR_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_PCR_SIZE}, /* GLOBAL_PHYBA (# 138) */ { (IFX_uint16_t)GLOBAL_PHYBA, (IFX_uint16_t)TANTOS_3G_SGC1_PHYBA_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_PHYBA_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_PHYBA_SIZE}, /* GLOBAL_RVID0 (# 139) */ { (IFX_uint16_t)GLOBAL_RVID0, (IFX_uint16_t)TANTOS_3G_SGC2_RVID0_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_RVID0_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_RVID0_SIZE}, /* GLOBAL_RVID1 (# 140) */ { (IFX_uint16_t)GLOBAL_RVID1, (IFX_uint16_t)TANTOS_3G_SGC2_RVID1_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_RVID1_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_RVID1_SIZE}, /* GLOBAL_RVIDFFF (# 141) */ { (IFX_uint16_t)GLOBAL_RVIDFFF, (IFX_uint16_t)TANTOS_3G_SGC2_RVIDFFF_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_RVIDFFF_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_RVIDFFF_SIZE}, /* GLOBAL_SE (# 142) */ { (IFX_uint16_t)GLOBAL_SE, (IFX_uint16_t)TANTOS_3G_SGC2_SE_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC2_SE_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC2_SE_SIZE}, /* GLOBAL_TSIPGE (# 143) */ { (IFX_uint16_t)GLOBAL_TSIPGE, (IFX_uint16_t)TANTOS_3G_SGC1_TSIPGE_OFFSET, (IFX_uint8_t)TANTOS_3G_SGC1_TSIPGE_SHIFT, (IFX_uint8_t)TANTOS_3G_SGC1_TSIPGE_SIZE}, /* INGRESS_FLOW_CTRL_B (# 144) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* INGRESS_FLOW_CTRL_BASE15_0 (# 145) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_BASE15_0, (IFX_uint16_t)TANTOS_3G_GBSBC_BASE15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_GBSBC_BASE15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_GBSBC_BASE15_0_SIZE}, /* INGRESS_FLOW_CTRL_BASE17_16 (# 146) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_BASE17_16, (IFX_uint16_t)TANTOS_3G_GBSCHB_BASE17_16_OFFSET, (IFX_uint8_t)TANTOS_3G_GBSCHB_BASE17_16_SHIFT, (IFX_uint8_t)TANTOS_3G_GBSCHB_BASE17_16_SIZE}, /* INGRESS_FLOW_CTRL_EBASE15_0 (# 147) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_EBASE15_0, (IFX_uint16_t)TANTOS_3G_GBSEBC_EBASE15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_GBSEBC_EBASE15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_GBSEBC_EBASE15_0_SIZE}, /* INGRESS_FLOW_CTRL_EBASE17_16 (# 148) */ { (IFX_uint16_t)INGRESS_FLOW_CTRL_EBASE17_16, (IFX_uint16_t)TANTOS_3G_GBSCHB_EBASE17_16_OFFSET, (IFX_uint8_t)TANTOS_3G_GBSCHB_EBASE17_16_SHIFT, (IFX_uint8_t)TANTOS_3G_GBSCHB_EBASE17_16_SIZE}, /* INGRESS_FLOW_CTRL_F (# 149) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_DBF (# 150) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_DBFIE (# 151) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_DBNF (# 152) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_DBNFIE (# 153) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_LTAD (# 154) */ { (IFX_uint16_t)IRQ_LTAD, (IFX_uint16_t)TANTOS_3G_IS_LTAD_OFFSET, (IFX_uint8_t)TANTOS_3G_IS_LTAD_SHIFT, (IFX_uint8_t)TANTOS_3G_IS_LTAD_SIZE}, /* IRQ_LTADIE (# 155) */ { (IFX_uint16_t)IRQ_LTADIE, (IFX_uint16_t)TANTOS_3G_IE_LTADIE_OFFSET, (IFX_uint8_t)TANTOS_3G_IE_LTADIE_SHIFT, (IFX_uint8_t)TANTOS_3G_IE_LTADIE_SIZE}, /* IRQ_LTF (# 156) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_LTFIE (# 157) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* IRQ_PSC (# 158) */ { (IFX_uint16_t)IRQ_PSC, (IFX_uint16_t)TANTOS_3G_IS_PSC_OFFSET, (IFX_uint8_t)TANTOS_3G_IS_PSC_SHIFT, (IFX_uint8_t)TANTOS_3G_IS_PSC_SIZE}, /* IRQ_PSCIE (# 159) */ { (IFX_uint16_t)IRQ_PSCIE, (IFX_uint16_t)TANTOS_3G_IE_PSCIE_OFFSET, (IFX_uint8_t)TANTOS_3G_IE_PSCIE_SHIFT, (IFX_uint8_t)TANTOS_3G_IE_PSCIE_SIZE}, /* IRQ_PSV (# 160) */ { (IFX_uint16_t)IRQ_PSV, (IFX_uint16_t)TANTOS_3G_IS_PSV_OFFSET, (IFX_uint8_t)TANTOS_3G_IS_PSV_SHIFT, (IFX_uint8_t)TANTOS_3G_IS_PSV_SIZE}, /* IRQ_PSVIE (# 161) */ { (IFX_uint16_t)IRQ_PSVIE, (IFX_uint16_t)TANTOS_3G_IE_PSVIE_OFFSET, (IFX_uint8_t)TANTOS_3G_IE_PSVIE_SHIFT, (IFX_uint8_t)TANTOS_3G_IE_PSVIE_SIZE}, /* MAC_TABLE_ADDR15_0 (# 162) */ { (IFX_uint16_t)MAC_TABLE_ADDR15_0, (IFX_uint16_t)TANTOS_3G_ATC0_ADDR15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC0_ADDR15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC0_ADDR15_0_SIZE}, /* MAC_TABLE_ADDR31_0 (# 163) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDR31_16 (# 164) */ { (IFX_uint16_t)MAC_TABLE_ADDR31_16, (IFX_uint16_t)TANTOS_3G_ATC1_ADDR31_16_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC1_ADDR31_16_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC1_ADDR31_16_SIZE}, /* MAC_TABLE_ADDR47_32 (# 165) */ { (IFX_uint16_t)MAC_TABLE_ADDR47_32, (IFX_uint16_t)TANTOS_3G_ATC2_ADDR47_32_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC2_ADDR47_32_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC2_ADDR47_32_SIZE}, /* MAC_TABLE_ADDRS15_0 (# 166) */ { (IFX_uint16_t)MAC_TABLE_ADDRS15_0, (IFX_uint16_t)TANTOS_3G_ATS0_ADDRS15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS0_ADDRS15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS0_ADDRS15_0_SIZE}, /* MAC_TABLE_ADDRS31_0 (# 167) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* MAC_TABLE_ADDRS31_16 (# 168) */ { (IFX_uint16_t)MAC_TABLE_ADDRS31_16, (IFX_uint16_t)TANTOS_3G_ATS1_ADDRS31_16_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS1_ADDRS31_16_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS1_ADDRS31_16_SIZE}, /* MAC_TABLE_ADDRS47_32 (# 169) */ { (IFX_uint16_t)MAC_TABLE_ADDRS47_32, (IFX_uint16_t)TANTOS_3G_ATS2_ADDRS47_32_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS2_ADDRS47_32_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS2_ADDRS47_32_SIZE}, /* MAC_TABLE_BAD (# 170) */ { (IFX_uint16_t)MAC_TABLE_BAD, (IFX_uint16_t)TANTOS_3G_ATS4_BAD_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS4_BAD_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS4_BAD_SIZE}, /* MAC_TABLE_BUSY (# 171) */ { (IFX_uint16_t)MAC_TABLE_BUSY, (IFX_uint16_t)TANTOS_3G_ATS5_BUSY_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS5_BUSY_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS5_BUSY_SIZE}, /* MAC_TABLE_C_AC (# 172) */ { (IFX_uint16_t)MAC_TABLE_C_AC, (IFX_uint16_t)TANTOS_3G_ATC5_AC_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC5_AC_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC5_AC_SIZE}, /* MAC_TABLE_C_CMD (# 173) */ { (IFX_uint16_t)MAC_TABLE_C_CMD, (IFX_uint16_t)TANTOS_3G_ATC5_CMD_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC5_CMD_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC5_CMD_SIZE}, /* MAC_TABLE_C_FCE (# 174) */ { (IFX_uint16_t)MAC_TABLE_C_FCE, (IFX_uint16_t)TANTOS_3G_ATC5_FCE_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC5_FCE_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC5_FCE_SIZE}, /* MAC_TABLE_FID (# 175) */ { (IFX_uint16_t)MAC_TABLE_FID, (IFX_uint16_t)TANTOS_3G_ATC3_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC3_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC3_FID_SIZE}, /* MAC_TABLE_FIDS (# 176) */ { (IFX_uint16_t)MAC_TABLE_FIDS, (IFX_uint16_t)TANTOS_3G_ATS3_FIDS_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS3_FIDS_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS3_FIDS_SIZE}, /* MAC_TABLE_INFOT (# 177) */ { (IFX_uint16_t)MAC_TABLE_INFOT, (IFX_uint16_t)TANTOS_3G_ATC4_INFOT_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC4_INFOT_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC4_INFOT_SIZE}, /* MAC_TABLE_INFOTS (# 178) */ { (IFX_uint16_t)MAC_TABLE_INFOTS, (IFX_uint16_t)TANTOS_3G_ATS4_INFOTS_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS4_INFOTS_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS4_INFOTS_SIZE}, /* MAC_TABLE_ITAT (# 179) */ { (IFX_uint16_t)MAC_TABLE_ITAT, (IFX_uint16_t)TANTOS_3G_ATC4_ITAT_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC4_ITAT_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC4_ITAT_SIZE}, /* MAC_TABLE_ITATS (# 180) */ { (IFX_uint16_t)MAC_TABLE_ITATS, (IFX_uint16_t)TANTOS_3G_ATS4_ITATS_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS4_ITATS_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS4_ITATS_SIZE}, /* MAC_TABLE_OCP (# 181) */ { (IFX_uint16_t)MAC_TABLE_OCP, (IFX_uint16_t)TANTOS_3G_ATS4_OCP_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS4_OCP_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS4_OCP_SIZE}, /* MAC_TABLE_PMAP (# 182) */ { (IFX_uint16_t)MAC_TABLE_PMAP, (IFX_uint16_t)TANTOS_3G_ATC3_PMAP_OFFSET, (IFX_uint8_t)TANTOS_3G_ATC3_PMAP_SHIFT, (IFX_uint8_t)TANTOS_3G_ATC3_PMAP_SIZE}, /* MAC_TABLE_PMAPS (# 183) */ { (IFX_uint16_t)MAC_TABLE_PMAPS, (IFX_uint16_t)TANTOS_3G_ATS3_PMAPS_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS3_PMAPS_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS3_PMAPS_SIZE}, /* MAC_TABLE_RSLT (# 184) */ { (IFX_uint16_t)MAC_TABLE_RSLT, (IFX_uint16_t)TANTOS_3G_ATS5_RSLT_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS5_RSLT_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS5_RSLT_SIZE}, /* MAC_TABLE_S_AC (# 185) */ { (IFX_uint16_t)MAC_TABLE_S_AC, (IFX_uint16_t)TANTOS_3G_ATS5_AC_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS5_AC_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS5_AC_SIZE}, /* MAC_TABLE_S_CMD (# 186) */ { (IFX_uint16_t)MAC_TABLE_S_CMD, (IFX_uint16_t)TANTOS_3G_ATS5_CMD_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS5_CMD_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS5_CMD_SIZE}, /* MAC_TABLE_S_FCE (# 187) */ { (IFX_uint16_t)MAC_TABLE_S_FCE, (IFX_uint16_t)TANTOS_3G_ATS5_FCE_OFFSET, (IFX_uint8_t)TANTOS_3G_ATS5_FCE_SHIFT, (IFX_uint8_t)TANTOS_3G_ATS5_FCE_SIZE}, /* MCS (# 188) */ { (IFX_uint16_t)MCS, (IFX_uint16_t)TANTOS_3G_MCSR_MCS_OFFSET, (IFX_uint8_t)TANTOS_3G_MCSR_MCS_SHIFT, (IFX_uint8_t)TANTOS_3G_MCSR_MCS_SIZE}, /* MDIO_MBUSY (# 189) */ { (IFX_uint16_t)MDIO_MBUSY, (IFX_uint16_t)TANTOS_3G_MIIAC_MBUSY_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIAC_MBUSY_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIAC_MBUSY_SIZE}, /* MDIO_OP (# 190) */ { (IFX_uint16_t)MDIO_OP, (IFX_uint16_t)TANTOS_3G_MIIAC_OP_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIAC_OP_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIAC_OP_SIZE}, /* MDIO_PHYAD (# 191) */ { (IFX_uint16_t)MDIO_PHYAD, (IFX_uint16_t)TANTOS_3G_MIIAC_PHYAD_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIAC_PHYAD_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIAC_PHYAD_SIZE}, /* MDIO_RD (# 192) */ { (IFX_uint16_t)MDIO_RD, (IFX_uint16_t)TANTOS_3G_MIIRD_RD_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIRD_RD_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIRD_RD_SIZE}, /* MDIO_REGAD (# 193) */ { (IFX_uint16_t)MDIO_REGAD, (IFX_uint16_t)TANTOS_3G_MIIAC_REGAD_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIAC_REGAD_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIAC_REGAD_SIZE}, /* MDIO_WD (# 194) */ { (IFX_uint16_t)MDIO_WD, (IFX_uint16_t)TANTOS_3G_MIIWD_WD_OFFSET, (IFX_uint8_t)TANTOS_3G_MIIWD_WD_SHIFT, (IFX_uint8_t)TANTOS_3G_MIIWD_WD_SIZE}, /* MIRROR_CCCRC (# 195) */ { (IFX_uint16_t)MIRROR_CCCRC, (IFX_uint16_t)TANTOS_3G_CMH_CCCRC_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_CCCRC_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_CCCRC_SIZE}, /* MIRROR_CPN (# 196) */ { (IFX_uint16_t)MIRROR_CPN, (IFX_uint16_t)TANTOS_3G_CMH_CPN_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_CPN_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_CPN_SIZE}, /* MIRROR_IGSTA (# 197) */ { (IFX_uint16_t)MIRROR_IGSTA, (IFX_uint16_t)TANTOS_3G_CMH_IGSTA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_IGSTA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_IGSTA_SIZE}, /* MIRROR_MCA (# 198) */ { (IFX_uint16_t)MIRROR_MCA, (IFX_uint16_t)TANTOS_3G_CMH_MCA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_MCA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_MCA_SIZE}, /* MIRROR_MLA (# 199) */ { (IFX_uint16_t)MIRROR_MLA, (IFX_uint16_t)TANTOS_3G_CMH_MLA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_MLA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_MLA_SIZE}, /* MIRROR_MPA (# 200) */ { (IFX_uint16_t)MIRROR_MPA, (IFX_uint16_t)TANTOS_3G_CMH_MPA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_MPA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_MPA_SIZE}, /* MIRROR_MRA (# 201) */ { (IFX_uint16_t)MIRROR_MRA, (IFX_uint16_t)TANTOS_3G_CMH_MRA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_MRA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_MRA_SIZE}, /* MIRROR_MSA (# 202) */ { (IFX_uint16_t)MIRROR_MSA, (IFX_uint16_t)TANTOS_3G_CMH_MSA_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_MSA_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_MSA_SIZE}, /* MIRROR_PAST (# 203) */ { (IFX_uint16_t)MIRROR_PAST, (IFX_uint16_t)TANTOS_3G_CMH_PAST_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_PAST_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_PAST_SIZE}, /* MIRROR_SNIFFPN (# 204) */ { (IFX_uint16_t)MIRROR_SNIFFPN, (IFX_uint16_t)TANTOS_3G_CMH_SPN_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_SPN_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_SPN_SIZE}, /* MIRROR_STRE (# 205) */ { (IFX_uint16_t)MIRROR_STRE, (IFX_uint16_t)TANTOS_3G_CMH_STRE_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_STRE_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_STRE_SIZE}, /* MIRROR_STTE (# 206) */ { (IFX_uint16_t)MIRROR_STTE, (IFX_uint16_t)TANTOS_3G_CMH_STTE_OFFSET, (IFX_uint8_t)TANTOS_3G_CMH_STTE_SHIFT, (IFX_uint8_t)TANTOS_3G_CMH_STTE_SIZE}, /* MULTICAST_ASC (# 207) */ { (IFX_uint16_t)MULTICAST_ASC, (IFX_uint16_t)TANTOS_3G_MS_ASC_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_ASC_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_ASC_SIZE}, /* MULTICAST_B01 (# 208) */ { (IFX_uint16_t)MULTICAST_B01, (IFX_uint16_t)TANTOS_3G_HIOR_B01_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_B01_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_B01_SIZE}, /* MULTICAST_B224 (# 209) */ { (IFX_uint16_t)MULTICAST_B224, (IFX_uint16_t)TANTOS_3G_HIOR_B224_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_B224_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_B224_SIZE}, /* MULTICAST_B33 (# 210) */ { (IFX_uint16_t)MULTICAST_B33, (IFX_uint16_t)TANTOS_3G_HIOR_B33_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_B33_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_B33_SIZE}, /* MULTICAST_DAIPS (# 211) */ { (IFX_uint16_t)MULTICAST_DAIPS, (IFX_uint16_t)TANTOS_3G_HIOR_DAIPS_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_DAIPS_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_DAIPS_SIZE}, /* MULTICAST_DRP (# 212) */ { (IFX_uint16_t)MULTICAST_DRP, (IFX_uint16_t)TANTOS_3G_HIC_DRP_OFFSET, (IFX_uint8_t)TANTOS_3G_HIC_DRP_SHIFT, (IFX_uint8_t)TANTOS_3G_HIC_DRP_SIZE}, /* MULTICAST_FMODE (# 213) */ { (IFX_uint16_t)MULTICAST_FMODE, (IFX_uint16_t)TANTOS_3G_IGMPTC5_FMODE_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC5_FMODE_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC5_FMODE_SIZE}, /* MULTICAST_GID15_0 (# 214) */ { (IFX_uint16_t)MULTICAST_GID15_0, (IFX_uint16_t)TANTOS_3G_IGMPTC3_GID15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC3_GID15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC3_GID15_0_SIZE}, /* MULTICAST_GID31_16 (# 215) */ { (IFX_uint16_t)MULTICAST_GID31_16, (IFX_uint16_t)TANTOS_3G_IGMPTC4_GID31_16_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC4_GID31_16_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC4_GID31_16_SIZE}, /* MULTICAST_HIPI (# 216) */ { (IFX_uint16_t)MULTICAST_HIPI, (IFX_uint16_t)TANTOS_3G_HIC_HIPI_OFFSET, (IFX_uint8_t)TANTOS_3G_HIC_HIPI_SHIFT, (IFX_uint8_t)TANTOS_3G_HIC_HIPI_SIZE}, /* MULTICAST_HISE (# 217) */ { (IFX_uint16_t)MULTICAST_HISE, (IFX_uint16_t)TANTOS_3G_HIOR_HISE_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_HISE_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_HISE_SIZE}, /* MULTICAST_HISFL (# 218) */ { (IFX_uint16_t)MULTICAST_HISFL, (IFX_uint16_t)TANTOS_3G_HIOR_HISFL_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_HISFL_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_HISFL_SIZE}, /* MULTICAST_ICMD (# 219) */ { (IFX_uint16_t)MULTICAST_ICMD, (IFX_uint16_t)TANTOS_3G_IGMPTC5_ICMD_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC5_ICMD_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC5_ICMD_SIZE}, /* MULTICAST_IGMPV3E (# 220) */ { (IFX_uint16_t)MULTICAST_IGMPV3E, (IFX_uint16_t)TANTOS_3G_HIOR_IGMPV3E_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_IGMPV3E_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_IGMPV3E_SIZE}, /* MULTICAST_INVC (# 221) */ { (IFX_uint16_t)MULTICAST_INVC, (IFX_uint16_t)TANTOS_3G_IGMPTC5_INVC_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC5_INVC_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC5_INVC_SIZE}, /* MULTICAST_IPMPT (# 222) */ { (IFX_uint16_t)MULTICAST_IPMPT, (IFX_uint16_t)TANTOS_3G_MS_IPMPT_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_IPMPT_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_IPMPT_SIZE}, /* MULTICAST_PORT (# 223) */ { (IFX_uint16_t)MULTICAST_PORT, (IFX_uint16_t)TANTOS_3G_IGMPTC5_PORT_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC5_PORT_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC5_PORT_SIZE}, /* MULTICAST_PPPOEHR (# 224) */ { (IFX_uint16_t)MULTICAST_PPPOEHR, (IFX_uint16_t)TANTOS_3G_HIOR_PPPOEHR_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_PPPOEHR_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_PPPOEHR_SIZE}, /* MULTICAST_QI (# 225) */ { (IFX_uint16_t)MULTICAST_QI, (IFX_uint16_t)TANTOS_3G_HIC_QI_OFFSET, (IFX_uint8_t)TANTOS_3G_HIC_QI_SHIFT, (IFX_uint8_t)TANTOS_3G_HIC_QI_SIZE}, /* MULTICAST_RV (# 226) */ { (IFX_uint16_t)MULTICAST_RV, (IFX_uint16_t)TANTOS_3G_MS_RV_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_RV_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_RV_SIZE}, /* MULTICAST_S3PMI (# 227) */ { (IFX_uint16_t)MULTICAST_S3PMI, (IFX_uint16_t)TANTOS_3G_IGMPTS3_S3PMI_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS3_S3PMI_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS3_S3PMI_SIZE}, /* MULTICAST_S3PMV (# 228) */ { (IFX_uint16_t)MULTICAST_S3PMV, (IFX_uint16_t)TANTOS_3G_IGMPTS3_S3PMV_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS3_S3PMV_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS3_S3PMV_SIZE}, /* MULTICAST_S4BUSY (# 229) */ { (IFX_uint16_t)MULTICAST_S4BUSY, (IFX_uint16_t)TANTOS_3G_IGMPTS4_S4BUSY_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS4_S4BUSY_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS4_S4BUSY_SIZE}, /* MULTICAST_S4R (# 230) */ { (IFX_uint16_t)MULTICAST_S4R, (IFX_uint16_t)TANTOS_3G_IGMPTS4_S4R_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS4_S4R_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS4_S4R_SIZE}, /* MULTICAST_SARE (# 231) */ { (IFX_uint16_t)MULTICAST_SARE, (IFX_uint16_t)TANTOS_3G_HIOR_SARE_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_SARE_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_SARE_SIZE}, /* MULTICAST_SCPA (# 232) */ { (IFX_uint16_t)MULTICAST_SCPA, (IFX_uint16_t)TANTOS_3G_MS_SCPA_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPA_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPA_SIZE}, /* MULTICAST_SCPP (# 233) */ { (IFX_uint16_t)MULTICAST_SCPP, (IFX_uint16_t)TANTOS_3G_MS_SCPP_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPP_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPP_SIZE}, /* MULTICAST_SCPPE (# 234) */ { (IFX_uint16_t)MULTICAST_SCPPE, (IFX_uint16_t)TANTOS_3G_MS_SCPPE_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPPE_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPPE_SIZE}, /* MULTICAST_SCPTCP (# 235) */ { (IFX_uint16_t)MULTICAST_SCPTCP, (IFX_uint16_t)TANTOS_3G_MS_SCPTCP_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPTCP_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPTCP_SIZE}, /* MULTICAST_SCPTMP (# 236) */ { (IFX_uint16_t)MULTICAST_SCPTMP, (IFX_uint16_t)TANTOS_3G_MS_SCPTMP_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPTMP_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPTMP_SIZE}, /* MULTICAST_SCPTSP (# 237) */ { (IFX_uint16_t)MULTICAST_SCPTSP, (IFX_uint16_t)TANTOS_3G_MS_SCPTSP_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPTSP_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPTSP_SIZE}, /* MULTICAST_SCPTTH (# 238) */ { (IFX_uint16_t)MULTICAST_SCPTTH, (IFX_uint16_t)TANTOS_3G_MS_SCPTTH_OFFSET, (IFX_uint8_t)TANTOS_3G_MS_SCPTTH_SHIFT, (IFX_uint8_t)TANTOS_3G_MS_SCPTTH_SIZE}, /* MULTICAST_SIP15_0 (# 239) */ { (IFX_uint16_t)MULTICAST_SIP15_0, (IFX_uint16_t)TANTOS_3G_IGMPTC0_SIP15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC0_SIP15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC0_SIP15_0_SIZE}, /* MULTICAST_SIP31_16 (# 240) */ { (IFX_uint16_t)MULTICAST_SIP31_16, (IFX_uint16_t)TANTOS_3G_IGMPTC1_SIP31_16_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC1_SIP31_16_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC1_SIP31_16_SIZE}, /* MULTICAST_SIP47_32 (# 241) */ { (IFX_uint16_t)MULTICAST_SIP47_32, (IFX_uint16_t)TANTOS_3G_IGMPTC2_SIP47_32_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTC2_SIP47_32_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTC2_SIP47_32_SIZE}, /* MULTICAST_SIPGID0 (# 242) */ { (IFX_uint16_t)MULTICAST_SIPGID0, (IFX_uint16_t)TANTOS_3G_IGMPTS0_SIPGID0_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS0_SIPGID0_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS0_SIPGID0_SIZE}, /* MULTICAST_SIPGID1 (# 243) */ { (IFX_uint16_t)MULTICAST_SIPGID1, (IFX_uint16_t)TANTOS_3G_IGMPTS1_SIPGID1_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS1_SIPGID1_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS1_SIPGID1_SIZE}, /* MULTICAST_SIPGID2 (# 244) */ { (IFX_uint16_t)MULTICAST_SIPGID2, (IFX_uint16_t)TANTOS_3G_IGMPTS2_SIPGID2_OFFSET, (IFX_uint8_t)TANTOS_3G_IGMPTS2_SIPGID2_SHIFT, (IFX_uint8_t)TANTOS_3G_IGMPTS2_SIPGID2_SIZE}, /* MULTICAST_TIMERC (# 245) */ { (IFX_uint16_t)MULTICAST_TIMERC, (IFX_uint16_t)TANTOS_3G_HIOR_TIMERC_OFFSET, (IFX_uint8_t)TANTOS_3G_HIOR_TIMERC_SHIFT, (IFX_uint8_t)TANTOS_3G_HIOR_TIMERC_SIZE}, /* PAUSE_ADDR15_0 (# 246) */ { (IFX_uint16_t)PAUSE_ADDR15_0, (IFX_uint16_t)TANTOS_3G_SMA3_ADDR15_0_OFFSET, (IFX_uint8_t)TANTOS_3G_SMA3_ADDR15_0_SHIFT, (IFX_uint8_t)TANTOS_3G_SMA3_ADDR15_0_SIZE}, /* PAUSE_ADDR31_16 (# 247) */ { (IFX_uint16_t)PAUSE_ADDR31_16, (IFX_uint16_t)TANTOS_3G_SMA2_ADDR31_16_OFFSET, (IFX_uint8_t)TANTOS_3G_SMA2_ADDR31_16_SHIFT, (IFX_uint8_t)TANTOS_3G_SMA2_ADDR31_16_SIZE}, /* PAUSE_ADDR39_32 (# 248) */ { (IFX_uint16_t)PAUSE_ADDR39_32, (IFX_uint16_t)TANTOS_3G_SMA1_ADDR39_32_OFFSET, (IFX_uint8_t)TANTOS_3G_SMA1_ADDR39_32_SHIFT, (IFX_uint8_t)TANTOS_3G_SMA1_ADDR39_32_SIZE}, /* PAUSE_ADDR47_41 (# 249) */ { (IFX_uint16_t)PAUSE_ADDR47_41, (IFX_uint16_t)TANTOS_3G_SMA1_ADDR47_41_OFFSET, (IFX_uint8_t)TANTOS_3G_SMA1_ADDR47_41_SHIFT, (IFX_uint8_t)TANTOS_3G_SMA1_ADDR47_41_SIZE}, /* PAUSE_PAC (# 250) */ { (IFX_uint16_t)PAUSE_PAC, (IFX_uint16_t)TANTOS_3G_SMA1_PAC_OFFSET, (IFX_uint8_t)TANTOS_3G_SMA1_PAC_SHIFT, (IFX_uint8_t)TANTOS_3G_SMA1_PAC_SIZE}, /* PHY_INIT_PHYIE0 (# 251) */ { (IFX_uint16_t)PHY_INIT_PHYIE0, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE0_SIZE}, /* PHY_INIT_PHYIE01 (# 252) */ { (IFX_uint16_t)PHY_INIT_PHYIE0, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE0_SIZE}, /* PHY_INIT_PHYIE02 (# 253) */ { (IFX_uint16_t)PHY_INIT_PHYIE0, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE0_SIZE}, /* PHY_INIT_PHYIE03 (# 254) */ { (IFX_uint16_t)PHY_INIT_PHYIE0, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE0_SIZE}, /* PHY_INIT_PHYIE1 (# 255) */ { (IFX_uint16_t)PHY_INIT_PHYIE1, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE1_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE1_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE1_SIZE}, /* PHY_INIT_PHYIE11 (# 256) */ { (IFX_uint16_t)PHY_INIT_PHYIE1, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE1_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE1_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE1_SIZE}, /* PHY_INIT_PHYIE12 (# 257) */ { (IFX_uint16_t)PHY_INIT_PHYIE1, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE1_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE1_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE1_SIZE}, /* PHY_INIT_PHYIE13 (# 258) */ { (IFX_uint16_t)PHY_INIT_PHYIE1, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE1_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE1_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE1_SIZE}, /* PHY_INIT_PHYIE2 (# 259) */ { (IFX_uint16_t)PHY_INIT_PHYIE2, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE2_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE2_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE2_SIZE}, /* PHY_INIT_PHYIE21 (# 260) */ { (IFX_uint16_t)PHY_INIT_PHYIE2, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE2_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE2_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE2_SIZE}, /* PHY_INIT_PHYIE22 (# 261) */ { (IFX_uint16_t)PHY_INIT_PHYIE2, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE2_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE2_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE2_SIZE}, /* PHY_INIT_PHYIE23 (# 262) */ { (IFX_uint16_t)PHY_INIT_PHYIE2, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE2_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE2_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE2_SIZE}, /* PHY_INIT_PHYIE3 (# 263) */ { (IFX_uint16_t)PHY_INIT_PHYIE3, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE3_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE3_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE3_SIZE}, /* PHY_INIT_PHYIE31 (# 264) */ { (IFX_uint16_t)PHY_INIT_PHYIE3, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE3_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE3_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE3_SIZE}, /* PHY_INIT_PHYIE32 (# 265) */ { (IFX_uint16_t)PHY_INIT_PHYIE3, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE3_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE3_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE3_SIZE}, /* PHY_INIT_PHYIE33 (# 266) */ { (IFX_uint16_t)PHY_INIT_PHYIE3, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE3_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE3_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE3_SIZE}, /* PHY_INIT_PHYIE4 (# 267) */ { (IFX_uint16_t)PHY_INIT_PHYIE4, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE4_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE4_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE4_SIZE}, /* PHY_INIT_PHYIE41 (# 268) */ { (IFX_uint16_t)PHY_INIT_PHYIE4, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE4_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE4_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE4_SIZE}, /* PHY_INIT_PHYIE42 (# 269) */ { (IFX_uint16_t)PHY_INIT_PHYIE4, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE4_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE4_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE4_SIZE}, /* PHY_INIT_PHYIE43 (# 270) */ { (IFX_uint16_t)PHY_INIT_PHYIE4, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE4_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE4_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE4_SIZE}, /* PHY_INIT_PHYIE5 (# 271) */ { (IFX_uint16_t)PHY_INIT_PHYIE5, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE5_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE5_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE5_SIZE}, /* PHY_INIT_PHYIE51 (# 272) */ { (IFX_uint16_t)PHY_INIT_PHYIE5, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE5_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE5_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE5_SIZE}, /* PHY_INIT_PHYIE52 (# 273) */ { (IFX_uint16_t)PHY_INIT_PHYIE5, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE5_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE5_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE5_SIZE}, /* PHY_INIT_PHYIE53 (# 274) */ { (IFX_uint16_t)PHY_INIT_PHYIE5, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE5_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE5_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE5_SIZE}, /* PHY_INIT_PHYIE6 (# 275) */ { (IFX_uint16_t)PHY_INIT_PHYIE6, (IFX_uint16_t)TANTOS_3G_PHYIC0_PHYIE6_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE6_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_PHYIE6_SIZE}, /* PHY_INIT_PHYIE61 (# 276) */ { (IFX_uint16_t)PHY_INIT_PHYIE6, (IFX_uint16_t)TANTOS_3G_PHYIC1_PHYIE6_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE6_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_PHYIE6_SIZE}, /* PHY_INIT_PHYIE62 (# 277) */ { (IFX_uint16_t)PHY_INIT_PHYIE6, (IFX_uint16_t)TANTOS_3G_PHYIC2_PHYIE6_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE6_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_PHYIE6_SIZE}, /* PHY_INIT_PHYIE63 (# 278) */ { (IFX_uint16_t)PHY_INIT_PHYIE6, (IFX_uint16_t)TANTOS_3G_PHYIC3_PHYIE6_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE6_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_PHYIE6_SIZE}, /* PHY_INIT_REGA (# 279) */ { (IFX_uint16_t)PHY_INIT_REGA, (IFX_uint16_t)TANTOS_3G_PHYIC0_REGA0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC0_REGA0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC0_REGA0_SIZE}, /* PHY_INIT_REGA1 (# 280) */ { (IFX_uint16_t)PHY_INIT_REGA, (IFX_uint16_t)TANTOS_3G_PHYIC1_REGA0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC1_REGA0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC1_REGA0_SIZE}, /* PHY_INIT_REGA2 (# 281) */ { (IFX_uint16_t)PHY_INIT_REGA, (IFX_uint16_t)TANTOS_3G_PHYIC2_REGA0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC2_REGA0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC2_REGA0_SIZE}, /* PHY_INIT_REGA3 (# 282) */ { (IFX_uint16_t)PHY_INIT_REGA, (IFX_uint16_t)TANTOS_3G_PHYIC3_REGA0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYIC3_REGA0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYIC3_REGA0_SIZE}, /* PHY_INIT_REGD (# 283) */ { (IFX_uint16_t)PHY_INIT_REGD, (IFX_uint16_t)TANTOS_3G_PHYID0_REGD0_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYID0_REGD0_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYID0_REGD0_SIZE}, /* PHY_INIT_REGD1 (# 284) */ { (IFX_uint16_t)PHY_INIT_REGD, (IFX_uint16_t)TANTOS_3G_PHYID1_REGD1_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYID1_REGD1_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYID1_REGD1_SIZE}, /* PHY_INIT_REGD2 (# 285) */ { (IFX_uint16_t)PHY_INIT_REGD, (IFX_uint16_t)TANTOS_3G_PHYID2_REGD2_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYID2_REGD2_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYID2_REGD2_SIZE}, /* PHY_INIT_REGD3 (# 286) */ { (IFX_uint16_t)PHY_INIT_REGD, (IFX_uint16_t)TANTOS_3G_PHYID3_REGD3_OFFSET, (IFX_uint8_t)TANTOS_3G_PHYID3_REGD3_SHIFT, (IFX_uint8_t)TANTOS_3G_PHYID3_REGD3_SIZE}, /* PMAC_ADD (# 287) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_ADD_CRC (# 288) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_AS (# 289) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_CFI (# 290) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_DA_31_0 (# 291) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_DA_47_32 (# 292) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_IDIS_REQ_WM (# 293) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_IPG_RX_CNT (# 294) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_IPG_TX_CNT (# 295) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_IREQ_WM (# 296) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_PRI (# 297) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_RC (# 298) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_RL2 (# 299) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_RXSH (# 300) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_SA_31_0 (# 301) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_SA_47_32 (# 302) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_TAG (# 303) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_TYPE_LEN (# 304) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PMAC_VLAN ID (# 305) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_AD (# 306) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P0EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_AD_SIZE}, /* PORT_AD1 (# 307) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P1EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_AD_SIZE}, /* PORT_AD2 (# 308) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P2EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_AD_SIZE}, /* PORT_AD3 (# 309) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P3EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_AD_SIZE}, /* PORT_AD4 (# 310) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P4EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_AD_SIZE}, /* PORT_AD5 (# 311) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P5EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_AD_SIZE}, /* PORT_AD6 (# 312) */ { (IFX_uint16_t)PORT_AD, (IFX_uint16_t)TANTOS_3G_P6EC_AD_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_AD_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_AD_SIZE}, /* PORT_BP (# 313) */ { (IFX_uint16_t)PORT_BP, (IFX_uint16_t)TANTOS_3G_UPMBPM_BP_OFFSET, (IFX_uint8_t)TANTOS_3G_UPMBPM_BP_SHIFT, (IFX_uint8_t)TANTOS_3G_UPMBPM_BP_SIZE}, /* PORT_DFWD (# 314) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_DFWD1 (# 315) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_DFWD2 (# 316) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_DSV821X (# 317) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_DSV821X1 (# 318) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_DSV821X2 (# 319) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_EGRESS_PSPQ0TR (# 320) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P0ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR1 (# 321) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P1ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR2 (# 322) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P2ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR3 (# 323) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P3ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR4 (# 324) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P4ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR5 (# 325) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P5ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ0TR6 (# 326) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ0TR, (IFX_uint16_t)TANTOS_3G_P6ECSQ0_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECSQ0_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECSQ0_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR (# 327) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P0ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR1 (# 328) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P1ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR2 (# 329) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P2ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR3 (# 330) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P3ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR4 (# 331) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P4ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR5 (# 332) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P5ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ1TR6 (# 333) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ1TR, (IFX_uint16_t)TANTOS_3G_P6ECSQ1_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECSQ1_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECSQ1_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR (# 334) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P0ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR1 (# 335) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P1ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR2 (# 336) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P2ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR3 (# 337) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P3ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR4 (# 338) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P4ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR5 (# 339) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P5ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ2TR6 (# 340) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ2TR, (IFX_uint16_t)TANTOS_3G_P6ECSQ2_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECSQ2_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECSQ2_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR (# 341) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P0ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR1 (# 342) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P1ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR2 (# 343) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P2ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR3 (# 344) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P3ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR4 (# 345) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P4ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR5 (# 346) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P5ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PSPQ3TR6 (# 347) */ { (IFX_uint16_t)PORT_EGRESS_PSPQ3TR, (IFX_uint16_t)TANTOS_3G_P6ECSQ3_P0SPQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECSQ3_P0SPQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECSQ3_P0SPQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR (# 348) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P0ECWQ0_P0WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECWQ0_P0WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECWQ0_P0WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR1 (# 349) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P1ECWQ0_P22WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECWQ0_P22WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECWQ0_P22WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR2 (# 350) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P2ECWQ0_P23WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECWQ0_P23WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECWQ0_P23WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR3 (# 351) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P3ECWQ0_P24WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECWQ0_P24WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECWQ0_P24WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR4 (# 352) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P4ECWQ0_P25WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECWQ0_P25WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECWQ0_P25WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR5 (# 353) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P5ECWQ0_P26WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECWQ0_P26WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECWQ0_P26WQ3TR_SIZE}, /* PORT_EGRESS_PWQ0TR6 (# 354) */ { (IFX_uint16_t)PORT_EGRESS_PWQ0TR, (IFX_uint16_t)TANTOS_3G_P6ECWQ0_P27WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECWQ0_P27WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECWQ0_P27WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR (# 355) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P0ECWQ1_P0WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECWQ1_P0WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECWQ1_P0WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR1 (# 356) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P1ECWQ1_P15WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECWQ1_P15WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECWQ1_P15WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR2 (# 357) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P2ECWQ1_P16WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECWQ1_P16WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECWQ1_P16WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR3 (# 358) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P3ECWQ1_P17WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECWQ1_P17WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECWQ1_P17WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR4 (# 359) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P4ECWQ1_P18WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECWQ1_P18WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECWQ1_P18WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR5 (# 360) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P5ECWQ1_P19WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECWQ1_P19WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECWQ1_P19WQ3TR_SIZE}, /* PORT_EGRESS_PWQ1TR6 (# 361) */ { (IFX_uint16_t)PORT_EGRESS_PWQ1TR, (IFX_uint16_t)TANTOS_3G_P6ECWQ1_P20WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECWQ1_P20WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECWQ1_P20WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR (# 362) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P0ECWQ2_P0WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECWQ2_P0WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECWQ2_P0WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR1 (# 363) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P1ECWQ2_P8WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECWQ2_P8WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECWQ2_P8WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR2 (# 364) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P2ECWQ2_P9WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECWQ2_P9WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECWQ2_P9WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR3 (# 365) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P3ECWQ2_P10WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECWQ2_P10WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECWQ2_P10WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR4 (# 366) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P4ECWQ2_P11WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECWQ2_P11WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECWQ2_P11WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR5 (# 367) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P5ECWQ2_P12WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECWQ2_P12WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECWQ2_P12WQ3TR_SIZE}, /* PORT_EGRESS_PWQ2TR6 (# 368) */ { (IFX_uint16_t)PORT_EGRESS_PWQ2TR, (IFX_uint16_t)TANTOS_3G_P6ECWQ2_P13WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECWQ2_P13WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECWQ2_P13WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR (# 369) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P0ECWQ3_P0WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ECWQ3_P0WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ECWQ3_P0WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR1 (# 370) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P1ECWQ3_P1WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ECWQ3_P1WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ECWQ3_P1WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR2 (# 371) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P2ECWQ3_P2WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ECWQ3_P2WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ECWQ3_P2WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR3 (# 372) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P3ECWQ3_P3WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ECWQ3_P3WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ECWQ3_P3WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR4 (# 373) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P4ECWQ3_P4WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ECWQ3_P4WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ECWQ3_P4WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR5 (# 374) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P5ECWQ3_P5WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ECWQ3_P5WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ECWQ3_P5WQ3TR_SIZE}, /* PORT_EGRESS_PWQ3TR6 (# 375) */ { (IFX_uint16_t)PORT_EGRESS_PWQ3TR, (IFX_uint16_t)TANTOS_3G_P6ECWQ3_P6WQ3TR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ECWQ3_P6WQ3TR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ECWQ3_P6WQ3TR_SIZE}, /* PORT_FILTER_ATUF (# 376) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR0_ATUF0_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR0_ATUF0_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR0_ATUF0_SIZE}, /* PORT_FILTER_ATUF1 (# 377) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR1_ATUF1_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR1_ATUF1_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR1_ATUF1_SIZE}, /* PORT_FILTER_ATUF2 (# 378) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR2_ATUF2_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR2_ATUF2_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR2_ATUF2_SIZE}, /* PORT_FILTER_ATUF3 (# 379) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR3_ATUF3_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR3_ATUF3_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR3_ATUF3_SIZE}, /* PORT_FILTER_ATUF4 (# 380) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR4_ATUF4_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR4_ATUF4_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR4_ATUF4_SIZE}, /* PORT_FILTER_ATUF5 (# 381) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR5_ATUF5_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR5_ATUF5_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR5_ATUF5_SIZE}, /* PORT_FILTER_ATUF6 (# 382) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR6_ATUF6_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR6_ATUF6_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR6_ATUF6_SIZE}, /* PORT_FILTER_ATUF7 (# 383) */ { (IFX_uint16_t)PORT_FILTER_ATUF, (IFX_uint16_t)TANTOS_3G_TUPR7_ATUF7_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR7_ATUF7_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR7_ATUF7_SIZE}, /* PORT_FILTER_BASEPT (# 384) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF0_BASEPT0_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF0_BASEPT0_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF0_BASEPT0_SIZE}, /* PORT_FILTER_BASEPT1 (# 385) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF1_BASEPT1_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF1_BASEPT1_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF1_BASEPT1_SIZE}, /* PORT_FILTER_BASEPT2 (# 386) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF2_BASEPT2_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF2_BASEPT2_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF2_BASEPT2_SIZE}, /* PORT_FILTER_BASEPT3 (# 387) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF3_BASEPT3_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF3_BASEPT3_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF3_BASEPT3_SIZE}, /* PORT_FILTER_BASEPT4 (# 388) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF4_BASEPT4_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF4_BASEPT4_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF4_BASEPT4_SIZE}, /* PORT_FILTER_BASEPT5 (# 389) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF5_BASEPT5_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF5_BASEPT5_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF5_BASEPT5_SIZE}, /* PORT_FILTER_BASEPT6 (# 390) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF6_BASEPT6_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF6_BASEPT6_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF6_BASEPT6_SIZE}, /* PORT_FILTER_BASEPT7 (# 391) */ { (IFX_uint16_t)PORT_FILTER_BASEPT, (IFX_uint16_t)TANTOS_3G_TUPF7_BASEPT7_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPF7_BASEPT7_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPF7_BASEPT7_SIZE}, /* PORT_FILTER_COMP (# 392) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR0_COMP0_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR0_COMP0_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR0_COMP0_SIZE}, /* PORT_FILTER_COMP1 (# 393) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR1_COMP1_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR1_COMP1_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR1_COMP1_SIZE}, /* PORT_FILTER_COMP2 (# 394) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR2_COMP2_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR2_COMP2_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR2_COMP2_SIZE}, /* PORT_FILTER_COMP3 (# 395) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR3_COMP3_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR3_COMP3_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR3_COMP3_SIZE}, /* PORT_FILTER_COMP4 (# 396) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR4_COMP4_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR4_COMP4_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR4_COMP4_SIZE}, /* PORT_FILTER_COMP5 (# 397) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR5_COMP5_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR5_COMP5_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR5_COMP5_SIZE}, /* PORT_FILTER_COMP6 (# 398) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR6_COMP6_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR6_COMP6_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR6_COMP6_SIZE}, /* PORT_FILTER_COMP7 (# 399) */ { (IFX_uint16_t)PORT_FILTER_COMP, (IFX_uint16_t)TANTOS_3G_TUPR7_COMP7_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR7_COMP7_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR7_COMP7_SIZE}, /* PORT_FILTER_PRANGE (# 400) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR0_PRANGE0_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR0_PRANGE0_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR0_PRANGE0_SIZE}, /* PORT_FILTER_PRANGE1 (# 401) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR1_PRANGE1_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR1_PRANGE1_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR1_PRANGE1_SIZE}, /* PORT_FILTER_PRANGE2 (# 402) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR2_PRANGE2_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR2_PRANGE2_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR2_PRANGE2_SIZE}, /* PORT_FILTER_PRANGE3 (# 403) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR3_PRANGE3_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR3_PRANGE3_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR3_PRANGE3_SIZE}, /* PORT_FILTER_PRANGE4 (# 404) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR4_PRANGE4_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR4_PRANGE4_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR4_PRANGE4_SIZE}, /* PORT_FILTER_PRANGE5 (# 405) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR5_PRANGE5_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR5_PRANGE5_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR5_PRANGE5_SIZE}, /* PORT_FILTER_PRANGE6 (# 406) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR6_PRANGE6_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR6_PRANGE6_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR6_PRANGE6_SIZE}, /* PORT_FILTER_PRANGE7 (# 407) */ { (IFX_uint16_t)PORT_FILTER_PRANGE, (IFX_uint16_t)TANTOS_3G_TUPR7_PRANGE7_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR7_PRANGE7_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR7_PRANGE7_SIZE}, /* PORT_FILTER_TUPF (# 408) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR0_TUPF0_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR0_TUPF0_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR0_TUPF0_SIZE}, /* PORT_FILTER_TUPF1 (# 409) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR1_TUPF1_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR1_TUPF1_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR1_TUPF1_SIZE}, /* PORT_FILTER_TUPF2 (# 410) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR2_TUPF2_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR2_TUPF2_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR2_TUPF2_SIZE}, /* PORT_FILTER_TUPF3 (# 411) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR3_TUPF3_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR3_TUPF3_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR3_TUPF3_SIZE}, /* PORT_FILTER_TUPF4 (# 412) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR4_TUPF4_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR4_TUPF4_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR4_TUPF4_SIZE}, /* PORT_FILTER_TUPF5 (# 413) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR5_TUPF5_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR5_TUPF5_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR5_TUPF5_SIZE}, /* PORT_FILTER_TUPF6 (# 414) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR6_TUPF6_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR6_TUPF6_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR6_TUPF6_SIZE}, /* PORT_FILTER_TUPF7 (# 415) */ { (IFX_uint16_t)PORT_FILTER_TUPF, (IFX_uint16_t)TANTOS_3G_TUPR7_TUPF7_OFFSET, (IFX_uint8_t)TANTOS_3G_TUPR7_TUPF7_SHIFT, (IFX_uint8_t)TANTOS_3G_TUPR7_TUPF7_SIZE}, /* PORT_FLD (# 416) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P0BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_FLD_SIZE}, /* PORT_FLD1 (# 417) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P1BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_FLD_SIZE}, /* PORT_FLD2 (# 418) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P2BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_FLD_SIZE}, /* PORT_FLD3 (# 419) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P3BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_FLD_SIZE}, /* PORT_FLD4 (# 420) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P4BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_FLD_SIZE}, /* PORT_FLD5 (# 421) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P5BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_FLD_SIZE}, /* PORT_FLD6 (# 422) */ { (IFX_uint16_t)PORT_FLD, (IFX_uint16_t)TANTOS_3G_P6BC_FLD_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_FLD_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_FLD_SIZE}, /* PORT_FLP (# 423) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P0BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_FLP_SIZE}, /* PORT_FLP1 (# 424) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P1BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_FLP_SIZE}, /* PORT_FLP2 (# 425) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P2BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_FLP_SIZE}, /* PORT_FLP3 (# 426) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P3BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_FLP_SIZE}, /* PORT_FLP4 (# 427) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P4BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_FLP_SIZE}, /* PORT_FLP5 (# 428) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P5BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_FLP_SIZE}, /* PORT_FLP6 (# 429) */ { (IFX_uint16_t)PORT_FLP, (IFX_uint16_t)TANTOS_3G_P6BC_FLP_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_FLP_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_FLP_SIZE}, /* PORT_IFNTE (# 430) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P0EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_IFNTE_SIZE}, /* PORT_IFNTE1 (# 431) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P1EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_IFNTE_SIZE}, /* PORT_IFNTE2 (# 432) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P2EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_IFNTE_SIZE}, /* PORT_IFNTE3 (# 433) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P3EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_IFNTE_SIZE}, /* PORT_IFNTE4 (# 434) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P4EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_IFNTE_SIZE}, /* PORT_IFNTE5 (# 435) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P5EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_IFNTE_SIZE}, /* PORT_IFNTE6 (# 436) */ { (IFX_uint16_t)PORT_IFNTE, (IFX_uint16_t)TANTOS_3G_P6EC_IFNTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_IFNTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_IFNTE_SIZE}, /* PORT_IMTE (# 437) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P0EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_IMTE_SIZE}, /* PORT_IMTE1 (# 438) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P1EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_IMTE_SIZE}, /* PORT_IMTE2 (# 439) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P2EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_IMTE_SIZE}, /* PORT_IMTE3 (# 440) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P3EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_IMTE_SIZE}, /* PORT_IMTE4 (# 441) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P4EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_IMTE_SIZE}, /* PORT_IMTE5 (# 442) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P5EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_IMTE_SIZE}, /* PORT_IMTE6 (# 443) */ { (IFX_uint16_t)PORT_IMTE, (IFX_uint16_t)TANTOS_3G_P6EC_IMTE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_IMTE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_IMTE_SIZE}, /* PORT_INGRESS_PITR (# 444) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P0ICR_P0ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ICR_P0ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ICR_P0ITR_SIZE}, /* PORT_INGRESS_PITR1 (# 445) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P1ICR_P1ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ICR_P1ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ICR_P1ITR_SIZE}, /* PORT_INGRESS_PITR2 (# 446) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P2ICR_P2ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ICR_P2ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ICR_P2ITR_SIZE}, /* PORT_INGRESS_PITR3 (# 447) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P3ICR_P3ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ICR_P3ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ICR_P3ITR_SIZE}, /* PORT_INGRESS_PITR4 (# 448) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P4ICR_P4ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ICR_P4ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ICR_P4ITR_SIZE}, /* PORT_INGRESS_PITR5 (# 449) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P5ICR_P5ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ICR_P5ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ICR_P5ITR_SIZE}, /* PORT_INGRESS_PITR6 (# 450) */ { (IFX_uint16_t)PORT_INGRESS_PITR, (IFX_uint16_t)TANTOS_3G_P6ICR_P6ITR_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ICR_P6ITR_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ICR_P6ITR_SIZE}, /* PORT_INGRESS_PITT (# 451) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P0ICR_P0ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P0ICR_P0ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P0ICR_P0ITT_SIZE}, /* PORT_INGRESS_PITT1 (# 452) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P1ICR_P1ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P1ICR_P1ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P1ICR_P1ITT_SIZE}, /* PORT_INGRESS_PITT2 (# 453) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P2ICR_P2ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P2ICR_P2ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P2ICR_P2ITT_SIZE}, /* PORT_INGRESS_PITT3 (# 454) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P3ICR_P3ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P3ICR_P3ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P3ICR_P3ITT_SIZE}, /* PORT_INGRESS_PITT4 (# 455) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P4ICR_P4ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P4ICR_P4ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P4ICR_P4ITT_SIZE}, /* PORT_INGRESS_PITT5 (# 456) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P5ICR_P5ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P5ICR_P5ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P5ICR_P5ITT_SIZE}, /* PORT_INGRESS_PITT6 (# 457) */ { (IFX_uint16_t)PORT_INGRESS_PITT, (IFX_uint16_t)TANTOS_3G_P6ICR_P6ITT_OFFSET, (IFX_uint8_t)TANTOS_3G_P6ICR_P6ITT_SHIFT, (IFX_uint8_t)TANTOS_3G_P6ICR_P6ITT_SIZE}, /* PORT_IPMO (# 458) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P0EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_IPMO_SIZE}, /* PORT_IPMO1 (# 459) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P1EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_IPMO_SIZE}, /* PORT_IPMO2 (# 460) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P2EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_IPMO_SIZE}, /* PORT_IPMO3 (# 461) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P3EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_IPMO_SIZE}, /* PORT_IPMO4 (# 462) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P4EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_IPMO_SIZE}, /* PORT_IPMO5 (# 463) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P5EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_IPMO_SIZE}, /* PORT_IPMO6 (# 464) */ { (IFX_uint16_t)PORT_IPMO, (IFX_uint16_t)TANTOS_3G_P6EC_IPMO_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_IPMO_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_IPMO_SIZE}, /* PORT_IPOVTU (# 465) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P0BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_IPOVTU_SIZE}, /* PORT_IPOVTU1 (# 466) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P1BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_IPOVTU_SIZE}, /* PORT_IPOVTU2 (# 467) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P2BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_IPOVTU_SIZE}, /* PORT_IPOVTU3 (# 468) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P3BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_IPOVTU_SIZE}, /* PORT_IPOVTU4 (# 469) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P4BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_IPOVTU_SIZE}, /* PORT_IPOVTU5 (# 470) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P5BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_IPOVTU_SIZE}, /* PORT_IPOVTU6 (# 471) */ { (IFX_uint16_t)PORT_IPOVTU, (IFX_uint16_t)TANTOS_3G_P6BC_IPOVTU_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_IPOVTU_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_IPOVTU_SIZE}, /* PORT_IPVLAN (# 472) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P0BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_IPVLAN_SIZE}, /* PORT_IPVLAN1 (# 473) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P1BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_IPVLAN_SIZE}, /* PORT_IPVLAN2 (# 474) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P2BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_IPVLAN_SIZE}, /* PORT_IPVLAN3 (# 475) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P3BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_IPVLAN_SIZE}, /* PORT_IPVLAN4 (# 476) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P4BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_IPVLAN_SIZE}, /* PORT_IPVLAN5 (# 477) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P5BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_IPVLAN_SIZE}, /* PORT_IPVLAN6 (# 478) */ { (IFX_uint16_t)PORT_IPVLAN, (IFX_uint16_t)TANTOS_3G_P6BC_IPVLAN_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_IPVLAN_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_IPVLAN_SIZE}, /* PORT_LD (# 479) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P0EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_LD_SIZE}, /* PORT_LD1 (# 480) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P1EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_LD_SIZE}, /* PORT_LD2 (# 481) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P2EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_LD_SIZE}, /* PORT_LD3 (# 482) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P3EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_LD_SIZE}, /* PORT_LD4 (# 483) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P4EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_LD_SIZE}, /* PORT_LD5 (# 484) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P5EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_LD_SIZE}, /* PORT_LD6 (# 485) */ { (IFX_uint16_t)PORT_LD, (IFX_uint16_t)TANTOS_3G_P6EC_LD_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_LD_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_LD_SIZE}, /* PORT_MNA24 (# 486) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P0EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_MNA024_SIZE}, /* PORT_MNA241 (# 487) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P1EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_MNA024_SIZE}, /* PORT_MNA242 (# 488) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P2EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_MNA024_SIZE}, /* PORT_MNA243 (# 489) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P3EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_MNA024_SIZE}, /* PORT_MNA244 (# 490) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P4EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_MNA024_SIZE}, /* PORT_MNA245 (# 491) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P5EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_MNA024_SIZE}, /* PORT_MNA246 (# 492) */ { (IFX_uint16_t)PORT_MNA24, (IFX_uint16_t)TANTOS_3G_P6EC_MNA024_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_MNA024_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_MNA024_SIZE}, /* PORT_MP (# 493) */ { (IFX_uint16_t)PORT_MP, (IFX_uint16_t)TANTOS_3G_MPMRPM_MP_OFFSET, (IFX_uint8_t)TANTOS_3G_MPMRPM_MP_SHIFT, (IFX_uint8_t)TANTOS_3G_MPMRPM_MP_SIZE}, /* PORT_PAS (# 494) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P0EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_PAS_SIZE}, /* PORT_PAS1 (# 495) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P1EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_PAS_SIZE}, /* PORT_PAS2 (# 496) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P2EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_PAS_SIZE}, /* PORT_PAS3 (# 497) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P3EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_PAS_SIZE}, /* PORT_PAS4 (# 498) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P4EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_PAS_SIZE}, /* PORT_PAS5 (# 499) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P5EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_PAS_SIZE}, /* PORT_PAS6 (# 500) */ { (IFX_uint16_t)PORT_PAS, (IFX_uint16_t)TANTOS_3G_P6EC_PAS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_PAS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_PAS_SIZE}, /* PORT_PDS (# 501) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P0S_P0DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0S_P0DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0S_P0DS_SIZE}, /* PORT_PDS1 (# 502) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P1S_P1DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1S_P1DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1S_P1DS_SIZE}, /* PORT_PDS2 (# 503) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P2S_P2DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2S_P2DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2S_P2DS_SIZE}, /* PORT_PDS3 (# 504) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P3S_P3DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3S_P3DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3S_P3DS_SIZE}, /* PORT_PDS4 (# 505) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P4S_P4DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4S_P4DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4S_P4DS_SIZE}, /* PORT_PDS5 (# 506) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P5S_P5DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5S_P5DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5S_P5DS_SIZE}, /* PORT_PDS6 (# 507) */ { (IFX_uint16_t)PORT_PDS, (IFX_uint16_t)TANTOS_3G_P6S_P6DS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6S_P6DS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6S_P6DS_SIZE}, /* PORT_PFCS (# 508) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P0S_P0FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0S_P0FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0S_P0FCS_SIZE}, /* PORT_PFCS1 (# 509) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P1S_P1FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1S_P1FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1S_P1FCS_SIZE}, /* PORT_PFCS2 (# 510) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P2S_P2FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2S_P2FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2S_P2FCS_SIZE}, /* PORT_PFCS3 (# 511) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P3S_P3FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3S_P3FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3S_P3FCS_SIZE}, /* PORT_PFCS4 (# 512) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P4S_P4FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4S_P4FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4S_P4FCS_SIZE}, /* PORT_PFCS5 (# 513) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P5S_P5FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5S_P5FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5S_P5FCS_SIZE}, /* PORT_PFCS6 (# 514) */ { (IFX_uint16_t)PORT_PFCS, (IFX_uint16_t)TANTOS_3G_P6S_P6FCS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6S_P6FCS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6S_P6FCS_SIZE}, /* PORT_PLS (# 515) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P0S_P0LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0S_P0LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0S_P0LS_SIZE}, /* PORT_PLS1 (# 516) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P1S_P1LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1S_P1LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1S_P1LS_SIZE}, /* PORT_PLS2 (# 517) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P2S_P2LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2S_P2LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2S_P2LS_SIZE}, /* PORT_PLS3 (# 518) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P3S_P3LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3S_P3LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3S_P3LS_SIZE}, /* PORT_PLS4 (# 519) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P4S_P4LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4S_P4LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4S_P4LS_SIZE}, /* PORT_PLS5 (# 520) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P5S_P5LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5S_P5LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5S_P5LS_SIZE}, /* PORT_PLS6 (# 521) */ { (IFX_uint16_t)PORT_PLS, (IFX_uint16_t)TANTOS_3G_P6S_P6LS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6S_P6LS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6S_P6LS_SIZE}, /* PORT_PM (# 522) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P0EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_PM_SIZE}, /* PORT_PM1 (# 523) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P1EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_PM_SIZE}, /* PORT_PM2 (# 524) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P2EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_PM_SIZE}, /* PORT_PM3 (# 525) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P3EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_PM_SIZE}, /* PORT_PM4 (# 526) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P4EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_PM_SIZE}, /* PORT_PM5 (# 527) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P5EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_PM_SIZE}, /* PORT_PM6 (# 528) */ { (IFX_uint16_t)PORT_PM, (IFX_uint16_t)TANTOS_3G_P6EC_PM_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_PM_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_PM_SIZE}, /* PORT_PPPOEP (# 529) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P0EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P0EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P0EC_PPPOEP_SIZE}, /* PORT_PPPOEP1 (# 530) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P1EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P1EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P1EC_PPPOEP_SIZE}, /* PORT_PPPOEP2 (# 531) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P2EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P2EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P2EC_PPPOEP_SIZE}, /* PORT_PPPOEP3 (# 532) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P3EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P3EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P3EC_PPPOEP_SIZE}, /* PORT_PPPOEP4 (# 533) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P4EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P4EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P4EC_PPPOEP_SIZE}, /* PORT_PPPOEP5 (# 534) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P5EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P5EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P5EC_PPPOEP_SIZE}, /* PORT_PPPOEP6 (# 535) */ { (IFX_uint16_t)PORT_PPPOEP, (IFX_uint16_t)TANTOS_3G_P6EC_PPPOEP_OFFSET, (IFX_uint8_t)TANTOS_3G_P6EC_PPPOEP_SHIFT, (IFX_uint8_t)TANTOS_3G_P6EC_PPPOEP_SIZE}, /* PORT_PSHS (# 536) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P0S_P0SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0S_P0SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0S_P0SHS_SIZE}, /* PORT_PSHS1 (# 537) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P1S_P1SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1S_P1SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1S_P1SHS_SIZE}, /* PORT_PSHS2 (# 538) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P2S_P2SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2S_P2SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2S_P2SHS_SIZE}, /* PORT_PSHS3 (# 539) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P3S_P3SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3S_P3SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3S_P3SHS_SIZE}, /* PORT_PSHS4 (# 540) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P4S_P4SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4S_P4SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4S_P4SHS_SIZE}, /* PORT_PSHS5 (# 541) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P5S_P5SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5S_P5SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5S_P5SHS_SIZE}, /* PORT_PSHS6 (# 542) */ { (IFX_uint16_t)PORT_PSHS, (IFX_uint16_t)TANTOS_3G_P6S_P6SHS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6S_P6SHS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6S_P6SHS_SIZE}, /* PORT_PSS (# 543) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P0S_P0SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0S_P0SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0S_P0SS_SIZE}, /* PORT_PSS1 (# 544) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P1S_P1SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1S_P1SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1S_P1SS_SIZE}, /* PORT_PSS2 (# 545) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P2S_P2SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2S_P2SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2S_P2SS_SIZE}, /* PORT_PSS3 (# 546) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P3S_P3SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3S_P3SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3S_P3SS_SIZE}, /* PORT_PSS4 (# 547) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P4S_P4SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4S_P4SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4S_P4SS_SIZE}, /* PORT_PSS5 (# 548) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P5S_P5SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5S_P5SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5S_P5SS_SIZE}, /* PORT_PSS6 (# 549) */ { (IFX_uint16_t)PORT_PSS, (IFX_uint16_t)TANTOS_3G_P6S_P6SS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6S_P6SS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6S_P6SS_SIZE}, /* PORT_REDIR (# 550) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_REDIR1 (# 551) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_REDIR2 (# 552) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0CKIO (# 553) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0DUP (# 554) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0FCE (# 555) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0FEQ (# 556) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0IS (# 557) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0RDLY (# 558) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0SPD (# 559) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P0TDLY (# 560) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1CKIO (# 561) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1DUP (# 562) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1FCE (# 563) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1FEQ (# 564) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1IS (# 565) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1RDLY (# 566) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1SPD (# 567) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P1TDLY (# 568) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PORT_RGMII_GMII_P4DUP (# 569) */ { (IFX_uint16_t)PORT_RGMII_GMII_P4DUP, (IFX_uint16_t)TANTOS_3G_RGMIICR_P4DUP_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4DUP_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4DUP_SIZE}, /* PORT_RGMII_GMII_P4FCE (# 570) */ { (IFX_uint16_t)PORT_RGMII_GMII_P4FCE, (IFX_uint16_t)TANTOS_3G_RGMIICR_P4FCE_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4FCE_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4FCE_SIZE}, /* PORT_RGMII_GMII_P4SPD (# 571) */ { (IFX_uint16_t)PORT_RGMII_GMII_P4SPD, (IFX_uint16_t)TANTOS_3G_RGMIICR_P4SPD_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4SPD_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P4SPD_SIZE}, /* PORT_RGMII_GMII_P5DUP (# 572) */ { (IFX_uint16_t)PORT_RGMII_GMII_P5DUP, (IFX_uint16_t)TANTOS_3G_RGMIICR_P5DUP_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5DUP_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5DUP_SIZE}, /* PORT_RGMII_GMII_P5FCE (# 573) */ { (IFX_uint16_t)PORT_RGMII_GMII_P5FCE, (IFX_uint16_t)TANTOS_3G_RGMIICR_P5FCE_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5FCE_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5FCE_SIZE}, /* PORT_RGMII_GMII_P5SPD (# 574) */ { (IFX_uint16_t)PORT_RGMII_GMII_P5SPD, (IFX_uint16_t)TANTOS_3G_RGMIICR_P5SPD_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5SPD_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P5SPD_SIZE}, /* PORT_RGMII_GMII_P6DUP (# 575) */ { (IFX_uint16_t)PORT_RGMII_GMII_P6DUP, (IFX_uint16_t)TANTOS_3G_RGMIICR_P6DUP_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6DUP_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6DUP_SIZE}, /* PORT_RGMII_GMII_P6FCE (# 576) */ { (IFX_uint16_t)PORT_RGMII_GMII_P6FCE, (IFX_uint16_t)TANTOS_3G_RGMIICR_P6FCE_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6FCE_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6FCE_SIZE}, /* PORT_RGMII_GMII_P6SPD (# 577) */ { (IFX_uint16_t)PORT_RGMII_GMII_P6SPD, (IFX_uint16_t)TANTOS_3G_RGMIICR_P6SPD_OFFSET, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6SPD_SHIFT, (IFX_uint8_t)TANTOS_3G_RGMIICR_P6SPD_SIZE}, /* PORT_RMWFQ (# 578) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P0BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_RMWFQ_SIZE}, /* PORT_RMWFQ1 (# 579) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P1BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_RMWFQ_SIZE}, /* PORT_RMWFQ2 (# 580) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P2BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_RMWFQ_SIZE}, /* PORT_RMWFQ3 (# 581) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P3BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_RMWFQ_SIZE}, /* PORT_RMWFQ4 (# 582) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P4BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_RMWFQ_SIZE}, /* PORT_RMWFQ5 (# 583) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P5BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_RMWFQ_SIZE}, /* PORT_RMWFQ6 (# 584) */ { (IFX_uint16_t)PORT_RMWFQ, (IFX_uint16_t)TANTOS_3G_P6BC_RMWFQ_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_RMWFQ_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_RMWFQ_SIZE}, /* PORT_RP (# 585) */ { (IFX_uint16_t)PORT_RP, (IFX_uint16_t)TANTOS_3G_MPMRPM_RP_OFFSET, (IFX_uint8_t)TANTOS_3G_MPMRPM_RP_SHIFT, (IFX_uint8_t)TANTOS_3G_MPMRPM_RP_SIZE}, /* PORT_SPE (# 586) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P0BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_SPE_SIZE}, /* PORT_SPE1 (# 587) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P1BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_SPE_SIZE}, /* PORT_SPE2 (# 588) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P2BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_SPE_SIZE}, /* PORT_SPE3 (# 589) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P3BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_SPE_SIZE}, /* PORT_SPE4 (# 590) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P4BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_SPE_SIZE}, /* PORT_SPE5 (# 591) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P5BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_SPE_SIZE}, /* PORT_SPE6 (# 592) */ { (IFX_uint16_t)PORT_SPE, (IFX_uint16_t)TANTOS_3G_P6BC_SPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_SPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_SPE_SIZE}, /* PORT_SPS (# 593) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P0BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_SPS_SIZE}, /* PORT_SPS1 (# 594) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P1BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_SPS_SIZE}, /* PORT_SPS2 (# 595) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P2BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_SPS_SIZE}, /* PORT_SPS3 (# 596) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P3BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_SPS_SIZE}, /* PORT_SPS4 (# 597) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P4BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_SPS_SIZE}, /* PORT_SPS5 (# 598) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P5BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_SPS_SIZE}, /* PORT_SPS6 (# 599) */ { (IFX_uint16_t)PORT_SPS, (IFX_uint16_t)TANTOS_3G_P6BC_SPS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_SPS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_SPS_SIZE}, /* PORT_TCPE (# 600) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P0BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_TCPE_SIZE}, /* PORT_TCPE1 (# 601) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P1BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_TCPE_SIZE}, /* PORT_TCPE2 (# 602) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P2BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_TCPE_SIZE}, /* PORT_TCPE3 (# 603) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P3BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_TCPE_SIZE}, /* PORT_TCPE4 (# 604) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P4BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_TCPE_SIZE}, /* PORT_TCPE5 (# 605) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P5BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_TCPE_SIZE}, /* PORT_TCPE6 (# 606) */ { (IFX_uint16_t)PORT_TCPE, (IFX_uint16_t)TANTOS_3G_P6BC_TCPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_TCPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_TCPE_SIZE}, /* PORT_TPE (# 607) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P0BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_TPE_SIZE}, /* PORT_TPE1 (# 608) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P1BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_TPE_SIZE}, /* PORT_TPE2 (# 609) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P2BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_TPE_SIZE}, /* PORT_TPE3 (# 610) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P3BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_TPE_SIZE}, /* PORT_TPE4 (# 611) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P4BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_TPE_SIZE}, /* PORT_TPE5 (# 612) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P5BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_TPE_SIZE}, /* PORT_TPE6 (# 613) */ { (IFX_uint16_t)PORT_TPE, (IFX_uint16_t)TANTOS_3G_P6BC_TPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_TPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_TPE_SIZE}, /* PORT_UP (# 614) */ { (IFX_uint16_t)PORT_UP, (IFX_uint16_t)TANTOS_3G_UPMBPM_UP_OFFSET, (IFX_uint8_t)TANTOS_3G_UPMBPM_UP_SHIFT, (IFX_uint8_t)TANTOS_3G_UPMBPM_UP_SIZE}, /* PORT_VLAN_AOVTP (# 615) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P0PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP1 (# 616) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P1PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP2 (# 617) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P2PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP3 (# 618) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P3PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP4 (# 619) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P4PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP5 (# 620) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P5PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_AOVTP_SIZE}, /* PORT_VLAN_AOVTP6 (# 621) */ { (IFX_uint16_t)PORT_VLAN_AOVTP, (IFX_uint16_t)TANTOS_3G_P6PBVM_AOVTP_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_AOVTP_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_AOVTP_SIZE}, /* PORT_VLAN_BYPASS (# 622) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P0PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS1 (# 623) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P1PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS2 (# 624) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P2PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS3 (# 625) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P3PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS4 (# 626) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P4PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS5 (# 627) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P5PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_BYPASS_SIZE}, /* PORT_VLAN_BYPASS6 (# 628) */ { (IFX_uint16_t)PORT_VLAN_BYPASS, (IFX_uint16_t)TANTOS_3G_P6PBVM_BYPASS_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_BYPASS_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_BYPASS_SIZE}, /* PORT_VLAN_DFID (# 629) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P0PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_DFID_SIZE}, /* PORT_VLAN_DFID1 (# 630) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P1PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_DFID_SIZE}, /* PORT_VLAN_DFID2 (# 631) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P2PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_DFID_SIZE}, /* PORT_VLAN_DFID3 (# 632) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P3PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_DFID_SIZE}, /* PORT_VLAN_DFID4 (# 633) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P4PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_DFID_SIZE}, /* PORT_VLAN_DFID5 (# 634) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P5PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_DFID_SIZE}, /* PORT_VLAN_DFID6 (# 635) */ { (IFX_uint16_t)PORT_VLAN_DFID, (IFX_uint16_t)TANTOS_3G_P6PBVM_DFID_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_DFID_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_DFID_SIZE}, /* PORT_VLAN_DVPM (# 636) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P0PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM1 (# 637) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P1PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM2 (# 638) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P2PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM3 (# 639) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P3PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM4 (# 640) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P4PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM5 (# 641) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P5PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_DVPM_SIZE}, /* PORT_VLAN_DVPM6 (# 642) */ { (IFX_uint16_t)PORT_VLAN_DVPM, (IFX_uint16_t)TANTOS_3G_P6PBVM_DVPM_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_DVPM_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_DVPM_SIZE}, /* PORT_VLAN_PP (# 643) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P0DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P0DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P0DVID_PP_SIZE}, /* PORT_VLAN_PP1 (# 644) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P1DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P1DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P1DVID_PP_SIZE}, /* PORT_VLAN_PP2 (# 645) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P2DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P2DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P2DVID_PP_SIZE}, /* PORT_VLAN_PP3 (# 646) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P3DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P3DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P3DVID_PP_SIZE}, /* PORT_VLAN_PP4 (# 647) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P4DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P4DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P4DVID_PP_SIZE}, /* PORT_VLAN_PP5 (# 648) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P5DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P5DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P5DVID_PP_SIZE}, /* PORT_VLAN_PP6 (# 649) */ { (IFX_uint16_t)PORT_VLAN_PP, (IFX_uint16_t)TANTOS_3G_P6DVID_PP_OFFSET, (IFX_uint8_t)TANTOS_3G_P6DVID_PP_SHIFT, (IFX_uint8_t)TANTOS_3G_P6DVID_PP_SIZE}, /* PORT_VLAN_PPE (# 650) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P0DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0DVID_PPE_SIZE}, /* PORT_VLAN_PPE1 (# 651) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P1DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1DVID_PPE_SIZE}, /* PORT_VLAN_PPE2 (# 652) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P2DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2DVID_PPE_SIZE}, /* PORT_VLAN_PPE3 (# 653) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P3DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3DVID_PPE_SIZE}, /* PORT_VLAN_PPE4 (# 654) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P4DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4DVID_PPE_SIZE}, /* PORT_VLAN_PPE5 (# 655) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P5DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5DVID_PPE_SIZE}, /* PORT_VLAN_PPE6 (# 656) */ { (IFX_uint16_t)PORT_VLAN_PPE, (IFX_uint16_t)TANTOS_3G_P6DVID_PPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6DVID_PPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6DVID_PPE_SIZE}, /* PORT_VLAN_PVID (# 657) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P0DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P0DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P0DVID_PVID_SIZE}, /* PORT_VLAN_PVID1 (# 658) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P1DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P1DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P1DVID_PVID_SIZE}, /* PORT_VLAN_PVID2 (# 659) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P2DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P2DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P2DVID_PVID_SIZE}, /* PORT_VLAN_PVID3 (# 660) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P3DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P3DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P3DVID_PVID_SIZE}, /* PORT_VLAN_PVID4 (# 661) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P4DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P4DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P4DVID_PVID_SIZE}, /* PORT_VLAN_PVID5 (# 662) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P5DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P5DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P5DVID_PVID_SIZE}, /* PORT_VLAN_PVID6 (# 663) */ { (IFX_uint16_t)PORT_VLAN_PVID, (IFX_uint16_t)TANTOS_3G_P6DVID_PVID_OFFSET, (IFX_uint8_t)TANTOS_3G_P6DVID_PVID_SHIFT, (IFX_uint8_t)TANTOS_3G_P6DVID_PVID_SIZE}, /* PORT_VLAN_PVTAGMP (# 664) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P0DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P0DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P0DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP1 (# 665) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P1DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P1DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P1DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP2 (# 666) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P2DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P2DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P2DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP3 (# 667) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P3DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P3DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P3DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP4 (# 668) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P4DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P4DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P4DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP5 (# 669) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P5DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P5DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P5DVID_PVTAGMP_SIZE}, /* PORT_VLAN_PVTAGMP6 (# 670) */ { (IFX_uint16_t)PORT_VLAN_PVTAGMP, (IFX_uint16_t)TANTOS_3G_P6DVID_PVTAGMP_OFFSET, (IFX_uint8_t)TANTOS_3G_P6DVID_PVTAGMP_SHIFT, (IFX_uint8_t)TANTOS_3G_P6DVID_PVTAGMP_SIZE}, /* PORT_VLAN_TBVE (# 671) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P0PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE1 (# 672) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P1PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE2 (# 673) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P2PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE3 (# 674) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P3PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE4 (# 675) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P4PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE5 (# 676) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P5PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_TBVE_SIZE}, /* PORT_VLAN_TBVE6 (# 677) */ { (IFX_uint16_t)PORT_VLAN_TBVE, (IFX_uint16_t)TANTOS_3G_P6PBVM_TBVE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_TBVE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_TBVE_SIZE}, /* PORT_VLAN_VC (# 678) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P0PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_VC_SIZE}, /* PORT_VLAN_VC1 (# 679) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P1PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_VC_SIZE}, /* PORT_VLAN_VC2 (# 680) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P2PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_VC_SIZE}, /* PORT_VLAN_VC3 (# 681) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P3PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_VC_SIZE}, /* PORT_VLAN_VC4 (# 682) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P4PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_VC_SIZE}, /* PORT_VLAN_VC5 (# 683) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P5PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_VC_SIZE}, /* PORT_VLAN_VC6 (# 684) */ { (IFX_uint16_t)PORT_VLAN_VC, (IFX_uint16_t)TANTOS_3G_P6PBVM_VC_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_VC_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_VC_SIZE}, /* PORT_VLAN_VMCE (# 685) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P0PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE1 (# 686) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P1PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE2 (# 687) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P2PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE3 (# 688) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P3PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE4 (# 689) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P4PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE5 (# 690) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P5PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_VMCE_SIZE}, /* PORT_VLAN_VMCE6 (# 691) */ { (IFX_uint16_t)PORT_VLAN_VMCE, (IFX_uint16_t)TANTOS_3G_P6PBVM_VMCE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_VMCE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_VMCE_SIZE}, /* PORT_VLAN_VSD (# 692) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P0PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P0PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P0PBVM_VSD_SIZE}, /* PORT_VLAN_VSD1 (# 693) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P1PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P1PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P1PBVM_VSD_SIZE}, /* PORT_VLAN_VSD2 (# 694) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P2PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P2PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P2PBVM_VSD_SIZE}, /* PORT_VLAN_VSD3 (# 695) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P3PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P3PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P3PBVM_VSD_SIZE}, /* PORT_VLAN_VSD4 (# 696) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P4PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P4PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P4PBVM_VSD_SIZE}, /* PORT_VLAN_VSD5 (# 697) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P5PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P5PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P5PBVM_VSD_SIZE}, /* PORT_VLAN_VSD6 (# 698) */ { (IFX_uint16_t)PORT_VLAN_VSD, (IFX_uint16_t)TANTOS_3G_P6PBVM_VSD_OFFSET, (IFX_uint8_t)TANTOS_3G_P6PBVM_VSD_SHIFT, (IFX_uint8_t)TANTOS_3G_P6PBVM_VSD_SIZE}, /* PORT_VPE (# 699) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P0BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P0BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P0BC_VPE_SIZE}, /* PORT_VPE1 (# 700) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P1BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P1BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P1BC_VPE_SIZE}, /* PORT_VPE2 (# 701) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P2BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P2BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P2BC_VPE_SIZE}, /* PORT_VPE3 (# 702) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P3BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P3BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P3BC_VPE_SIZE}, /* PORT_VPE4 (# 703) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P4BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P4BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P4BC_VPE_SIZE}, /* PORT_VPE5 (# 704) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P5BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P5BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P5BC_VPE_SIZE}, /* PORT_VPE6 (# 705) */ { (IFX_uint16_t)PORT_VPE, (IFX_uint16_t)TANTOS_3G_P6BC_VPE_OFFSET, (IFX_uint8_t)TANTOS_3G_P6BC_VPE_SHIFT, (IFX_uint8_t)TANTOS_3G_P6BC_VPE_SIZE}, /* PPPOE_SID (# 706) */ { (IFX_uint16_t)PPPOE_SID, (IFX_uint16_t)TANTOS_3G_PSIDR_PPPOESID_OFFSET, (IFX_uint8_t)TANTOS_3G_PSIDR_PPPOESID_SHIFT, (IFX_uint8_t)TANTOS_3G_PSIDR_PPPOESID_SIZE}, /* PROTOCOL_FILTER_APF (# 707) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF0_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF0_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF0_SIZE}, /* PROTOCOL_FILTER_APF1 (# 708) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF1_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF1_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF1_SIZE}, /* PROTOCOL_FILTER_APF2 (# 709) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF2_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF2_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF2_SIZE}, /* PROTOCOL_FILTER_APF3 (# 710) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF3_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF3_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF3_SIZE}, /* PROTOCOL_FILTER_APF4 (# 711) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF4_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF4_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF4_SIZE}, /* PROTOCOL_FILTER_APF5 (# 712) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF5_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF5_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF5_SIZE}, /* PROTOCOL_FILTER_APF6 (# 713) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF6_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF6_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF6_SIZE}, /* PROTOCOL_FILTER_APF7 (# 714) */ { (IFX_uint16_t)PROTOCOL_FILTER_APF, (IFX_uint16_t)TANTOS_3G_PFA_APF7_OFFSET, (IFX_uint8_t)TANTOS_3G_PFA_APF7_SHIFT, (IFX_uint8_t)TANTOS_3G_PFA_APF7_SIZE}, /* PROTOCOL_FILTER_PFR0 (# 715) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)TANTOS_3G_PF_0_PFR0_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_0_PFR0_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_0_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR01 (# 716) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)TANTOS_3G_PF_1_PFR0_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_1_PFR0_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_1_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR02 (# 717) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)TANTOS_3G_PF_2_PFR0_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_2_PFR0_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_2_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR03 (# 718) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR0, (IFX_uint16_t)TANTOS_3G_PF_3_PFR0_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_3_PFR0_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_3_PFR0_SIZE}, /* PROTOCOL_FILTER_PFR1 (# 719) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)TANTOS_3G_PF_0_PFR1_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_0_PFR1_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_0_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR11 (# 720) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)TANTOS_3G_PF_1_PFR1_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_1_PFR1_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_1_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR12 (# 721) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)TANTOS_3G_PF_2_PFR1_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_2_PFR1_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_2_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR13 (# 722) */ { (IFX_uint16_t)PROTOCOL_FILTER_PFR1, (IFX_uint16_t)TANTOS_3G_PF_3_PFR1_OFFSET, (IFX_uint8_t)TANTOS_3G_PF_3_PFR1_SHIFT, (IFX_uint8_t)TANTOS_3G_PF_3_PFR1_SIZE}, /* PROTOCOL_FILTER_PFR2 (# 723) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR21 (# 724) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR3 (# 725) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* PROTOCOL_FILTER_PFR31 (# 726) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA00_ACT (# 727) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_ACT_SIZE}, /* RA00_ACT1 (# 728) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_ACT_SIZE}, /* RA00_ACT2 (# 729) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_ACT_SIZE}, /* RA00_ACT3 (# 730) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_ACT_SIZE}, /* RA00_ACT4 (# 731) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_ACT_SIZE}, /* RA00_ACT5 (# 732) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_ACT_SIZE}, /* RA00_ACT6 (# 733) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_ACT_SIZE}, /* RA00_ACT7 (# 734) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_ACT_SIZE}, /* RA00_ACT8 (# 735) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_ACT_SIZE}, /* RA00_ACT9 (# 736) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_ACT_SIZE}, /* RA00_ACT10 (# 737) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_ACT_SIZE}, /* RA00_ACT11 (# 738) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_ACT_SIZE}, /* RA00_ACT12 (# 739) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_ACT_SIZE}, /* RA00_ACT13 (# 740) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_ACT_SIZE}, /* RA00_ACT14 (# 741) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_ACT_SIZE}, /* RA00_ACT15 (# 742) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_ACT_SIZE}, /* RA00_ACT16 (# 743) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_ACT_SIZE}, /* RA00_ACT17 (# 744) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_ACT_SIZE}, /* RA00_ACT18 (# 745) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_ACT_SIZE}, /* RA00_ACT19 (# 746) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_ACT_SIZE}, /* RA00_ACT20 (# 747) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_ACT_SIZE}, /* RA00_ACT21 (# 748) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_ACT_SIZE}, /* RA00_ACT22 (# 749) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_ACT_SIZE}, /* RA00_ACT23 (# 750) */ { (IFX_uint16_t)RA00_ACT, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_ACT_SIZE}, /* RA00_CV (# 751) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_CV_SIZE}, /* RA00_CV1 (# 752) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_CV_SIZE}, /* RA00_CV2 (# 753) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_CV_SIZE}, /* RA00_CV3 (# 754) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_CV_SIZE}, /* RA00_CV4 (# 755) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_CV_SIZE}, /* RA00_CV5 (# 756) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_CV_SIZE}, /* RA00_CV6 (# 757) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_CV_SIZE}, /* RA00_CV7 (# 758) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_CV_SIZE}, /* RA00_CV8 (# 759) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_CV_SIZE}, /* RA00_CV9 (# 760) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_CV_SIZE}, /* RA00_CV10 (# 761) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_CV_SIZE}, /* RA00_CV11 (# 762) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_CV_SIZE}, /* RA00_CV12 (# 763) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_CV_SIZE}, /* RA00_CV13 (# 764) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_CV_SIZE}, /* RA00_CV14 (# 765) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_CV_SIZE}, /* RA00_CV15 (# 766) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_CV_SIZE}, /* RA00_CV16 (# 767) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_CV_SIZE}, /* RA00_CV17 (# 768) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_CV_SIZE}, /* RA00_CV18 (# 769) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_CV_SIZE}, /* RA00_CV19 (# 770) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_CV_SIZE}, /* RA00_CV20 (# 771) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_CV_SIZE}, /* RA00_CV21 (# 772) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_CV_SIZE}, /* RA00_CV22 (# 773) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_CV_SIZE}, /* RA00_CV23 (# 774) */ { (IFX_uint16_t)RA00_CV, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_CV_SIZE}, /* RA00_MG (# 775) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_MG_SIZE}, /* RA00_MG1 (# 776) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_MG_SIZE}, /* RA00_MG2 (# 777) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_MG_SIZE}, /* RA00_MG3 (# 778) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_MG_SIZE}, /* RA00_MG4 (# 779) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_MG_SIZE}, /* RA00_MG5 (# 780) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_MG_SIZE}, /* RA00_MG6 (# 781) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_MG_SIZE}, /* RA00_MG7 (# 782) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_MG_SIZE}, /* RA00_MG8 (# 783) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_MG_SIZE}, /* RA00_MG9 (# 784) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_MG_SIZE}, /* RA00_MG10 (# 785) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_MG_SIZE}, /* RA00_MG11 (# 786) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_MG_SIZE}, /* RA00_MG12 (# 787) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_MG_SIZE}, /* RA00_MG13 (# 788) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_MG_SIZE}, /* RA00_MG14 (# 789) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_MG_SIZE}, /* RA00_MG15 (# 790) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_MG_SIZE}, /* RA00_MG16 (# 791) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_MG_SIZE}, /* RA00_MG17 (# 792) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_MG_SIZE}, /* RA00_MG18 (# 793) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_MG_SIZE}, /* RA00_MG19 (# 794) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_MG_SIZE}, /* RA00_MG20 (# 795) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_MG_SIZE}, /* RA00_MG21 (# 796) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_MG_SIZE}, /* RA00_MG22 (# 797) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_MG_SIZE}, /* RA00_MG23 (# 798) */ { (IFX_uint16_t)RA00_MG, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_MG_SIZE}, /* RA00_SPAN (# 799) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_SPAN_SIZE}, /* RA00_SPAN1 (# 800) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_SPAN_SIZE}, /* RA00_SPAN2 (# 801) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_SPAN_SIZE}, /* RA00_SPAN3 (# 802) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_SPAN_SIZE}, /* RA00_SPAN4 (# 803) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_SPAN_SIZE}, /* RA00_SPAN5 (# 804) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_SPAN_SIZE}, /* RA00_SPAN6 (# 805) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_SPAN_SIZE}, /* RA00_SPAN7 (# 806) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_SPAN_SIZE}, /* RA00_SPAN8 (# 807) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_SPAN_SIZE}, /* RA00_SPAN9 (# 808) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_SPAN_SIZE}, /* RA00_SPAN10 (# 809) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_SPAN_SIZE}, /* RA00_SPAN11 (# 810) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_SPAN_SIZE}, /* RA00_SPAN12 (# 811) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_SPAN_SIZE}, /* RA00_SPAN13 (# 812) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_SPAN_SIZE}, /* RA00_SPAN14 (# 813) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_SPAN_SIZE}, /* RA00_SPAN15 (# 814) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_SPAN_SIZE}, /* RA00_SPAN16 (# 815) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_SPAN_SIZE}, /* RA00_SPAN17 (# 816) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_SPAN_SIZE}, /* RA00_SPAN18 (# 817) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_SPAN_SIZE}, /* RA00_SPAN19 (# 818) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_SPAN_SIZE}, /* RA00_SPAN20 (# 819) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_SPAN_SIZE}, /* RA00_SPAN21 (# 820) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_SPAN_SIZE}, /* RA00_SPAN22 (# 821) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_SPAN_SIZE}, /* RA00_SPAN23 (# 822) */ { (IFX_uint16_t)RA00_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_SPAN_SIZE}, /* RA00_TXTAG (# 823) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_TXTAG_SIZE}, /* RA00_TXTAG1 (# 824) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_TXTAG_SIZE}, /* RA00_TXTAG2 (# 825) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_TXTAG_SIZE}, /* RA00_TXTAG3 (# 826) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_TXTAG_SIZE}, /* RA00_TXTAG4 (# 827) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_TXTAG_SIZE}, /* RA00_TXTAG5 (# 828) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SIZE}, /* RA00_TXTAG6 (# 829) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SIZE}, /* RA00_TXTAG7 (# 830) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SIZE}, /* RA00_TXTAG8 (# 831) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_TXTAG_SIZE}, /* RA00_TXTAG9 (# 832) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_TXTAG_SIZE}, /* RA00_TXTAG10 (# 833) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_TXTAG_SIZE}, /* RA00_TXTAG11 (# 834) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_TXTAG_SIZE}, /* RA00_TXTAG12 (# 835) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_TXTAG_SIZE}, /* RA00_TXTAG13 (# 836) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_TXTAG_SIZE}, /* RA00_TXTAG14 (# 837) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_TXTAG_SIZE}, /* RA00_TXTAG15 (# 838) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_TXTAG_SIZE}, /* RA00_TXTAG16 (# 839) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_TXTAG_SIZE}, /* RA00_TXTAG17 (# 840) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_TXTAG_SIZE}, /* RA00_TXTAG18 (# 841) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_TXTAG_SIZE}, /* RA00_TXTAG19 (# 842) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_TXTAG_SIZE}, /* RA00_TXTAG20 (# 843) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_TXTAG_SIZE}, /* RA00_TXTAG21 (# 844) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_TXTAG_SIZE}, /* RA00_TXTAG22 (# 845) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_TXTAG_SIZE}, /* RA00_TXTAG23 (# 846) */ { (IFX_uint16_t)RA00_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_TXTAG_SIZE}, /* RA00_VALID (# 847) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA00_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA00_VALID_SIZE}, /* RA00_VALID1 (# 848) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA20_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA20_VALID_SIZE}, /* RA00_VALID2 (# 849) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA40_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA40_VALID_SIZE}, /* RA00_VALID3 (# 850) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA60_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA60_VALID_SIZE}, /* RA00_VALID4 (# 851) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA80_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA80_VALID_SIZE}, /* RA00_VALID5 (# 852) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1100_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1100_VALID_SIZE}, /* RA00_VALID6 (# 853) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1320_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1320_VALID_SIZE}, /* RA00_VALID7 (# 854) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1540_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1540_VALID_SIZE}, /* RA00_VALID8 (# 855) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1760_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1760_VALID_SIZE}, /* RA00_VALID9 (# 856) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1980_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1980_VALID_SIZE}, /* RA00_VALID10 (# 857) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA200_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA200_VALID_SIZE}, /* RA00_VALID11 (# 858) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA220_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA220_VALID_SIZE}, /* RA00_VALID12 (# 859) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA240_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA240_VALID_SIZE}, /* RA00_VALID13 (# 860) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA260_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA260_VALID_SIZE}, /* RA00_VALID14 (# 861) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA280_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA280_VALID_SIZE}, /* RA00_VALID15 (# 862) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA300_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA300_VALID_SIZE}, /* RA00_VALID16 (# 863) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA320_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA320_VALID_SIZE}, /* RA00_VALID17 (# 864) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA340_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA340_VALID_SIZE}, /* RA00_VALID18 (# 865) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA360_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA360_VALID_SIZE}, /* RA00_VALID19 (# 866) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA380_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA380_VALID_SIZE}, /* RA00_VALID20 (# 867) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA400_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA400_VALID_SIZE}, /* RA00_VALID21 (# 868) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA420_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA420_VALID_SIZE}, /* RA00_VALID22 (# 869) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA440_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA440_VALID_SIZE}, /* RA00_VALID23 (# 870) */ { (IFX_uint16_t)RA00_VALID, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA460_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA460_VALID_SIZE}, /* RA01_ACT (# 871) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_ACT_SIZE}, /* RA01_ACT1 (# 872) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_ACT_SIZE}, /* RA01_ACT2 (# 873) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_ACT_SIZE}, /* RA01_ACT3 (# 874) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_ACT_SIZE}, /* RA01_ACT4 (# 875) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_ACT_SIZE}, /* RA01_ACT5 (# 876) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_ACT_SIZE}, /* RA01_ACT6 (# 877) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_ACT_SIZE}, /* RA01_ACT7 (# 878) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_ACT_SIZE}, /* RA01_ACT8 (# 879) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_ACT_SIZE}, /* RA01_ACT9 (# 880) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_ACT_SIZE}, /* RA01_ACT10 (# 881) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_ACT_SIZE}, /* RA01_ACT11 (# 882) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_ACT_SIZE}, /* RA01_ACT12 (# 883) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_ACT_SIZE}, /* RA01_ACT13 (# 884) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_ACT_SIZE}, /* RA01_ACT14 (# 885) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_ACT_SIZE}, /* RA01_ACT15 (# 886) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_ACT_SIZE}, /* RA01_ACT16 (# 887) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_ACT_SIZE}, /* RA01_ACT17 (# 888) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_ACT_SIZE}, /* RA01_ACT18 (# 889) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_ACT_SIZE}, /* RA01_ACT19 (# 890) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_ACT_SIZE}, /* RA01_ACT20 (# 891) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_ACT_SIZE}, /* RA01_ACT21 (# 892) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_ACT_SIZE}, /* RA01_ACT22 (# 893) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_ACT_SIZE}, /* RA01_ACT23 (# 894) */ { (IFX_uint16_t)RA01_ACT, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_ACT_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_ACT_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_ACT_SIZE}, /* RA01_CV (# 895) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_CV_SIZE}, /* RA01_CV1 (# 896) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_CV_SIZE}, /* RA01_CV2 (# 897) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_CV_SIZE}, /* RA01_CV3 (# 898) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_CV_SIZE}, /* RA01_CV4 (# 899) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_CV_SIZE}, /* RA01_CV5 (# 900) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_CV_SIZE}, /* RA01_CV6 (# 901) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_CV_SIZE}, /* RA01_CV7 (# 902) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_CV_SIZE}, /* RA01_CV8 (# 903) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_CV_SIZE}, /* RA01_CV9 (# 904) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_CV_SIZE}, /* RA01_CV10 (# 905) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_CV_SIZE}, /* RA01_CV11 (# 906) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_CV_SIZE}, /* RA01_CV12 (# 907) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_CV_SIZE}, /* RA01_CV13 (# 908) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_CV_SIZE}, /* RA01_CV14 (# 909) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_CV_SIZE}, /* RA01_CV15 (# 910) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_CV_SIZE}, /* RA01_CV16 (# 911) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_CV_SIZE}, /* RA01_CV17 (# 912) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_CV_SIZE}, /* RA01_CV18 (# 913) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_CV_SIZE}, /* RA01_CV19 (# 914) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_CV_SIZE}, /* RA01_CV20 (# 915) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_CV_SIZE}, /* RA01_CV21 (# 916) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_CV_SIZE}, /* RA01_CV22 (# 917) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_CV_SIZE}, /* RA01_CV23 (# 918) */ { (IFX_uint16_t)RA01_CV, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_CV_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_CV_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_CV_SIZE}, /* RA01_MG (# 919) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_MG_SIZE}, /* RA01_MG1 (# 920) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_MG_SIZE}, /* RA01_MG2 (# 921) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_MG_SIZE}, /* RA01_MG3 (# 922) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_MG_SIZE}, /* RA01_MG4 (# 923) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_MG_SIZE}, /* RA01_MG5 (# 924) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_MG_SIZE}, /* RA01_MG6 (# 925) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_MG_SIZE}, /* RA01_MG7 (# 926) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_MG_SIZE}, /* RA01_MG8 (# 927) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_MG_SIZE}, /* RA01_MG9 (# 928) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_MG_SIZE}, /* RA01_MG10 (# 929) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_MG_SIZE}, /* RA01_MG11 (# 930) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_MG_SIZE}, /* RA01_MG12 (# 931) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_MG_SIZE}, /* RA01_MG13 (# 932) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_MG_SIZE}, /* RA01_MG14 (# 933) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_MG_SIZE}, /* RA01_MG15 (# 934) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_MG_SIZE}, /* RA01_MG16 (# 935) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_MG_SIZE}, /* RA01_MG17 (# 936) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_MG_SIZE}, /* RA01_MG18 (# 937) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_MG_SIZE}, /* RA01_MG19 (# 938) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_MG_SIZE}, /* RA01_MG20 (# 939) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_MG_SIZE}, /* RA01_MG21 (# 940) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_MG_SIZE}, /* RA01_MG22 (# 941) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_MG_SIZE}, /* RA01_MG23 (# 942) */ { (IFX_uint16_t)RA01_MG, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_MG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_MG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_MG_SIZE}, /* RA01_SPAN (# 943) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_SPAN_SIZE}, /* RA01_SPAN1 (# 944) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_SPAN_SIZE}, /* RA01_SPAN2 (# 945) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_SPAN_SIZE}, /* RA01_SPAN3 (# 946) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_SPAN_SIZE}, /* RA01_SPAN4 (# 947) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_SPAN_SIZE}, /* RA01_SPAN5 (# 948) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_SPAN_SIZE}, /* RA01_SPAN6 (# 949) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_SPAN_SIZE}, /* RA01_SPAN7 (# 950) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_SPAN_SIZE}, /* RA01_SPAN8 (# 951) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_SPAN_SIZE}, /* RA01_SPAN9 (# 952) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_SPAN_SIZE}, /* RA01_SPAN10 (# 953) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_SPAN_SIZE}, /* RA01_SPAN11 (# 954) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_SPAN_SIZE}, /* RA01_SPAN12 (# 955) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_SPAN_SIZE}, /* RA01_SPAN13 (# 956) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_SPAN_SIZE}, /* RA01_SPAN14 (# 957) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_SPAN_SIZE}, /* RA01_SPAN15 (# 958) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_SPAN_SIZE}, /* RA01_SPAN16 (# 959) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_SPAN_SIZE}, /* RA01_SPAN17 (# 960) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_SPAN_SIZE}, /* RA01_SPAN18 (# 961) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_SPAN_SIZE}, /* RA01_SPAN19 (# 962) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_SPAN_SIZE}, /* RA01_SPAN20 (# 963) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_SPAN_SIZE}, /* RA01_SPAN21 (# 964) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_SPAN_SIZE}, /* RA01_SPAN22 (# 965) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_SPAN_SIZE}, /* RA01_SPAN23 (# 966) */ { (IFX_uint16_t)RA01_SPAN, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_SPAN_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_SPAN_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_SPAN_SIZE}, /* RA01_TXTAG (# 967) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_TXTAG_SIZE}, /* RA01_TXTAG1 (# 968) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_TXTAG_SIZE}, /* RA01_TXTAG2 (# 969) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_TXTAG_SIZE}, /* RA01_TXTAG3 (# 970) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_TXTAG_SIZE}, /* RA01_TXTAG4 (# 971) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_TXTAG_SIZE}, /* RA01_TXTAG5 (# 972) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SIZE}, /* RA01_TXTAG6 (# 973) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SIZE}, /* RA01_TXTAG7 (# 974) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SIZE}, /* RA01_TXTAG8 (# 975) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_TXTAG_SIZE}, /* RA01_TXTAG9 (# 976) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_TXTAG_SIZE}, /* RA01_TXTAG10 (# 977) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_TXTAG_SIZE}, /* RA01_TXTAG11 (# 978) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_TXTAG_SIZE}, /* RA01_TXTAG12 (# 979) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_TXTAG_SIZE}, /* RA01_TXTAG13 (# 980) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SIZE}, /* RA01_TXTAG14 (# 981) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SIZE}, /* RA01_TXTAG15 (# 982) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SIZE}, /* RA01_TXTAG16 (# 983) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_TXTAG_SIZE}, /* RA01_TXTAG17 (# 984) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_TXTAG_SIZE}, /* RA01_TXTAG18 (# 985) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_TXTAG_SIZE}, /* RA01_TXTAG19 (# 986) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_TXTAG_SIZE}, /* RA01_TXTAG20 (# 987) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_TXTAG_SIZE}, /* RA01_TXTAG21 (# 988) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SIZE}, /* RA01_TXTAG22 (# 989) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SIZE}, /* RA01_TXTAG23 (# 990) */ { (IFX_uint16_t)RA01_TXTAG, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_TXTAG_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SIZE}, /* RA01_VALID (# 991) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_01_00_RA01_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_01_00_RA01_VALID_SIZE}, /* RA01_VALID1 (# 992) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_03_02_RA23_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_03_02_RA23_VALID_SIZE}, /* RA01_VALID2 (# 993) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_05_04_RA45_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_05_04_RA45_VALID_SIZE}, /* RA01_VALID3 (# 994) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_07_06_RA67_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_07_06_RA67_VALID_SIZE}, /* RA01_VALID4 (# 995) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_09_08_RA89_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_09_08_RA89_VALID_SIZE}, /* RA01_VALID5 (# 996) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_0B_0A_RA1101_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0B_0A_RA1101_VALID_SIZE}, /* RA01_VALID6 (# 997) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_0D_0C_RA1321_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0D_0C_RA1321_VALID_SIZE}, /* RA01_VALID7 (# 998) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_0F_0E_RA1541_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_0F_0E_RA1541_VALID_SIZE}, /* RA01_VALID8 (# 999) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_11_10_RA1761_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_11_10_RA1761_VALID_SIZE}, /* RA01_VALID9 (# 1000) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_13_12_RA1981_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_13_12_RA1981_VALID_SIZE}, /* RA01_VALID10 (# 1001) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_15_14_RA2021_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_15_14_RA2021_VALID_SIZE}, /* RA01_VALID11 (# 1002) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_17_16_RA2223_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_17_16_RA2223_VALID_SIZE}, /* RA01_VALID12 (# 1003) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_19_18_RA2425_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_19_18_RA2425_VALID_SIZE}, /* RA01_VALID13 (# 1004) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_1B_1A_RA2627_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1B_1A_RA2627_VALID_SIZE}, /* RA01_VALID14 (# 1005) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_1D_1C_RA2829_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1D_1C_RA2829_VALID_SIZE}, /* RA01_VALID15 (# 1006) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_1F_1E_RA3031_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_1F_1E_RA3031_VALID_SIZE}, /* RA01_VALID16 (# 1007) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_21_20_RA3233_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_21_20_RA3233_VALID_SIZE}, /* RA01_VALID17 (# 1008) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_23_22_RA3435_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_23_22_RA3435_VALID_SIZE}, /* RA01_VALID18 (# 1009) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_25_24_RA3637_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_25_24_RA3637_VALID_SIZE}, /* RA01_VALID19 (# 1010) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_27_26_RA3839_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_27_26_RA3839_VALID_SIZE}, /* RA01_VALID20 (# 1011) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_29_28_RA4041_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_29_28_RA4041_VALID_SIZE}, /* RA01_VALID21 (# 1012) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_2B_2A_RA4243_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2B_2A_RA4243_VALID_SIZE}, /* RA01_VALID22 (# 1013) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_2D_2C_RA4445_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2D_2C_RA4445_VALID_SIZE}, /* RA01_VALID23 (# 1014) */ { (IFX_uint16_t)RA01_VALID, (IFX_uint16_t)TANTOS_3G_RA_2F_2E_RA4647_VALID_OFFSET, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_VALID_SHIFT, (IFX_uint8_t)TANTOS_3G_RA_2F_2E_RA4647_VALID_SIZE}, /* RA02_ACT (# 1015) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT1 (# 1016) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT2 (# 1017) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT3 (# 1018) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT4 (# 1019) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT5 (# 1020) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT6 (# 1021) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT7 (# 1022) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT8 (# 1023) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT9 (# 1024) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT10 (# 1025) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_ACT11 (# 1026) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV (# 1027) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV1 (# 1028) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV2 (# 1029) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV3 (# 1030) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV4 (# 1031) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV5 (# 1032) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV6 (# 1033) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV7 (# 1034) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV8 (# 1035) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV9 (# 1036) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV10 (# 1037) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_CV11 (# 1038) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG (# 1039) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG1 (# 1040) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG2 (# 1041) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG3 (# 1042) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG4 (# 1043) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG5 (# 1044) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG6 (# 1045) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG7 (# 1046) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG8 (# 1047) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG9 (# 1048) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG10 (# 1049) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_MG11 (# 1050) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN (# 1051) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN1 (# 1052) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN2 (# 1053) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN3 (# 1054) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN4 (# 1055) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN5 (# 1056) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN6 (# 1057) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN7 (# 1058) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN8 (# 1059) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN9 (# 1060) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN10 (# 1061) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_SPAN11 (# 1062) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG (# 1063) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG1 (# 1064) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG2 (# 1065) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG3 (# 1066) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG4 (# 1067) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG5 (# 1068) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG6 (# 1069) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG7 (# 1070) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG8 (# 1071) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG9 (# 1072) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG10 (# 1073) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_TXTAG11 (# 1074) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID (# 1075) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID1 (# 1076) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID2 (# 1077) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID3 (# 1078) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID4 (# 1079) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID5 (# 1080) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID6 (# 1081) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID7 (# 1082) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID8 (# 1083) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID9 (# 1084) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID10 (# 1085) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA02_VALID11 (# 1086) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT (# 1087) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT1 (# 1088) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT2 (# 1089) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT3 (# 1090) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT4 (# 1091) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT5 (# 1092) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT6 (# 1093) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT7 (# 1094) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT8 (# 1095) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT9 (# 1096) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT10 (# 1097) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_ACT11 (# 1098) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV (# 1099) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV1 (# 1100) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV2 (# 1101) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV3 (# 1102) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV4 (# 1103) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV5 (# 1104) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV6 (# 1105) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV7 (# 1106) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV8 (# 1107) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV9 (# 1108) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV10 (# 1109) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_CV11 (# 1110) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG (# 1111) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG1 (# 1112) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG2 (# 1113) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG3 (# 1114) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG4 (# 1115) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG5 (# 1116) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG6 (# 1117) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG7 (# 1118) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG8 (# 1119) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG9 (# 1120) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG10 (# 1121) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_MG11 (# 1122) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN (# 1123) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN1 (# 1124) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN2 (# 1125) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN3 (# 1126) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN4 (# 1127) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN5 (# 1128) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN6 (# 1129) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN7 (# 1130) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN8 (# 1131) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN9 (# 1132) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN10 (# 1133) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_SPAN11 (# 1134) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG (# 1135) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG1 (# 1136) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG2 (# 1137) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG3 (# 1138) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG4 (# 1139) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG5 (# 1140) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG6 (# 1141) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG7 (# 1142) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG8 (# 1143) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG9 (# 1144) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG10 (# 1145) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_TXTAG11 (# 1146) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID (# 1147) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID1 (# 1148) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID2 (# 1149) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID3 (# 1150) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID4 (# 1151) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID5 (# 1152) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID6 (# 1153) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID7 (# 1154) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID8 (# 1155) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID9 (# 1156) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID10 (# 1157) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RA03_VALID11 (# 1158) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RMON_BAS (# 1159) */ { (IFX_uint16_t)RMON_BAS, (IFX_uint16_t)TANTOS_3G_RCC_BAS_OFFSET, (IFX_uint8_t)TANTOS_3G_RCC_BAS_SHIFT, (IFX_uint8_t)TANTOS_3G_RCC_BAS_SIZE}, /* RMON_CAC (# 1160) */ { (IFX_uint16_t)RMON_CAC, (IFX_uint16_t)TANTOS_3G_RCC_CAC_OFFSET, (IFX_uint8_t)TANTOS_3G_RCC_CAC_SHIFT, (IFX_uint8_t)TANTOS_3G_RCC_CAC_SIZE}, /* RMON_COUNTER (# 1161) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* RMON_HIGH_COUNTER (# 1162) */ { (IFX_uint16_t)RMON_HIGH_COUNTER, (IFX_uint16_t)TANTOS_3G_RCSH_COUNTER_OFFSET, (IFX_uint8_t)TANTOS_3G_RCSH_COUNTER_SHIFT, (IFX_uint8_t)TANTOS_3G_RCSH_COUNTER_SIZE}, /* RMON_LOW_COUNTER (# 1163) */ { (IFX_uint16_t)RMON_LOW_COUNTER, (IFX_uint16_t)TANTOS_3G_RCSL_COUNTER_OFFSET, (IFX_uint8_t)TANTOS_3G_RCSL_COUNTER_SHIFT, (IFX_uint8_t)TANTOS_3G_RCSL_COUNTER_SIZE}, /* RMON_OFFSET (# 1164) */ { (IFX_uint16_t)RMON_OFFSET, (IFX_uint16_t)TANTOS_3G_RCC_OFFSET_OFFSET, (IFX_uint8_t)TANTOS_3G_RCC_OFFSET_SHIFT, (IFX_uint8_t)TANTOS_3G_RCC_OFFSET_SIZE}, /* RMON_PORTC (# 1165) */ { (IFX_uint16_t)RMON_PORTC, (IFX_uint16_t)TANTOS_3G_RCC_PORTC_OFFSET, (IFX_uint8_t)TANTOS_3G_RCC_PORTC_SHIFT, (IFX_uint8_t)TANTOS_3G_RCC_PORTC_SIZE}, /* TYPE_FILTER_ATF (# 1166) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF0_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF0_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF0_SIZE}, /* TYPE_FILTER_ATF1 (# 1167) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF1_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF1_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF1_SIZE}, /* TYPE_FILTER_ATF2 (# 1168) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF2_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF2_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF2_SIZE}, /* TYPE_FILTER_ATF3 (# 1169) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF3_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF3_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF3_SIZE}, /* TYPE_FILTER_ATF4 (# 1170) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF4_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF4_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF4_SIZE}, /* TYPE_FILTER_ATF5 (# 1171) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF5_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF5_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF5_SIZE}, /* TYPE_FILTER_ATF6 (# 1172) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF6_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF6_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF6_SIZE}, /* TYPE_FILTER_ATF7 (# 1173) */ { (IFX_uint16_t)TYPE_FILTER_ATF, (IFX_uint16_t)TANTOS_3G_TFA0_ATF7_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA0_ATF7_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA0_ATF7_SIZE}, /* TYPE_FILTER_QTF (# 1174) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF0_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF0_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF0_SIZE}, /* TYPE_FILTER_QTF1 (# 1175) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF1_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF1_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF1_SIZE}, /* TYPE_FILTER_QTF2 (# 1176) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF2_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF2_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF2_SIZE}, /* TYPE_FILTER_QTF3 (# 1177) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF3_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF3_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF3_SIZE}, /* TYPE_FILTER_QTF4 (# 1178) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF4_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF4_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF4_SIZE}, /* TYPE_FILTER_QTF5 (# 1179) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QTF5_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QTF5_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QTF5_SIZE}, /* TYPE_FILTER_QTF6 (# 1180) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QATF6_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QATF6_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QATF6_SIZE}, /* TYPE_FILTER_QTF7 (# 1181) */ { (IFX_uint16_t)TYPE_FILTER_QTF, (IFX_uint16_t)TANTOS_3G_TFA1_QATF7_OFFSET, (IFX_uint8_t)TANTOS_3G_TFA1_QATF7_SHIFT, (IFX_uint8_t)TANTOS_3G_TFA1_QATF7_SIZE}, /* TYPE_FILTER_VCET0 (# 1182) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET01 (# 1183) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET02 (# 1184) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET03 (# 1185) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET1 (# 1186) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET11 (# 1187) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET12 (# 1188) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET13 (# 1189) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0}, /* TYPE_FILTER_VCET_ALL (# 1190) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF0_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF0_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF0_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL1 (# 1191) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF1_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF1_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF1_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL2 (# 1192) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF2_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF2_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF2_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL3 (# 1193) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF3_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF3_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF3_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL4 (# 1194) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF4_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF4_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF4_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL5 (# 1195) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF5_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF5_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF5_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL6 (# 1196) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF6_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF6_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF6_VCET_SIZE}, /* TYPE_FILTER_VCET_ALL7 (# 1197) */ { (IFX_uint16_t)TYPE_FILTER_VCET_ALL, (IFX_uint16_t)TANTOS_3G_TF7_VCET_OFFSET, (IFX_uint8_t)TANTOS_3G_TF7_VCET_SHIFT, (IFX_uint8_t)TANTOS_3G_TF7_VCET_SIZE}, /* VLAN_FILTER_M (# 1198) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF0H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0H_M_SIZE}, /* VLAN_FILTER_M1 (# 1199) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF1H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1H_M_SIZE}, /* VLAN_FILTER_M2 (# 1200) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF2H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2H_M_SIZE}, /* VLAN_FILTER_M3 (# 1201) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF3H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3H_M_SIZE}, /* VLAN_FILTER_M4 (# 1202) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF4H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4H_M_SIZE}, /* VLAN_FILTER_M5 (# 1203) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF5H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5H_M_SIZE}, /* VLAN_FILTER_M6 (# 1204) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF6H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6H_M_SIZE}, /* VLAN_FILTER_M7 (# 1205) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF7H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7H_M_SIZE}, /* VLAN_FILTER_M8 (# 1206) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF8H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8H_M_SIZE}, /* VLAN_FILTER_M9 (# 1207) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF9H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9H_M_SIZE}, /* VLAN_FILTER_M10 (# 1208) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF10H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10H_M_SIZE}, /* VLAN_FILTER_M11 (# 1209) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF11H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11H_M_SIZE}, /* VLAN_FILTER_M12 (# 1210) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF12H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12H_M_SIZE}, /* VLAN_FILTER_M13 (# 1211) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF13H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13H_M_SIZE}, /* VLAN_FILTER_M14 (# 1212) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF14H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14H_M_SIZE}, /* VLAN_FILTER_M15 (# 1213) */ { (IFX_uint16_t)VLAN_FILTER_M, (IFX_uint16_t)TANTOS_3G_VF15H_M_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15H_M_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15H_M_SIZE}, /* VLAN_FILTER_TM (# 1214) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF0H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0H_TM_SIZE}, /* VLAN_FILTER_TM1 (# 1215) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF1H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1H_TM_SIZE}, /* VLAN_FILTER_TM2 (# 1216) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF2H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2H_TM_SIZE}, /* VLAN_FILTER_TM3 (# 1217) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF3H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3H_TM_SIZE}, /* VLAN_FILTER_TM4 (# 1218) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF4H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4H_TM_SIZE}, /* VLAN_FILTER_TM5 (# 1219) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF5H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5H_TM_SIZE}, /* VLAN_FILTER_TM6 (# 1220) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF6H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6H_TM_SIZE}, /* VLAN_FILTER_TM7 (# 1221) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF7H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7H_TM_SIZE}, /* VLAN_FILTER_TM8 (# 1222) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF8H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8H_TM_SIZE}, /* VLAN_FILTER_TM9 (# 1223) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF9H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9H_TM_SIZE}, /* VLAN_FILTER_TM10 (# 1224) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF10H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10H_TM_SIZE}, /* VLAN_FILTER_TM11 (# 1225) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF11H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11H_TM_SIZE}, /* VLAN_FILTER_TM12 (# 1226) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF12H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12H_TM_SIZE}, /* VLAN_FILTER_TM13 (# 1227) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF13H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13H_TM_SIZE}, /* VLAN_FILTER_TM14 (# 1228) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF14H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14H_TM_SIZE}, /* VLAN_FILTER_TM15 (# 1229) */ { (IFX_uint16_t)VLAN_FILTER_TM, (IFX_uint16_t)TANTOS_3G_VF15H_TM_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15H_TM_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15H_TM_SIZE}, /* VLAN_FILTER_VFID (# 1230) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF0H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0H_FID_SIZE}, /* VLAN_FILTER_VFID1 (# 1231) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF1H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1H_FID_SIZE}, /* VLAN_FILTER_VFID2 (# 1232) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF2H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2H_FID_SIZE}, /* VLAN_FILTER_VFID3 (# 1233) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF3H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3H_FID_SIZE}, /* VLAN_FILTER_VFID4 (# 1234) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF4H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4H_FID_SIZE}, /* VLAN_FILTER_VFID5 (# 1235) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF5H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5H_FID_SIZE}, /* VLAN_FILTER_VFID6 (# 1236) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF6H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6H_FID_SIZE}, /* VLAN_FILTER_VFID7 (# 1237) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF7H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7H_FID_SIZE}, /* VLAN_FILTER_VFID8 (# 1238) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF8H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8H_FID_SIZE}, /* VLAN_FILTER_VFID9 (# 1239) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF9H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9H_FID_SIZE}, /* VLAN_FILTER_VFID10 (# 1240) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF10H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10H_FID_SIZE}, /* VLAN_FILTER_VFID11 (# 1241) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF11H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11H_FID_SIZE}, /* VLAN_FILTER_VFID12 (# 1242) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF12H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12H_FID_SIZE}, /* VLAN_FILTER_VFID13 (# 1243) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF13H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13H_FID_SIZE}, /* VLAN_FILTER_VFID14 (# 1244) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF14H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14H_FID_SIZE}, /* VLAN_FILTER_VFID15 (# 1245) */ { (IFX_uint16_t)VLAN_FILTER_VFID, (IFX_uint16_t)TANTOS_3G_VF15H_FID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15H_FID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15H_FID_SIZE}, /* VLAN_FILTER_VID (# 1246) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF0L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0L_VID_SIZE}, /* VLAN_FILTER_VID1 (# 1247) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF1L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1L_VID_SIZE}, /* VLAN_FILTER_VID2 (# 1248) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF2L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2L_VID_SIZE}, /* VLAN_FILTER_VID3 (# 1249) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF3L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3L_VID_SIZE}, /* VLAN_FILTER_VID4 (# 1250) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF4L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4L_VID_SIZE}, /* VLAN_FILTER_VID5 (# 1251) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF5L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5L_VID_SIZE}, /* VLAN_FILTER_VID6 (# 1252) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF6L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6L_VID_SIZE}, /* VLAN_FILTER_VID7 (# 1253) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF7L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7L_VID_SIZE}, /* VLAN_FILTER_VID8 (# 1254) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF8L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8L_VID_SIZE}, /* VLAN_FILTER_VID9 (# 1255) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF9L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9L_VID_SIZE}, /* VLAN_FILTER_VID10 (# 1256) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF10L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10L_VID_SIZE}, /* VLAN_FILTER_VID11 (# 1257) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF11L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11L_VID_SIZE}, /* VLAN_FILTER_VID12 (# 1258) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF12L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12L_VID_SIZE}, /* VLAN_FILTER_VID13 (# 1259) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF13L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13L_VID_SIZE}, /* VLAN_FILTER_VID14 (# 1260) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF14L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14L_VID_SIZE}, /* VLAN_FILTER_VID15 (# 1261) */ { (IFX_uint16_t)VLAN_FILTER_VID, (IFX_uint16_t)TANTOS_3G_VF15L_VID_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15L_VID_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15L_VID_SIZE}, /* VLAN_FILTER_VP (# 1262) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF0L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0L_VP_SIZE}, /* VLAN_FILTER_VP1 (# 1263) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF1L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1L_VP_SIZE}, /* VLAN_FILTER_VP2 (# 1264) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF2L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2L_VP_SIZE}, /* VLAN_FILTER_VP3 (# 1265) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF3L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3L_VP_SIZE}, /* VLAN_FILTER_VP4 (# 1266) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF4L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4L_VP_SIZE}, /* VLAN_FILTER_VP5 (# 1267) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF5L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5L_VP_SIZE}, /* VLAN_FILTER_VP6 (# 1268) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF6L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6L_VP_SIZE}, /* VLAN_FILTER_VP7 (# 1269) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF7L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7L_VP_SIZE}, /* VLAN_FILTER_VP8 (# 1270) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF8L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8L_VP_SIZE}, /* VLAN_FILTER_VP9 (# 1271) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF9L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9L_VP_SIZE}, /* VLAN_FILTER_VP10 (# 1272) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF10L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10L_VP_SIZE}, /* VLAN_FILTER_VP11 (# 1273) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF11L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11L_VP_SIZE}, /* VLAN_FILTER_VP12 (# 1274) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF12L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12L_VP_SIZE}, /* VLAN_FILTER_VP13 (# 1275) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF13L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13L_VP_SIZE}, /* VLAN_FILTER_VP14 (# 1276) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF14L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14L_VP_SIZE}, /* VLAN_FILTER_VP15 (# 1277) */ { (IFX_uint16_t)VLAN_FILTER_VP, (IFX_uint16_t)TANTOS_3G_VF15L_VP_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15L_VP_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15L_VP_SIZE}, /* VLAN_FILTER_VV (# 1278) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF0L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF0L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF0L_VV_SIZE}, /* VLAN_FILTER_VV1 (# 1279) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF1L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF1L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF1L_VV_SIZE}, /* VLAN_FILTER_VV2 (# 1280) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF2L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF2L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF2L_VV_SIZE}, /* VLAN_FILTER_VV3 (# 1281) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF3L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF3L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF3L_VV_SIZE}, /* VLAN_FILTER_VV4 (# 1282) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF4L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF4L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF4L_VV_SIZE}, /* VLAN_FILTER_VV5 (# 1283) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF5L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF5L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF5L_VV_SIZE}, /* VLAN_FILTER_VV6 (# 1284) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF6L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF6L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF6L_VV_SIZE}, /* VLAN_FILTER_VV7 (# 1285) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF7L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF7L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF7L_VV_SIZE}, /* VLAN_FILTER_VV8 (# 1286) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF8L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF8L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF8L_VV_SIZE}, /* VLAN_FILTER_VV9 (# 1287) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF9L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF9L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF9L_VV_SIZE}, /* VLAN_FILTER_VV10 (# 1288) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF10L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF10L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF10L_VV_SIZE}, /* VLAN_FILTER_VV11 (# 1289) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF11L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF11L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF11L_VV_SIZE}, /* VLAN_FILTER_VV12 (# 1290) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF12L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF12L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF12L_VV_SIZE}, /* VLAN_FILTER_VV13 (# 1291) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF13L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF13L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF13L_VV_SIZE}, /* VLAN_FILTER_VV14 (# 1292) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF14L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF14L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF14L_VV_SIZE}, /* VLAN_FILTER_VV15 (# 1293) */ { (IFX_uint16_t)VLAN_FILTER_VV, (IFX_uint16_t)TANTOS_3G_VF15L_VV_OFFSET, (IFX_uint8_t)TANTOS_3G_VF15L_VV_SHIFT, (IFX_uint8_t)TANTOS_3G_VF15L_VV_SIZE}, /* Last Element (# 1294) */ { (IFX_uint16_t)COMMON_BIT_LATEST , (IFX_uint16_t)0, (IFX_uint8_t)0, (IFX_uint8_t)0} }; #ifdef IFX_ETHSW_DEBUG char regMapper_TANTOS_3G_Names = [] = { "AR.APT" /* ARP_APT (# 0) */, "AR.MACA" /* ARP_MACA (# 1) */, "AR.RAPA" /* ARP_RAPA (# 2) */, "AR.RAPOTH" /* ARP_RAPOTH (# 3) */, "AR.RAPP" /* ARP_RAPP (# 4) */, "AR.RAPPE" /* ARP_RAPPE (# 5) */, "AR.RAPTM" /* ARP_RAPTM (# 6) */, "AR.RPT" /* ARP_RPT (# 7) */, "AR.TAP" /* ARP_TAP (# 8) */, "AR.TAPTS" /* ARP_TAPTS (# 9) */, "AR.TRP" /* ARP_TRP (# 10) */, "AR.UPT" /* ARP_UPT (# 11) */, "GSHS.CTBR" /* BIST_CTBR (# 12) */, "GSHS.DBBR" /* BIST_DBBR (# 13) */, NULL /* BIST_DONE (# 14) */, "GSHS.HIGTBR" /* BIST_HIGTBR (# 15) */, "GSHS.HISTBR" /* BIST_HISTBR (# 16) */, "GSHS.LLTBR" /* BIST_LLTBR (# 17) */, "GSHS.LTBR" /* BIST_LTBR (# 18) */, NULL /* BUFFER_PFA (# 19) */, NULL /* BUFFER_PFO0 (# 20) */, NULL /* BUFFER_PFO1 (# 21) */, NULL /* BUFFER_PFO2 (# 22) */, NULL /* BUFFER_PUA (# 23) */, NULL /* BUFFER_PUO0 (# 24) */, NULL /* BUFFER_PUO1 (# 25) */, NULL /* BUFFER_PUO2 (# 26) */, NULL /* BUFFER_THA (# 27) */, NULL /* BUFFER_THO (# 28) */, NULL /* BUFFER_TLA (# 29) */, NULL /* BUFFER_TLO (# 30) */, "CI0.BOND" /* CHIPID_BOND (# 31) */, "CI1.PC" /* CHIPID_PC (# 32) */, "CI0.VN" /* CHIPID_VN (# 33) */, "CCR.EDSTX" /* CONGESTION_EDSTX (# 34) */, "CCR.IJT" /* CONGESTION_IJT (# 35) */, "CCR.IRSJA" /* CONGESTION_IRSJA (# 36) */, "SCR0.STORM_100_TH" /* CONGESTION_STORM_100_TH (# 37) */, "SCR1.STORM_10_TH" /* CONGESTION_STORM_10_TH (# 38) */, "SCR0.STORM_B" /* CONGESTION_STORM_B (# 39) */, "SCR0.STORM_M" /* CONGESTION_STORM_M (# 40) */, "SCR0.STORM_U" /* CONGESTION_STORM_U (# 41) */, "DM0.PQ0" /* DIFFSERV_PQA (# 42) */, "DM0.PQ1" /* DIFFSERV_PQA01 (# 43) */, "DM0.PQ2" /* DIFFSERV_PQA02 (# 44) */, "DM0.PQ3" /* DIFFSERV_PQA03 (# 45) */, "DM0.PQ4" /* DIFFSERV_PQA04 (# 46) */, "DM0.PQ5" /* DIFFSERV_PQA05 (# 47) */, "DM0.PQ6" /* DIFFSERV_PQA06 (# 48) */, "DM0.PQ7" /* DIFFSERV_PQA07 (# 49) */, "DM1.PQ8" /* DIFFSERV_PQA08 (# 50) */, "DM1.PQ9" /* DIFFSERV_PQA09 (# 51) */, "DM1.PQA" /* DIFFSERV_PQA10 (# 52) */, "DM1.PQB" /* DIFFSERV_PQA11 (# 53) */, "DM1.PQC" /* DIFFSERV_PQA12 (# 54) */, "DM1.PQD" /* DIFFSERV_PQA13 (# 55) */, "DM1.PQE" /* DIFFSERV_PQA14 (# 56) */, "DM1.PQF" /* DIFFSERV_PQA15 (# 57) */, "DM2.PQ10" /* DIFFSERV_PQB (# 58) */, "DM2.PQ11" /* DIFFSERV_PQB01 (# 59) */, "DM2.PQ12" /* DIFFSERV_PQB02 (# 60) */, "DM2.PQ13" /* DIFFSERV_PQB03 (# 61) */, "DM2.PQ14" /* DIFFSERV_PQB04 (# 62) */, "DM2.PQ15" /* DIFFSERV_PQB05 (# 63) */, "DM2.PQ16" /* DIFFSERV_PQB06 (# 64) */, "DM2.PQ17" /* DIFFSERV_PQB07 (# 65) */, "DM3.PQ18" /* DIFFSERV_PQB08 (# 66) */, "DM3.PQ19" /* DIFFSERV_PQB09 (# 67) */, "DM3.PQ1A" /* DIFFSERV_PQB10 (# 68) */, "DM3.PQ1B" /* DIFFSERV_PQB11 (# 69) */, "DM3.PQ1C" /* DIFFSERV_PQB12 (# 70) */, "DM3.PQ1D" /* DIFFSERV_PQB13 (# 71) */, "DM3.PQ1E" /* DIFFSERV_PQB14 (# 72) */, "DM3.PQ1F" /* DIFFSERV_PQB15 (# 73) */, "DM4.PQ20" /* DIFFSERV_PQC (# 74) */, "DM4.PQ21" /* DIFFSERV_PQC01 (# 75) */, "DM4.PQ22" /* DIFFSERV_PQC02 (# 76) */, "DM4.PQ23" /* DIFFSERV_PQC03 (# 77) */, "DM4.PQ24" /* DIFFSERV_PQC04 (# 78) */, "DM4.PQ25" /* DIFFSERV_PQC05 (# 79) */, "DM4.PQ26" /* DIFFSERV_PQC06 (# 80) */, "DM4.PQ27" /* DIFFSERV_PQC07 (# 81) */, "DM5.PQ28" /* DIFFSERV_PQC08 (# 82) */, "DM5.PQ29" /* DIFFSERV_PQC09 (# 83) */, "DM5.PQ2A" /* DIFFSERV_PQC10 (# 84) */, "DM5.PQ2B" /* DIFFSERV_PQC11 (# 85) */, "DM5.PQ2C" /* DIFFSERV_PQC12 (# 86) */, "DM5.PQ2D" /* DIFFSERV_PQC13 (# 87) */, "DM5.PQ2E" /* DIFFSERV_PQC14 (# 88) */, "DM5.PQ2F" /* DIFFSERV_PQC15 (# 89) */, "DM6.PQ30" /* DIFFSERV_PQD (# 90) */, "DM6.PQ31" /* DIFFSERV_PQD01 (# 91) */, "DM6.PQ32" /* DIFFSERV_PQD02 (# 92) */, "DM6.PQ33" /* DIFFSERV_PQD03 (# 93) */, "DM6.PQ34" /* DIFFSERV_PQD04 (# 94) */, "DM6.PQ35" /* DIFFSERV_PQD05 (# 95) */, "DM6.PQ36" /* DIFFSERV_PQD06 (# 96) */, "DM6.PQ37" /* DIFFSERV_PQD07 (# 97) */, "DM7.PQ38" /* DIFFSERV_PQD08 (# 98) */, "DM7.PQ39" /* DIFFSERV_PQD09 (# 99) */, "DM7.PQ3A" /* DIFFSERV_PQD10 (# 100) */, "DM7.PQ3B" /* DIFFSERV_PQD11 (# 101) */, "DM7.PQ3C" /* DIFFSERV_PQD12 (# 102) */, "DM7.PQ3D" /* DIFFSERV_PQD13 (# 103) */, "DM7.PQ3E" /* DIFFSERV_PQD14 (# 104) */, "DM7.PQ3F" /* DIFFSERV_PQD15 (# 105) */, "1PPM.1PPQ0" /* DOT1X_PRIORITY_1PPQ (# 106) */, "1PPM.1PPQ1" /* DOT1X_PRIORITY_1PPQ1 (# 107) */, "1PPM.1PPQ2" /* DOT1X_PRIORITY_1PPQ2 (# 108) */, "1PPM.1PPQ3" /* DOT1X_PRIORITY_1PPQ3 (# 109) */, "1PPM.1PPQ4" /* DOT1X_PRIORITY_1PPQ4 (# 110) */, "1PPM.1PPQ5" /* DOT1X_PRIORITY_1PPQ5 (# 111) */, "1PPM.1PPQ6" /* DOT1X_PRIORITY_1PPQ6 (# 112) */, "1PPM.1PPQ7" /* DOT1X_PRIORITY_1PPQ7 (# 113) */, "SGC1.ATS" /* GLOBAL_ATS (# 114) */, NULL /* GLOBAL_CTTX (# 115) */, "PIOFGPM.DIE" /* GLOBAL_DIE (# 116) */, "PIOFGPM.DII6P" /* GLOBAL_DII6P (# 117) */, "PIOFGPM.DIIP" /* GLOBAL_DIIP (# 118) */, "PIOFGPM.DIIPS" /* GLOBAL_DIIPS (# 119) */, "PIOFGPM.DIS" /* GLOBAL_DIS (# 120) */, "PIOFGPM.DIVS" /* GLOBAL_DIVS (# 121) */, "SGC1.DMQ0" /* GLOBAL_DMQ0 (# 122) */, "SGC1.DMQ1" /* GLOBAL_DMQ1 (# 123) */, "SGC1.DMQ2" /* GLOBAL_DMQ2 (# 124) */, "SGC1.DMQ3" /* GLOBAL_DMQ3 (# 125) */, "SGC1.DPWECH" /* GLOBAL_DPWECH (# 126) */, "SGC2.DUPCOLSP" /* GLOBAL_DUPCOLSP (# 127) */, "SGC2.ICRCCD" /* GLOBAL_ICRCCD (# 128) */, "SGC2.ITENLMT" /* GLOBAL_ITENLMT (# 129) */, "SGC2.ITRUNK" /* GLOBAL_ITRUNK (# 130) */, NULL /* GLOBAL_LPE (# 131) */, "SGC1.MPL" /* GLOBAL_MPL (# 132) */, "GSHS.P4M" /* GLOBAL_P4M (# 133) */, "GSHS.P5M" /* GLOBAL_P5M (# 134) */, "GSHS.P6M" /* GLOBAL_P6M (# 135) */, "SGC2.PCE" /* GLOBAL_PCE (# 136) */, "SGC2.PCR" /* GLOBAL_PCR (# 137) */, "SGC1.PHYBA" /* GLOBAL_PHYBA (# 138) */, "SGC2.RVID0" /* GLOBAL_RVID0 (# 139) */, "SGC2.RVID1" /* GLOBAL_RVID1 (# 140) */, "SGC2.RVIDFFF" /* GLOBAL_RVIDFFF (# 141) */, "SGC2.SE" /* GLOBAL_SE (# 142) */, "SGC1.TSIPGE" /* GLOBAL_TSIPGE (# 143) */, NULL /* INGRESS_FLOW_CTRL_B (# 144) */, "GBSBC.Base15_0" /* INGRESS_FLOW_CTRL_BASE15_0 (# 145) */, "GBSCHB.Base17_16" /* INGRESS_FLOW_CTRL_BASE17_16 (# 146) */, "GBSEBC.EBase15_0" /* INGRESS_FLOW_CTRL_EBASE15_0 (# 147) */, "GBSCHB.EBase17_16" /* INGRESS_FLOW_CTRL_EBASE17_16 (# 148) */, NULL /* INGRESS_FLOW_CTRL_F (# 149) */, NULL /* IRQ_DBF (# 150) */, NULL /* IRQ_DBFIE (# 151) */, NULL /* IRQ_DBNF (# 152) */, NULL /* IRQ_DBNFIE (# 153) */, "IS.LTAD" /* IRQ_LTAD (# 154) */, "IE.LTADIE" /* IRQ_LTADIE (# 155) */, NULL /* IRQ_LTF (# 156) */, NULL /* IRQ_LTFIE (# 157) */, "IS.PSC" /* IRQ_PSC (# 158) */, "IE.PSCIE" /* IRQ_PSCIE (# 159) */, "IS.PSV" /* IRQ_PSV (# 160) */, "IE.PSVIE" /* IRQ_PSVIE (# 161) */, "ATC0.ADDR15_0" /* MAC_TABLE_ADDR15_0 (# 162) */, NULL /* MAC_TABLE_ADDR31_0 (# 163) */, "ATC1.ADDR31_16" /* MAC_TABLE_ADDR31_16 (# 164) */, "ATC2.ADDR47_32" /* MAC_TABLE_ADDR47_32 (# 165) */, "ATS0.ADDRS15_0" /* MAC_TABLE_ADDRS15_0 (# 166) */, NULL /* MAC_TABLE_ADDRS31_0 (# 167) */, "ATS1.ADDRS31_16" /* MAC_TABLE_ADDRS31_16 (# 168) */, "ATS2.ADDRS47_32" /* MAC_TABLE_ADDRS47_32 (# 169) */, "ATS4.BAD" /* MAC_TABLE_BAD (# 170) */, "ATS5.BUSY" /* MAC_TABLE_BUSY (# 171) */, "ATC5.AC" /* MAC_TABLE_C_AC (# 172) */, "ATC5.CMD" /* MAC_TABLE_C_CMD (# 173) */, "ATC5.FCE" /* MAC_TABLE_C_FCE (# 174) */, "ATC3.FID" /* MAC_TABLE_FID (# 175) */, "ATS3.FIDS" /* MAC_TABLE_FIDS (# 176) */, "ATC4.INFOT" /* MAC_TABLE_INFOT (# 177) */, "ATS4.INFOTS" /* MAC_TABLE_INFOTS (# 178) */, "ATC4.ITAT" /* MAC_TABLE_ITAT (# 179) */, "ATS4.ITATS" /* MAC_TABLE_ITATS (# 180) */, "ATS4.OCP" /* MAC_TABLE_OCP (# 181) */, "ATC3.PMAP" /* MAC_TABLE_PMAP (# 182) */, "ATS3.PMAPS" /* MAC_TABLE_PMAPS (# 183) */, "ATS5.RSLT" /* MAC_TABLE_RSLT (# 184) */, "ATS5.AC" /* MAC_TABLE_S_AC (# 185) */, "ATS5.CMD" /* MAC_TABLE_S_CMD (# 186) */, "ATS5.FCE" /* MAC_TABLE_S_FCE (# 187) */, "MCSR.MCS" /* MCS (# 188) */, "MIIAC.MBUSY" /* MDIO_MBUSY (# 189) */, "MIIAC.OP" /* MDIO_OP (# 190) */, "MIIAC.PHYAD" /* MDIO_PHYAD (# 191) */, "MIIRD.RD" /* MDIO_RD (# 192) */, "MIIAC.REGAD" /* MDIO_REGAD (# 193) */, "MIIWD.WD" /* MDIO_WD (# 194) */, "CMH.CCCRC" /* MIRROR_CCCRC (# 195) */, "CMH.CPN" /* MIRROR_CPN (# 196) */, "CMH.IGSTA" /* MIRROR_IGSTA (# 197) */, "CMH.MCA" /* MIRROR_MCA (# 198) */, "CMH.MLA" /* MIRROR_MLA (# 199) */, "CMH.MPA" /* MIRROR_MPA (# 200) */, "CMH.MRA" /* MIRROR_MRA (# 201) */, "CMH.MSA" /* MIRROR_MSA (# 202) */, "CMH.PAST" /* MIRROR_PAST (# 203) */, "CMH.SPN" /* MIRROR_SNIFFPN (# 204) */, "CMH.STRE" /* MIRROR_STRE (# 205) */, "CMH.STTE" /* MIRROR_STTE (# 206) */, "MS.ASC" /* MULTICAST_ASC (# 207) */, "HIOR.B01" /* MULTICAST_B01 (# 208) */, "HIOR.B224" /* MULTICAST_B224 (# 209) */, "HIOR.B33" /* MULTICAST_B33 (# 210) */, "HIOR.DAIPS" /* MULTICAST_DAIPS (# 211) */, "HIC.DRP" /* MULTICAST_DRP (# 212) */, "IGMPTC5.FMODE" /* MULTICAST_FMODE (# 213) */, "IGMPTC3.GID15_0" /* MULTICAST_GID15_0 (# 214) */, "IGMPTC4.GID31_16" /* MULTICAST_GID31_16 (# 215) */, "HIC.HIPI" /* MULTICAST_HIPI (# 216) */, "HIOR.HISE" /* MULTICAST_HISE (# 217) */, "HIOR.HISFL" /* MULTICAST_HISFL (# 218) */, "IGMPTC5.ICMD" /* MULTICAST_ICMD (# 219) */, "HIOR.IGMPV3E" /* MULTICAST_IGMPV3E (# 220) */, "IGMPTC5.INVC" /* MULTICAST_INVC (# 221) */, "MS.IPMPT" /* MULTICAST_IPMPT (# 222) */, "IGMPTC5.PORT" /* MULTICAST_PORT (# 223) */, "HIOR.PPPoEHR" /* MULTICAST_PPPOEHR (# 224) */, "HIC.QI" /* MULTICAST_QI (# 225) */, "MS.RV" /* MULTICAST_RV (# 226) */, "IGMPTS3.S3PMI" /* MULTICAST_S3PMI (# 227) */, "IGMPTS3.S3PMV" /* MULTICAST_S3PMV (# 228) */, "IGMPTS4.S4BUSY" /* MULTICAST_S4BUSY (# 229) */, "IGMPTS4.S4R" /* MULTICAST_S4R (# 230) */, "HIOR.SARE" /* MULTICAST_SARE (# 231) */, "MS.SCPA" /* MULTICAST_SCPA (# 232) */, "MS.SCPP" /* MULTICAST_SCPP (# 233) */, "MS.SCPPE" /* MULTICAST_SCPPE (# 234) */, "MS.SCPTCP" /* MULTICAST_SCPTCP (# 235) */, "MS.SCPTMP" /* MULTICAST_SCPTMP (# 236) */, "MS.SCPTSP" /* MULTICAST_SCPTSP (# 237) */, "MS.SCPTTH" /* MULTICAST_SCPTTH (# 238) */, "IGMPTC0.SIP15_0" /* MULTICAST_SIP15_0 (# 239) */, "IGMPTC1.SIP31_16" /* MULTICAST_SIP31_16 (# 240) */, "IGMPTC2.SIP47_32" /* MULTICAST_SIP47_32 (# 241) */, "IGMPTS0.SIPGID0" /* MULTICAST_SIPGID0 (# 242) */, "IGMPTS1.SIPGID1" /* MULTICAST_SIPGID1 (# 243) */, "IGMPTS2.SIPGID2" /* MULTICAST_SIPGID2 (# 244) */, "HIOR.TIMERC" /* MULTICAST_TIMERC (# 245) */, "SMA3.ADDR15_0" /* PAUSE_ADDR15_0 (# 246) */, "SMA2.ADDR31_16" /* PAUSE_ADDR31_16 (# 247) */, "SMA1.ADDR39_32" /* PAUSE_ADDR39_32 (# 248) */, "SMA1.ADDR47_41" /* PAUSE_ADDR47_41 (# 249) */, "SMA1.PAC" /* PAUSE_PAC (# 250) */, "PHYIC0.PHYIE0" /* PHY_INIT_PHYIE0 (# 251) */, "PHYIC1.PHYIE0" /* PHY_INIT_PHYIE01 (# 252) */, "PHYIC2.PHYIE0" /* PHY_INIT_PHYIE02 (# 253) */, "PHYIC3.PHYIE0" /* PHY_INIT_PHYIE03 (# 254) */, "PHYIC0.PHYIE1" /* PHY_INIT_PHYIE1 (# 255) */, "PHYIC1.PHYIE1" /* PHY_INIT_PHYIE11 (# 256) */, "PHYIC2.PHYIE1" /* PHY_INIT_PHYIE12 (# 257) */, "PHYIC3.PHYIE1" /* PHY_INIT_PHYIE13 (# 258) */, "PHYIC0.PHYIE2" /* PHY_INIT_PHYIE2 (# 259) */, "PHYIC1.PHYIE2" /* PHY_INIT_PHYIE21 (# 260) */, "PHYIC2.PHYIE2" /* PHY_INIT_PHYIE22 (# 261) */, "PHYIC3.PHYIE2" /* PHY_INIT_PHYIE23 (# 262) */, "PHYIC0.PHYIE3" /* PHY_INIT_PHYIE3 (# 263) */, "PHYIC1.PHYIE3" /* PHY_INIT_PHYIE31 (# 264) */, "PHYIC2.PHYIE3" /* PHY_INIT_PHYIE32 (# 265) */, "PHYIC3.PHYIE3" /* PHY_INIT_PHYIE33 (# 266) */, "PHYIC0.PHYIE4" /* PHY_INIT_PHYIE4 (# 267) */, "PHYIC1.PHYIE4" /* PHY_INIT_PHYIE41 (# 268) */, "PHYIC2.PHYIE4" /* PHY_INIT_PHYIE42 (# 269) */, "PHYIC3.PHYIE4" /* PHY_INIT_PHYIE43 (# 270) */, "PHYIC0.PHYIE5" /* PHY_INIT_PHYIE5 (# 271) */, "PHYIC1.PHYIE5" /* PHY_INIT_PHYIE51 (# 272) */, "PHYIC2.PHYIE5" /* PHY_INIT_PHYIE52 (# 273) */, "PHYIC3.PHYIE5" /* PHY_INIT_PHYIE53 (# 274) */, "PHYIC0.PHYIE6" /* PHY_INIT_PHYIE6 (# 275) */, "PHYIC1.PHYIE6" /* PHY_INIT_PHYIE61 (# 276) */, "PHYIC2.PHYIE6" /* PHY_INIT_PHYIE62 (# 277) */, "PHYIC3.PHYIE6" /* PHY_INIT_PHYIE63 (# 278) */, "PHYIC0.REGA0" /* PHY_INIT_REGA (# 279) */, "PHYIC1.REGA0" /* PHY_INIT_REGA1 (# 280) */, "PHYIC2.REGA0" /* PHY_INIT_REGA2 (# 281) */, "PHYIC3.REGA0" /* PHY_INIT_REGA3 (# 282) */, "PHYID0.REGD0" /* PHY_INIT_REGD (# 283) */, "PHYID1.REGD1" /* PHY_INIT_REGD1 (# 284) */, "PHYID2.REGD2" /* PHY_INIT_REGD2 (# 285) */, "PHYID3.REGD3" /* PHY_INIT_REGD3 (# 286) */, NULL /* PMAC_ADD (# 287) */, NULL /* PMAC_ADD_CRC (# 288) */, NULL /* PMAC_AS (# 289) */, NULL /* PMAC_CFI (# 290) */, NULL /* PMAC_DA_31_0 (# 291) */, NULL /* PMAC_DA_47_32 (# 292) */, NULL /* PMAC_IDIS_REQ_WM (# 293) */, NULL /* PMAC_IPG_RX_CNT (# 294) */, NULL /* PMAC_IPG_TX_CNT (# 295) */, NULL /* PMAC_IREQ_WM (# 296) */, NULL /* PMAC_PRI (# 297) */, NULL /* PMAC_RC (# 298) */, NULL /* PMAC_RL2 (# 299) */, NULL /* PMAC_RXSH (# 300) */, NULL /* PMAC_SA_31_0 (# 301) */, NULL /* PMAC_SA_47_32 (# 302) */, NULL /* PMAC_TAG (# 303) */, NULL /* PMAC_TYPE_LEN (# 304) */, NULL /* PMAC_VLAN ID (# 305) */, "P0EC.AD" /* PORT_AD (# 306) */, "P1EC.AD" /* PORT_AD1 (# 307) */, "P2EC.AD" /* PORT_AD2 (# 308) */, "P3EC.AD" /* PORT_AD3 (# 309) */, "P4EC.AD" /* PORT_AD4 (# 310) */, "P5EC.AD" /* PORT_AD5 (# 311) */, "P6EC.AD" /* PORT_AD6 (# 312) */, "UPMBPM.BP" /* PORT_BP (# 313) */, NULL /* PORT_DFWD (# 314) */, NULL /* PORT_DFWD1 (# 315) */, NULL /* PORT_DFWD2 (# 316) */, NULL /* PORT_DSV821X (# 317) */, NULL /* PORT_DSV821X1 (# 318) */, NULL /* PORT_DSV821X2 (# 319) */, "P0ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR (# 320) */, "P1ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR1 (# 321) */, "P2ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR2 (# 322) */, "P3ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR3 (# 323) */, "P4ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR4 (# 324) */, "P5ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR5 (# 325) */, "P6ECSQ0.P0SPQ3TR" /* PORT_EGRESS_PSPQ0TR6 (# 326) */, "P0ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR (# 327) */, "P1ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR1 (# 328) */, "P2ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR2 (# 329) */, "P3ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR3 (# 330) */, "P4ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR4 (# 331) */, "P5ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR5 (# 332) */, "P6ECSQ1.P0SPQ3TR" /* PORT_EGRESS_PSPQ1TR6 (# 333) */, "P0ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR (# 334) */, "P1ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR1 (# 335) */, "P2ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR2 (# 336) */, "P3ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR3 (# 337) */, "P4ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR4 (# 338) */, "P5ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR5 (# 339) */, "P6ECSQ2.P0SPQ3TR" /* PORT_EGRESS_PSPQ2TR6 (# 340) */, "P0ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR (# 341) */, "P1ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR1 (# 342) */, "P2ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR2 (# 343) */, "P3ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR3 (# 344) */, "P4ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR4 (# 345) */, "P5ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR5 (# 346) */, "P6ECSQ3.P0SPQ3TR" /* PORT_EGRESS_PSPQ3TR6 (# 347) */, "P0ECWQ0.P0WQ3TR" /* PORT_EGRESS_PWQ0TR (# 348) */, "P1ECWQ0.P22WQ3TR" /* PORT_EGRESS_PWQ0TR1 (# 349) */, "P2ECWQ0.P23WQ3TR" /* PORT_EGRESS_PWQ0TR2 (# 350) */, "P3ECWQ0.P24WQ3TR" /* PORT_EGRESS_PWQ0TR3 (# 351) */, "P4ECWQ0.P25WQ3TR" /* PORT_EGRESS_PWQ0TR4 (# 352) */, "P5ECWQ0.P26WQ3TR" /* PORT_EGRESS_PWQ0TR5 (# 353) */, "P6ECWQ0.P27WQ3TR" /* PORT_EGRESS_PWQ0TR6 (# 354) */, "P0ECWQ1.P0WQ3TR" /* PORT_EGRESS_PWQ1TR (# 355) */, "P1ECWQ1.P15WQ3TR" /* PORT_EGRESS_PWQ1TR1 (# 356) */, "P2ECWQ1.P16WQ3TR" /* PORT_EGRESS_PWQ1TR2 (# 357) */, "P3ECWQ1.P17WQ3TR" /* PORT_EGRESS_PWQ1TR3 (# 358) */, "P4ECWQ1.P18WQ3TR" /* PORT_EGRESS_PWQ1TR4 (# 359) */, "P5ECWQ1.P19WQ3TR" /* PORT_EGRESS_PWQ1TR5 (# 360) */, "P6ECWQ1.P20WQ3TR" /* PORT_EGRESS_PWQ1TR6 (# 361) */, "P0ECWQ2.P0WQ3TR" /* PORT_EGRESS_PWQ2TR (# 362) */, "P1ECWQ2.P8WQ3TR" /* PORT_EGRESS_PWQ2TR1 (# 363) */, "P2ECWQ2.P9WQ3TR" /* PORT_EGRESS_PWQ2TR2 (# 364) */, "P3ECWQ2.P10WQ3TR" /* PORT_EGRESS_PWQ2TR3 (# 365) */, "P4ECWQ2.P11WQ3TR" /* PORT_EGRESS_PWQ2TR4 (# 366) */, "P5ECWQ2.P12WQ3TR" /* PORT_EGRESS_PWQ2TR5 (# 367) */, "P6ECWQ2.P13WQ3TR" /* PORT_EGRESS_PWQ2TR6 (# 368) */, "P0ECWQ3.P0WQ3TR" /* PORT_EGRESS_PWQ3TR (# 369) */, "P1ECWQ3.P1WQ3TR" /* PORT_EGRESS_PWQ3TR1 (# 370) */, "P2ECWQ3.P2WQ3TR" /* PORT_EGRESS_PWQ3TR2 (# 371) */, "P3ECWQ3.P3WQ3TR" /* PORT_EGRESS_PWQ3TR3 (# 372) */, "P4ECWQ3.P4WQ3TR" /* PORT_EGRESS_PWQ3TR4 (# 373) */, "P5ECWQ3.P5WQ3TR" /* PORT_EGRESS_PWQ3TR5 (# 374) */, "P6ECWQ3.P6WQ3TR" /* PORT_EGRESS_PWQ3TR6 (# 375) */, "TUPR0.ATUF0" /* PORT_FILTER_ATUF (# 376) */, "TUPR1.ATUF1" /* PORT_FILTER_ATUF1 (# 377) */, "TUPR2.ATUF2" /* PORT_FILTER_ATUF2 (# 378) */, "TUPR3.ATUF3" /* PORT_FILTER_ATUF3 (# 379) */, "TUPR4.ATUF4" /* PORT_FILTER_ATUF4 (# 380) */, "TUPR5.ATUF5" /* PORT_FILTER_ATUF5 (# 381) */, "TUPR6.ATUF6" /* PORT_FILTER_ATUF6 (# 382) */, "TUPR7.ATUF7" /* PORT_FILTER_ATUF7 (# 383) */, "TUPF0.BASEPT0" /* PORT_FILTER_BASEPT (# 384) */, "TUPF1.BASEPT1" /* PORT_FILTER_BASEPT1 (# 385) */, "TUPF2.BASEPT2" /* PORT_FILTER_BASEPT2 (# 386) */, "TUPF3.BASEPT3" /* PORT_FILTER_BASEPT3 (# 387) */, "TUPF4.BASEPT4" /* PORT_FILTER_BASEPT4 (# 388) */, "TUPF5.BASEPT5" /* PORT_FILTER_BASEPT5 (# 389) */, "TUPF6.BASEPT6" /* PORT_FILTER_BASEPT6 (# 390) */, "TUPF7.BASEPT7" /* PORT_FILTER_BASEPT7 (# 391) */, "TUPR0.COMP0" /* PORT_FILTER_COMP (# 392) */, "TUPR1.COMP1" /* PORT_FILTER_COMP1 (# 393) */, "TUPR2.COMP2" /* PORT_FILTER_COMP2 (# 394) */, "TUPR3.COMP3" /* PORT_FILTER_COMP3 (# 395) */, "TUPR4.COMP4" /* PORT_FILTER_COMP4 (# 396) */, "TUPR5.COMP5" /* PORT_FILTER_COMP5 (# 397) */, "TUPR6.COMP6" /* PORT_FILTER_COMP6 (# 398) */, "TUPR7.COMP7" /* PORT_FILTER_COMP7 (# 399) */, "TUPR0.PRANGE0" /* PORT_FILTER_PRANGE (# 400) */, "TUPR1.PRANGE1" /* PORT_FILTER_PRANGE1 (# 401) */, "TUPR2.PRANGE2" /* PORT_FILTER_PRANGE2 (# 402) */, "TUPR3.PRANGE3" /* PORT_FILTER_PRANGE3 (# 403) */, "TUPR4.PRANGE4" /* PORT_FILTER_PRANGE4 (# 404) */, "TUPR5.PRANGE5" /* PORT_FILTER_PRANGE5 (# 405) */, "TUPR6.PRANGE6" /* PORT_FILTER_PRANGE6 (# 406) */, "TUPR7.PRANGE7" /* PORT_FILTER_PRANGE7 (# 407) */, "TUPR0.TUPF0" /* PORT_FILTER_TUPF (# 408) */, "TUPR1.TUPF1" /* PORT_FILTER_TUPF1 (# 409) */, "TUPR2.TUPF2" /* PORT_FILTER_TUPF2 (# 410) */, "TUPR3.TUPF3" /* PORT_FILTER_TUPF3 (# 411) */, "TUPR4.TUPF4" /* PORT_FILTER_TUPF4 (# 412) */, "TUPR5.TUPF5" /* PORT_FILTER_TUPF5 (# 413) */, "TUPR6.TUPF6" /* PORT_FILTER_TUPF6 (# 414) */, "TUPR7.TUPF7" /* PORT_FILTER_TUPF7 (# 415) */, "P0BC.FLD" /* PORT_FLD (# 416) */, "P1BC.FLD" /* PORT_FLD1 (# 417) */, "P2BC.FLD" /* PORT_FLD2 (# 418) */, "P3BC.FLD" /* PORT_FLD3 (# 419) */, "P4BC.FLD" /* PORT_FLD4 (# 420) */, "P5BC.FLD" /* PORT_FLD5 (# 421) */, "P6BC.FLD" /* PORT_FLD6 (# 422) */, "P0BC.FLP" /* PORT_FLP (# 423) */, "P1BC.FLP" /* PORT_FLP1 (# 424) */, "P2BC.FLP" /* PORT_FLP2 (# 425) */, "P3BC.FLP" /* PORT_FLP3 (# 426) */, "P4BC.FLP" /* PORT_FLP4 (# 427) */, "P5BC.FLP" /* PORT_FLP5 (# 428) */, "P6BC.FLP" /* PORT_FLP6 (# 429) */, "P0EC.IFNTE" /* PORT_IFNTE (# 430) */, "P1EC.IFNTE" /* PORT_IFNTE1 (# 431) */, "P2EC.IFNTE" /* PORT_IFNTE2 (# 432) */, "P3EC.IFNTE" /* PORT_IFNTE3 (# 433) */, "P4EC.IFNTE" /* PORT_IFNTE4 (# 434) */, "P5EC.IFNTE" /* PORT_IFNTE5 (# 435) */, "P6EC.IFNTE" /* PORT_IFNTE6 (# 436) */, "P0EC.IMTE" /* PORT_IMTE (# 437) */, "P1EC.IMTE" /* PORT_IMTE1 (# 438) */, "P2EC.IMTE" /* PORT_IMTE2 (# 439) */, "P3EC.IMTE" /* PORT_IMTE3 (# 440) */, "P4EC.IMTE" /* PORT_IMTE4 (# 441) */, "P5EC.IMTE" /* PORT_IMTE5 (# 442) */, "P6EC.IMTE" /* PORT_IMTE6 (# 443) */, "P0ICR.P0ITR" /* PORT_INGRESS_PITR (# 444) */, "P1ICR.P1ITR" /* PORT_INGRESS_PITR1 (# 445) */, "P2ICR.P2ITR" /* PORT_INGRESS_PITR2 (# 446) */, "P3ICR.P3ITR" /* PORT_INGRESS_PITR3 (# 447) */, "P4ICR.P4ITR" /* PORT_INGRESS_PITR4 (# 448) */, "P5ICR.P5ITR" /* PORT_INGRESS_PITR5 (# 449) */, "P6ICR.P6ITR" /* PORT_INGRESS_PITR6 (# 450) */, "P0ICR.P0ITT" /* PORT_INGRESS_PITT (# 451) */, "P1ICR.P1ITT" /* PORT_INGRESS_PITT1 (# 452) */, "P2ICR.P2ITT" /* PORT_INGRESS_PITT2 (# 453) */, "P3ICR.P3ITT" /* PORT_INGRESS_PITT3 (# 454) */, "P4ICR.P4ITT" /* PORT_INGRESS_PITT4 (# 455) */, "P5ICR.P5ITT" /* PORT_INGRESS_PITT5 (# 456) */, "P6ICR.P6ITT" /* PORT_INGRESS_PITT6 (# 457) */, "P0EC.IPMO" /* PORT_IPMO (# 458) */, "P1EC.IPMO" /* PORT_IPMO1 (# 459) */, "P2EC.IPMO" /* PORT_IPMO2 (# 460) */, "P3EC.IPMO" /* PORT_IPMO3 (# 461) */, "P4EC.IPMO" /* PORT_IPMO4 (# 462) */, "P5EC.IPMO" /* PORT_IPMO5 (# 463) */, "P6EC.IPMO" /* PORT_IPMO6 (# 464) */, "P0BC.IPOVTU" /* PORT_IPOVTU (# 465) */, "P1BC.IPOVTU" /* PORT_IPOVTU1 (# 466) */, "P2BC.IPOVTU" /* PORT_IPOVTU2 (# 467) */, "P3BC.IPOVTU" /* PORT_IPOVTU3 (# 468) */, "P4BC.IPOVTU" /* PORT_IPOVTU4 (# 469) */, "P5BC.IPOVTU" /* PORT_IPOVTU5 (# 470) */, "P6BC.IPOVTU" /* PORT_IPOVTU6 (# 471) */, "P0BC.IPVLAN" /* PORT_IPVLAN (# 472) */, "P1BC.IPVLAN" /* PORT_IPVLAN1 (# 473) */, "P2BC.IPVLAN" /* PORT_IPVLAN2 (# 474) */, "P3BC.IPVLAN" /* PORT_IPVLAN3 (# 475) */, "P4BC.IPVLAN" /* PORT_IPVLAN4 (# 476) */, "P5BC.IPVLAN" /* PORT_IPVLAN5 (# 477) */, "P6BC.IPVLAN" /* PORT_IPVLAN6 (# 478) */, "P0EC.LD" /* PORT_LD (# 479) */, "P1EC.LD" /* PORT_LD1 (# 480) */, "P2EC.LD" /* PORT_LD2 (# 481) */, "P3EC.LD" /* PORT_LD3 (# 482) */, "P4EC.LD" /* PORT_LD4 (# 483) */, "P5EC.LD" /* PORT_LD5 (# 484) */, "P6EC.LD" /* PORT_LD6 (# 485) */, "P0EC.MNA024" /* PORT_MNA24 (# 486) */, "P1EC.MNA024" /* PORT_MNA241 (# 487) */, "P2EC.MNA024" /* PORT_MNA242 (# 488) */, "P3EC.MNA024" /* PORT_MNA243 (# 489) */, "P4EC.MNA024" /* PORT_MNA244 (# 490) */, "P5EC.MNA024" /* PORT_MNA245 (# 491) */, "P6EC.MNA024" /* PORT_MNA246 (# 492) */, "MPMRPM.MP" /* PORT_MP (# 493) */, "P0EC.PAS" /* PORT_PAS (# 494) */, "P1EC.PAS" /* PORT_PAS1 (# 495) */, "P2EC.PAS" /* PORT_PAS2 (# 496) */, "P3EC.PAS" /* PORT_PAS3 (# 497) */, "P4EC.PAS" /* PORT_PAS4 (# 498) */, "P5EC.PAS" /* PORT_PAS5 (# 499) */, "P6EC.PAS" /* PORT_PAS6 (# 500) */, "P0S.P0DS" /* PORT_PDS (# 501) */, "P1S.P1DS" /* PORT_PDS1 (# 502) */, "P2S.P2DS" /* PORT_PDS2 (# 503) */, "P3S.P3DS" /* PORT_PDS3 (# 504) */, "P4S.P4DS" /* PORT_PDS4 (# 505) */, "P5S.P5DS" /* PORT_PDS5 (# 506) */, "P6S.P6DS" /* PORT_PDS6 (# 507) */, "P0S.P0FCS" /* PORT_PFCS (# 508) */, "P1S.P1FCS" /* PORT_PFCS1 (# 509) */, "P2S.P2FCS" /* PORT_PFCS2 (# 510) */, "P3S.P3FCS" /* PORT_PFCS3 (# 511) */, "P4S.P4FCS" /* PORT_PFCS4 (# 512) */, "P5S.P5FCS" /* PORT_PFCS5 (# 513) */, "P6S.P6FCS" /* PORT_PFCS6 (# 514) */, "P0S.P0LS" /* PORT_PLS (# 515) */, "P1S.P1LS" /* PORT_PLS1 (# 516) */, "P2S.P2LS" /* PORT_PLS2 (# 517) */, "P3S.P3LS" /* PORT_PLS3 (# 518) */, "P4S.P4LS" /* PORT_PLS4 (# 519) */, "P5S.P5LS" /* PORT_PLS5 (# 520) */, "P6S.P6LS" /* PORT_PLS6 (# 521) */, "P0EC.PM" /* PORT_PM (# 522) */, "P1EC.PM" /* PORT_PM1 (# 523) */, "P2EC.PM" /* PORT_PM2 (# 524) */, "P3EC.PM" /* PORT_PM3 (# 525) */, "P4EC.PM" /* PORT_PM4 (# 526) */, "P5EC.PM" /* PORT_PM5 (# 527) */, "P6EC.PM" /* PORT_PM6 (# 528) */, "P0EC.PPPOEP" /* PORT_PPPOEP (# 529) */, "P1EC.PPPOEP" /* PORT_PPPOEP1 (# 530) */, "P2EC.PPPOEP" /* PORT_PPPOEP2 (# 531) */, "P3EC.PPPOEP" /* PORT_PPPOEP3 (# 532) */, "P4EC.PPPOEP" /* PORT_PPPOEP4 (# 533) */, "P5EC.PPPOEP" /* PORT_PPPOEP5 (# 534) */, "P6EC.PPPOEP" /* PORT_PPPOEP6 (# 535) */, "P0S.P0SHS" /* PORT_PSHS (# 536) */, "P1S.P1SHS" /* PORT_PSHS1 (# 537) */, "P2S.P2SHS" /* PORT_PSHS2 (# 538) */, "P3S.P3SHS" /* PORT_PSHS3 (# 539) */, "P4S.P4SHS" /* PORT_PSHS4 (# 540) */, "P5S.P5SHS" /* PORT_PSHS5 (# 541) */, "P6S.P6SHS" /* PORT_PSHS6 (# 542) */, "P0S.P0SS" /* PORT_PSS (# 543) */, "P1S.P1SS" /* PORT_PSS1 (# 544) */, "P2S.P2SS" /* PORT_PSS2 (# 545) */, "P3S.P3SS" /* PORT_PSS3 (# 546) */, "P4S.P4SS" /* PORT_PSS4 (# 547) */, "P5S.P5SS" /* PORT_PSS5 (# 548) */, "P6S.P6SS" /* PORT_PSS6 (# 549) */, NULL /* PORT_REDIR (# 550) */, NULL /* PORT_REDIR1 (# 551) */, NULL /* PORT_REDIR2 (# 552) */, NULL /* PORT_RGMII_GMII_P0CKIO (# 553) */, NULL /* PORT_RGMII_GMII_P0DUP (# 554) */, NULL /* PORT_RGMII_GMII_P0FCE (# 555) */, NULL /* PORT_RGMII_GMII_P0FEQ (# 556) */, NULL /* PORT_RGMII_GMII_P0IS (# 557) */, NULL /* PORT_RGMII_GMII_P0RDLY (# 558) */, NULL /* PORT_RGMII_GMII_P0SPD (# 559) */, NULL /* PORT_RGMII_GMII_P0TDLY (# 560) */, NULL /* PORT_RGMII_GMII_P1CKIO (# 561) */, NULL /* PORT_RGMII_GMII_P1DUP (# 562) */, NULL /* PORT_RGMII_GMII_P1FCE (# 563) */, NULL /* PORT_RGMII_GMII_P1FEQ (# 564) */, NULL /* PORT_RGMII_GMII_P1IS (# 565) */, NULL /* PORT_RGMII_GMII_P1RDLY (# 566) */, NULL /* PORT_RGMII_GMII_P1SPD (# 567) */, NULL /* PORT_RGMII_GMII_P1TDLY (# 568) */, "RGMIICR.P4DUP" /* PORT_RGMII_GMII_P4DUP (# 569) */, "RGMIICR.P4FCE" /* PORT_RGMII_GMII_P4FCE (# 570) */, "RGMIICR.P4SPD" /* PORT_RGMII_GMII_P4SPD (# 571) */, "RGMIICR.P5DUP" /* PORT_RGMII_GMII_P5DUP (# 572) */, "RGMIICR.P5FCE" /* PORT_RGMII_GMII_P5FCE (# 573) */, "RGMIICR.P5SPD" /* PORT_RGMII_GMII_P5SPD (# 574) */, "RGMIICR.P6DUP" /* PORT_RGMII_GMII_P6DUP (# 575) */, "RGMIICR.P6FCE" /* PORT_RGMII_GMII_P6FCE (# 576) */, "RGMIICR.P6SPD" /* PORT_RGMII_GMII_P6SPD (# 577) */, "P0BC.RMWFQ" /* PORT_RMWFQ (# 578) */, "P1BC.RMWFQ" /* PORT_RMWFQ1 (# 579) */, "P2BC.RMWFQ" /* PORT_RMWFQ2 (# 580) */, "P3BC.RMWFQ" /* PORT_RMWFQ3 (# 581) */, "P4BC.RMWFQ" /* PORT_RMWFQ4 (# 582) */, "P5BC.RMWFQ" /* PORT_RMWFQ5 (# 583) */, "P6BC.RMWFQ" /* PORT_RMWFQ6 (# 584) */, "MPMRPM.RP" /* PORT_RP (# 585) */, "P0BC.SPE" /* PORT_SPE (# 586) */, "P1BC.SPE" /* PORT_SPE1 (# 587) */, "P2BC.SPE" /* PORT_SPE2 (# 588) */, "P3BC.SPE" /* PORT_SPE3 (# 589) */, "P4BC.SPE" /* PORT_SPE4 (# 590) */, "P5BC.SPE" /* PORT_SPE5 (# 591) */, "P6BC.SPE" /* PORT_SPE6 (# 592) */, "P0BC.SPS" /* PORT_SPS (# 593) */, "P1BC.SPS" /* PORT_SPS1 (# 594) */, "P2BC.SPS" /* PORT_SPS2 (# 595) */, "P3BC.SPS" /* PORT_SPS3 (# 596) */, "P4BC.SPS" /* PORT_SPS4 (# 597) */, "P5BC.SPS" /* PORT_SPS5 (# 598) */, "P6BC.SPS" /* PORT_SPS6 (# 599) */, "P0BC.TCPE" /* PORT_TCPE (# 600) */, "P1BC.TCPE" /* PORT_TCPE1 (# 601) */, "P2BC.TCPE" /* PORT_TCPE2 (# 602) */, "P3BC.TCPE" /* PORT_TCPE3 (# 603) */, "P4BC.TCPE" /* PORT_TCPE4 (# 604) */, "P5BC.TCPE" /* PORT_TCPE5 (# 605) */, "P6BC.TCPE" /* PORT_TCPE6 (# 606) */, "P0BC.TPE" /* PORT_TPE (# 607) */, "P1BC.TPE" /* PORT_TPE1 (# 608) */, "P2BC.TPE" /* PORT_TPE2 (# 609) */, "P3BC.TPE" /* PORT_TPE3 (# 610) */, "P4BC.TPE" /* PORT_TPE4 (# 611) */, "P5BC.TPE" /* PORT_TPE5 (# 612) */, "P6BC.TPE" /* PORT_TPE6 (# 613) */, "UPMBPM.UP" /* PORT_UP (# 614) */, "P0PBVM.AOVTP" /* PORT_VLAN_AOVTP (# 615) */, "P1PBVM.AOVTP" /* PORT_VLAN_AOVTP1 (# 616) */, "P2PBVM.AOVTP" /* PORT_VLAN_AOVTP2 (# 617) */, "P3PBVM.AOVTP" /* PORT_VLAN_AOVTP3 (# 618) */, "P4PBVM.AOVTP" /* PORT_VLAN_AOVTP4 (# 619) */, "P5PBVM.AOVTP" /* PORT_VLAN_AOVTP5 (# 620) */, "P6PBVM.AOVTP" /* PORT_VLAN_AOVTP6 (# 621) */, "P0PBVM.BYPASS" /* PORT_VLAN_BYPASS (# 622) */, "P1PBVM.BYPASS" /* PORT_VLAN_BYPASS1 (# 623) */, "P2PBVM.BYPASS" /* PORT_VLAN_BYPASS2 (# 624) */, "P3PBVM.BYPASS" /* PORT_VLAN_BYPASS3 (# 625) */, "P4PBVM.BYPASS" /* PORT_VLAN_BYPASS4 (# 626) */, "P5PBVM.BYPASS" /* PORT_VLAN_BYPASS5 (# 627) */, "P6PBVM.BYPASS" /* PORT_VLAN_BYPASS6 (# 628) */, "P0PBVM.DFID" /* PORT_VLAN_DFID (# 629) */, "P1PBVM.DFID" /* PORT_VLAN_DFID1 (# 630) */, "P2PBVM.DFID" /* PORT_VLAN_DFID2 (# 631) */, "P3PBVM.DFID" /* PORT_VLAN_DFID3 (# 632) */, "P4PBVM.DFID" /* PORT_VLAN_DFID4 (# 633) */, "P5PBVM.DFID" /* PORT_VLAN_DFID5 (# 634) */, "P6PBVM.DFID" /* PORT_VLAN_DFID6 (# 635) */, "P0PBVM.DVPM" /* PORT_VLAN_DVPM (# 636) */, "P1PBVM.DVPM" /* PORT_VLAN_DVPM1 (# 637) */, "P2PBVM.DVPM" /* PORT_VLAN_DVPM2 (# 638) */, "P3PBVM.DVPM" /* PORT_VLAN_DVPM3 (# 639) */, "P4PBVM.DVPM" /* PORT_VLAN_DVPM4 (# 640) */, "P5PBVM.DVPM" /* PORT_VLAN_DVPM5 (# 641) */, "P6PBVM.DVPM" /* PORT_VLAN_DVPM6 (# 642) */, "P0DVID.PP" /* PORT_VLAN_PP (# 643) */, "P1DVID.PP" /* PORT_VLAN_PP1 (# 644) */, "P2DVID.PP" /* PORT_VLAN_PP2 (# 645) */, "P3DVID.PP" /* PORT_VLAN_PP3 (# 646) */, "P4DVID.PP" /* PORT_VLAN_PP4 (# 647) */, "P5DVID.PP" /* PORT_VLAN_PP5 (# 648) */, "P6DVID.PP" /* PORT_VLAN_PP6 (# 649) */, "P0DVID.PPE" /* PORT_VLAN_PPE (# 650) */, "P1DVID.PPE" /* PORT_VLAN_PPE1 (# 651) */, "P2DVID.PPE" /* PORT_VLAN_PPE2 (# 652) */, "P3DVID.PPE" /* PORT_VLAN_PPE3 (# 653) */, "P4DVID.PPE" /* PORT_VLAN_PPE4 (# 654) */, "P5DVID.PPE" /* PORT_VLAN_PPE5 (# 655) */, "P6DVID.PPE" /* PORT_VLAN_PPE6 (# 656) */, "P0DVID.PVID" /* PORT_VLAN_PVID (# 657) */, "P1DVID.PVID" /* PORT_VLAN_PVID1 (# 658) */, "P2DVID.PVID" /* PORT_VLAN_PVID2 (# 659) */, "P3DVID.PVID" /* PORT_VLAN_PVID3 (# 660) */, "P4DVID.PVID" /* PORT_VLAN_PVID4 (# 661) */, "P5DVID.PVID" /* PORT_VLAN_PVID5 (# 662) */, "P6DVID.PVID" /* PORT_VLAN_PVID6 (# 663) */, "P0DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP (# 664) */, "P1DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP1 (# 665) */, "P2DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP2 (# 666) */, "P3DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP3 (# 667) */, "P4DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP4 (# 668) */, "P5DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP5 (# 669) */, "P6DVID.PVTAGMP" /* PORT_VLAN_PVTAGMP6 (# 670) */, "P0PBVM.TBVE" /* PORT_VLAN_TBVE (# 671) */, "P1PBVM.TBVE" /* PORT_VLAN_TBVE1 (# 672) */, "P2PBVM.TBVE" /* PORT_VLAN_TBVE2 (# 673) */, "P3PBVM.TBVE" /* PORT_VLAN_TBVE3 (# 674) */, "P4PBVM.TBVE" /* PORT_VLAN_TBVE4 (# 675) */, "P5PBVM.TBVE" /* PORT_VLAN_TBVE5 (# 676) */, "P6PBVM.TBVE" /* PORT_VLAN_TBVE6 (# 677) */, "P0PBVM.VC" /* PORT_VLAN_VC (# 678) */, "P1PBVM.VC" /* PORT_VLAN_VC1 (# 679) */, "P2PBVM.VC" /* PORT_VLAN_VC2 (# 680) */, "P3PBVM.VC" /* PORT_VLAN_VC3 (# 681) */, "P4PBVM.VC" /* PORT_VLAN_VC4 (# 682) */, "P5PBVM.VC" /* PORT_VLAN_VC5 (# 683) */, "P6PBVM.VC" /* PORT_VLAN_VC6 (# 684) */, "P0PBVM.VMCE" /* PORT_VLAN_VMCE (# 685) */, "P1PBVM.VMCE" /* PORT_VLAN_VMCE1 (# 686) */, "P2PBVM.VMCE" /* PORT_VLAN_VMCE2 (# 687) */, "P3PBVM.VMCE" /* PORT_VLAN_VMCE3 (# 688) */, "P4PBVM.VMCE" /* PORT_VLAN_VMCE4 (# 689) */, "P5PBVM.VMCE" /* PORT_VLAN_VMCE5 (# 690) */, "P6PBVM.VMCE" /* PORT_VLAN_VMCE6 (# 691) */, "P0PBVM.VSD" /* PORT_VLAN_VSD (# 692) */, "P1PBVM.VSD" /* PORT_VLAN_VSD1 (# 693) */, "P2PBVM.VSD" /* PORT_VLAN_VSD2 (# 694) */, "P3PBVM.VSD" /* PORT_VLAN_VSD3 (# 695) */, "P4PBVM.VSD" /* PORT_VLAN_VSD4 (# 696) */, "P5PBVM.VSD" /* PORT_VLAN_VSD5 (# 697) */, "P6PBVM.VSD" /* PORT_VLAN_VSD6 (# 698) */, "P0BC.VPE" /* PORT_VPE (# 699) */, "P1BC.VPE" /* PORT_VPE1 (# 700) */, "P2BC.VPE" /* PORT_VPE2 (# 701) */, "P3BC.VPE" /* PORT_VPE3 (# 702) */, "P4BC.VPE" /* PORT_VPE4 (# 703) */, "P5BC.VPE" /* PORT_VPE5 (# 704) */, "P6BC.VPE" /* PORT_VPE6 (# 705) */, "PSIDR.PPPoESID" /* PPPOE_SID (# 706) */, "PFA.APF0" /* PROTOCOL_FILTER_APF (# 707) */, "PFA.APF1" /* PROTOCOL_FILTER_APF1 (# 708) */, "PFA.APF2" /* PROTOCOL_FILTER_APF2 (# 709) */, "PFA.APF3" /* PROTOCOL_FILTER_APF3 (# 710) */, "PFA.APF4" /* PROTOCOL_FILTER_APF4 (# 711) */, "PFA.APF5" /* PROTOCOL_FILTER_APF5 (# 712) */, "PFA.APF6" /* PROTOCOL_FILTER_APF6 (# 713) */, "PFA.APF7" /* PROTOCOL_FILTER_APF7 (# 714) */, "PF_0.PFR0" /* PROTOCOL_FILTER_PFR0 (# 715) */, "PF_1.PFR0" /* PROTOCOL_FILTER_PFR01 (# 716) */, "PF_2.PFR0" /* PROTOCOL_FILTER_PFR02 (# 717) */, "PF_3.PFR0" /* PROTOCOL_FILTER_PFR03 (# 718) */, "PF_0.PFR1" /* PROTOCOL_FILTER_PFR1 (# 719) */, "PF_1.PFR1" /* PROTOCOL_FILTER_PFR11 (# 720) */, "PF_2.PFR1" /* PROTOCOL_FILTER_PFR12 (# 721) */, "PF_3.PFR1" /* PROTOCOL_FILTER_PFR13 (# 722) */, NULL /* PROTOCOL_FILTER_PFR2 (# 723) */, NULL /* PROTOCOL_FILTER_PFR21 (# 724) */, NULL /* PROTOCOL_FILTER_PFR3 (# 725) */, NULL /* PROTOCOL_FILTER_PFR31 (# 726) */, "RA_01_00.RA00_ACT" /* RA00_ACT (# 727) */, "RA_03_02.RA20_ACT" /* RA00_ACT1 (# 728) */, "RA_05_04.RA40_ACT" /* RA00_ACT2 (# 729) */, "RA_07_06.RA60_ACT" /* RA00_ACT3 (# 730) */, "RA_09_08.RA80_ACT" /* RA00_ACT4 (# 731) */, "RA_0B_0A.RA1100_ACT" /* RA00_ACT5 (# 732) */, "RA_0D_0C.RA1320_ACT" /* RA00_ACT6 (# 733) */, "RA_0F_0E.RA1540_ACT" /* RA00_ACT7 (# 734) */, "RA_11_10.RA1760_ACT" /* RA00_ACT8 (# 735) */, "RA_13_12.RA1980_ACT" /* RA00_ACT9 (# 736) */, "RA_15_14.RA200_ACT" /* RA00_ACT10 (# 737) */, "RA_17_16.RA220_ACT" /* RA00_ACT11 (# 738) */, "RA_19_18.RA240_ACT" /* RA00_ACT12 (# 739) */, "RA_1B_1A.RA260_ACT" /* RA00_ACT13 (# 740) */, "RA_1D_1C.RA280_ACT" /* RA00_ACT14 (# 741) */, "RA_1F_1E.RA300_ACT" /* RA00_ACT15 (# 742) */, "RA_21_20.RA320_ACT" /* RA00_ACT16 (# 743) */, "RA_23_22.RA340_ACT" /* RA00_ACT17 (# 744) */, "RA_25_24.RA360_ACT" /* RA00_ACT18 (# 745) */, "RA_27_26.RA380_ACT" /* RA00_ACT19 (# 746) */, "RA_29_28.RA400_ACT" /* RA00_ACT20 (# 747) */, "RA_2B_2A.RA420_ACT" /* RA00_ACT21 (# 748) */, "RA_2D_2C.RA440_ACT" /* RA00_ACT22 (# 749) */, "RA_2F_2E.RA460_ACT" /* RA00_ACT23 (# 750) */, "RA_01_00.RA00_CV" /* RA00_CV (# 751) */, "RA_03_02.RA20_CV" /* RA00_CV1 (# 752) */, "RA_05_04.RA40_CV" /* RA00_CV2 (# 753) */, "RA_07_06.RA60_CV" /* RA00_CV3 (# 754) */, "RA_09_08.RA80_CV" /* RA00_CV4 (# 755) */, "RA_0B_0A.RA1100_CV" /* RA00_CV5 (# 756) */, "RA_0D_0C.RA1320_CV" /* RA00_CV6 (# 757) */, "RA_0F_0E.RA1540_CV" /* RA00_CV7 (# 758) */, "RA_11_10.RA1760_CV" /* RA00_CV8 (# 759) */, "RA_13_12.RA1980_CV" /* RA00_CV9 (# 760) */, "RA_15_14.RA200_CV" /* RA00_CV10 (# 761) */, "RA_17_16.RA220_CV" /* RA00_CV11 (# 762) */, "RA_19_18.RA240_CV" /* RA00_CV12 (# 763) */, "RA_1B_1A.RA260_CV" /* RA00_CV13 (# 764) */, "RA_1D_1C.RA280_CV" /* RA00_CV14 (# 765) */, "RA_1F_1E.RA300_CV" /* RA00_CV15 (# 766) */, "RA_21_20.RA320_CV" /* RA00_CV16 (# 767) */, "RA_23_22.RA340_CV" /* RA00_CV17 (# 768) */, "RA_25_24.RA360_CV" /* RA00_CV18 (# 769) */, "RA_27_26.RA380_CV" /* RA00_CV19 (# 770) */, "RA_29_28.RA400_CV" /* RA00_CV20 (# 771) */, "RA_2B_2A.RA420_CV" /* RA00_CV21 (# 772) */, "RA_2D_2C.RA440_CV" /* RA00_CV22 (# 773) */, "RA_2F_2E.RA460_CV" /* RA00_CV23 (# 774) */, "RA_01_00.RA00_MG" /* RA00_MG (# 775) */, "RA_03_02.RA20_MG" /* RA00_MG1 (# 776) */, "RA_05_04.RA40_MG" /* RA00_MG2 (# 777) */, "RA_07_06.RA60_MG" /* RA00_MG3 (# 778) */, "RA_09_08.RA80_MG" /* RA00_MG4 (# 779) */, "RA_0B_0A.RA1100_MG" /* RA00_MG5 (# 780) */, "RA_0D_0C.RA1320_MG" /* RA00_MG6 (# 781) */, "RA_0F_0E.RA1540_MG" /* RA00_MG7 (# 782) */, "RA_11_10.RA1760_MG" /* RA00_MG8 (# 783) */, "RA_13_12.RA1980_MG" /* RA00_MG9 (# 784) */, "RA_15_14.RA200_MG" /* RA00_MG10 (# 785) */, "RA_17_16.RA220_MG" /* RA00_MG11 (# 786) */, "RA_19_18.RA240_MG" /* RA00_MG12 (# 787) */, "RA_1B_1A.RA260_MG" /* RA00_MG13 (# 788) */, "RA_1D_1C.RA280_MG" /* RA00_MG14 (# 789) */, "RA_1F_1E.RA300_MG" /* RA00_MG15 (# 790) */, "RA_21_20.RA320_MG" /* RA00_MG16 (# 791) */, "RA_23_22.RA340_MG" /* RA00_MG17 (# 792) */, "RA_25_24.RA360_MG" /* RA00_MG18 (# 793) */, "RA_27_26.RA380_MG" /* RA00_MG19 (# 794) */, "RA_29_28.RA400_MG" /* RA00_MG20 (# 795) */, "RA_2B_2A.RA420_MG" /* RA00_MG21 (# 796) */, "RA_2D_2C.RA440_MG" /* RA00_MG22 (# 797) */, "RA_2F_2E.RA460_MG" /* RA00_MG23 (# 798) */, "RA_01_00.RA00_SPAN" /* RA00_SPAN (# 799) */, "RA_03_02.RA20_SPAN" /* RA00_SPAN1 (# 800) */, "RA_05_04.RA40_SPAN" /* RA00_SPAN2 (# 801) */, "RA_07_06.RA60_SPAN" /* RA00_SPAN3 (# 802) */, "RA_09_08.RA80_SPAN" /* RA00_SPAN4 (# 803) */, "RA_0B_0A.RA1100_SPAN" /* RA00_SPAN5 (# 804) */, "RA_0D_0C.RA1320_SPAN" /* RA00_SPAN6 (# 805) */, "RA_0F_0E.RA1540_SPAN" /* RA00_SPAN7 (# 806) */, "RA_11_10.RA1760_SPAN" /* RA00_SPAN8 (# 807) */, "RA_13_12.RA1980_SPAN" /* RA00_SPAN9 (# 808) */, "RA_15_14.RA200_SPAN" /* RA00_SPAN10 (# 809) */, "RA_17_16.RA220_SPAN" /* RA00_SPAN11 (# 810) */, "RA_19_18.RA240_SPAN" /* RA00_SPAN12 (# 811) */, "RA_1B_1A.RA260_SPAN" /* RA00_SPAN13 (# 812) */, "RA_1D_1C.RA280_SPAN" /* RA00_SPAN14 (# 813) */, "RA_1F_1E.RA300_SPAN" /* RA00_SPAN15 (# 814) */, "RA_21_20.RA320_SPAN" /* RA00_SPAN16 (# 815) */, "RA_23_22.RA340_SPAN" /* RA00_SPAN17 (# 816) */, "RA_25_24.RA360_SPAN" /* RA00_SPAN18 (# 817) */, "RA_27_26.RA380_SPAN" /* RA00_SPAN19 (# 818) */, "RA_29_28.RA400_SPAN" /* RA00_SPAN20 (# 819) */, "RA_2B_2A.RA420_SPAN" /* RA00_SPAN21 (# 820) */, "RA_2D_2C.RA440_SPAN" /* RA00_SPAN22 (# 821) */, "RA_2F_2E.RA460_SPAN" /* RA00_SPAN23 (# 822) */, "RA_01_00.RA00_TXTAG" /* RA00_TXTAG (# 823) */, "RA_03_02.RA20_TXTAG" /* RA00_TXTAG1 (# 824) */, "RA_05_04.RA40_TXTAG" /* RA00_TXTAG2 (# 825) */, "RA_07_06.RA60_TXTAG" /* RA00_TXTAG3 (# 826) */, "RA_09_08.RA80_TXTAG" /* RA00_TXTAG4 (# 827) */, "RA_0B_0A.RA1100_TXTAG" /* RA00_TXTAG5 (# 828) */, "RA_0D_0C.RA1320_TXTAG" /* RA00_TXTAG6 (# 829) */, "RA_0F_0E.RA1540_TXTAG" /* RA00_TXTAG7 (# 830) */, "RA_11_10.RA1760_TXTAG" /* RA00_TXTAG8 (# 831) */, "RA_13_12.RA1980_TXTAG" /* RA00_TXTAG9 (# 832) */, "RA_15_14.RA200_TXTAG" /* RA00_TXTAG10 (# 833) */, "RA_17_16.RA220_TXTAG" /* RA00_TXTAG11 (# 834) */, "RA_19_18.RA240_TXTAG" /* RA00_TXTAG12 (# 835) */, "RA_1B_1A.RA260_TXTAG" /* RA00_TXTAG13 (# 836) */, "RA_1D_1C.RA280_TXTAG" /* RA00_TXTAG14 (# 837) */, "RA_1F_1E.RA300_TXTAG" /* RA00_TXTAG15 (# 838) */, "RA_21_20.RA320_TXTAG" /* RA00_TXTAG16 (# 839) */, "RA_23_22.RA340_TXTAG" /* RA00_TXTAG17 (# 840) */, "RA_25_24.RA360_TXTAG" /* RA00_TXTAG18 (# 841) */, "RA_27_26.RA380_TXTAG" /* RA00_TXTAG19 (# 842) */, "RA_29_28.RA400_TXTAG" /* RA00_TXTAG20 (# 843) */, "RA_2B_2A.RA420_TXTAG" /* RA00_TXTAG21 (# 844) */, "RA_2D_2C.RA440_TXTAG" /* RA00_TXTAG22 (# 845) */, "RA_2F_2E.RA460_TXTAG" /* RA00_TXTAG23 (# 846) */, "RA_01_00.RA00_VALID" /* RA00_VALID (# 847) */, "RA_03_02.RA20_VALID" /* RA00_VALID1 (# 848) */, "RA_05_04.RA40_VALID" /* RA00_VALID2 (# 849) */, "RA_07_06.RA60_VALID" /* RA00_VALID3 (# 850) */, "RA_09_08.RA80_VALID" /* RA00_VALID4 (# 851) */, "RA_0B_0A.RA1100_VALID" /* RA00_VALID5 (# 852) */, "RA_0D_0C.RA1320_VALID" /* RA00_VALID6 (# 853) */, "RA_0F_0E.RA1540_VALID" /* RA00_VALID7 (# 854) */, "RA_11_10.RA1760_VALID" /* RA00_VALID8 (# 855) */, "RA_13_12.RA1980_VALID" /* RA00_VALID9 (# 856) */, "RA_15_14.RA200_VALID" /* RA00_VALID10 (# 857) */, "RA_17_16.RA220_VALID" /* RA00_VALID11 (# 858) */, "RA_19_18.RA240_VALID" /* RA00_VALID12 (# 859) */, "RA_1B_1A.RA260_VALID" /* RA00_VALID13 (# 860) */, "RA_1D_1C.RA280_VALID" /* RA00_VALID14 (# 861) */, "RA_1F_1E.RA300_VALID" /* RA00_VALID15 (# 862) */, "RA_21_20.RA320_VALID" /* RA00_VALID16 (# 863) */, "RA_23_22.RA340_VALID" /* RA00_VALID17 (# 864) */, "RA_25_24.RA360_VALID" /* RA00_VALID18 (# 865) */, "RA_27_26.RA380_VALID" /* RA00_VALID19 (# 866) */, "RA_29_28.RA400_VALID" /* RA00_VALID20 (# 867) */, "RA_2B_2A.RA420_VALID" /* RA00_VALID21 (# 868) */, "RA_2D_2C.RA440_VALID" /* RA00_VALID22 (# 869) */, "RA_2F_2E.RA460_VALID" /* RA00_VALID23 (# 870) */, "RA_01_00.RA01_ACT" /* RA01_ACT (# 871) */, "RA_03_02.RA23_ACT" /* RA01_ACT1 (# 872) */, "RA_05_04.RA45_ACT" /* RA01_ACT2 (# 873) */, "RA_07_06.RA67_ACT" /* RA01_ACT3 (# 874) */, "RA_09_08.RA89_ACT" /* RA01_ACT4 (# 875) */, "RA_0B_0A.RA1101_ACT" /* RA01_ACT5 (# 876) */, "RA_0D_0C.RA1321_ACT" /* RA01_ACT6 (# 877) */, "RA_0F_0E.RA1541_ACT" /* RA01_ACT7 (# 878) */, "RA_11_10.RA1761_ACT" /* RA01_ACT8 (# 879) */, "RA_13_12.RA1981_ACT" /* RA01_ACT9 (# 880) */, "RA_15_14.RA2021_ACT" /* RA01_ACT10 (# 881) */, "RA_17_16.RA2223_ACT" /* RA01_ACT11 (# 882) */, "RA_19_18.RA2425_ACT" /* RA01_ACT12 (# 883) */, "RA_1B_1A.RA2627_ACT" /* RA01_ACT13 (# 884) */, "RA_1D_1C.RA2829_ACT" /* RA01_ACT14 (# 885) */, "RA_1F_1E.RA3031_ACT" /* RA01_ACT15 (# 886) */, "RA_21_20.RA3233_ACT" /* RA01_ACT16 (# 887) */, "RA_23_22.RA3435_ACT" /* RA01_ACT17 (# 888) */, "RA_25_24.RA3637_ACT" /* RA01_ACT18 (# 889) */, "RA_27_26.RA3839_ACT" /* RA01_ACT19 (# 890) */, "RA_29_28.RA4041_ACT" /* RA01_ACT20 (# 891) */, "RA_2B_2A.RA4243_ACT" /* RA01_ACT21 (# 892) */, "RA_2D_2C.RA4445_ACT" /* RA01_ACT22 (# 893) */, "RA_2F_2E.RA4647_ACT" /* RA01_ACT23 (# 894) */, "RA_01_00.RA01_CV" /* RA01_CV (# 895) */, "RA_03_02.RA23_CV" /* RA01_CV1 (# 896) */, "RA_05_04.RA45_CV" /* RA01_CV2 (# 897) */, "RA_07_06.RA67_CV" /* RA01_CV3 (# 898) */, "RA_09_08.RA89_CV" /* RA01_CV4 (# 899) */, "RA_0B_0A.RA1101_CV" /* RA01_CV5 (# 900) */, "RA_0D_0C.RA1321_CV" /* RA01_CV6 (# 901) */, "RA_0F_0E.RA1541_CV" /* RA01_CV7 (# 902) */, "RA_11_10.RA1761_CV" /* RA01_CV8 (# 903) */, "RA_13_12.RA1981_CV" /* RA01_CV9 (# 904) */, "RA_15_14.RA2021_CV" /* RA01_CV10 (# 905) */, "RA_17_16.RA2223_CV" /* RA01_CV11 (# 906) */, "RA_19_18.RA2425_CV" /* RA01_CV12 (# 907) */, "RA_1B_1A.RA2627_CV" /* RA01_CV13 (# 908) */, "RA_1D_1C.RA2829_CV" /* RA01_CV14 (# 909) */, "RA_1F_1E.RA3031_CV" /* RA01_CV15 (# 910) */, "RA_21_20.RA3233_CV" /* RA01_CV16 (# 911) */, "RA_23_22.RA3435_CV" /* RA01_CV17 (# 912) */, "RA_25_24.RA3637_CV" /* RA01_CV18 (# 913) */, "RA_27_26.RA3839_CV" /* RA01_CV19 (# 914) */, "RA_29_28.RA4041_CV" /* RA01_CV20 (# 915) */, "RA_2B_2A.RA4243_CV" /* RA01_CV21 (# 916) */, "RA_2D_2C.RA4445_CV" /* RA01_CV22 (# 917) */, "RA_2F_2E.RA4647_CV" /* RA01_CV23 (# 918) */, "RA_01_00.RA01_MG" /* RA01_MG (# 919) */, "RA_03_02.RA23_MG" /* RA01_MG1 (# 920) */, "RA_05_04.RA45_MG" /* RA01_MG2 (# 921) */, "RA_07_06.RA67_MG" /* RA01_MG3 (# 922) */, "RA_09_08.RA89_MG" /* RA01_MG4 (# 923) */, "RA_0B_0A.RA1101_MG" /* RA01_MG5 (# 924) */, "RA_0D_0C.RA1321_MG" /* RA01_MG6 (# 925) */, "RA_0F_0E.RA1541_MG" /* RA01_MG7 (# 926) */, "RA_11_10.RA1761_MG" /* RA01_MG8 (# 927) */, "RA_13_12.RA1981_MG" /* RA01_MG9 (# 928) */, "RA_15_14.RA2021_MG" /* RA01_MG10 (# 929) */, "RA_17_16.RA2223_MG" /* RA01_MG11 (# 930) */, "RA_19_18.RA2425_MG" /* RA01_MG12 (# 931) */, "RA_1B_1A.RA2627_MG" /* RA01_MG13 (# 932) */, "RA_1D_1C.RA2829_MG" /* RA01_MG14 (# 933) */, "RA_1F_1E.RA3031_MG" /* RA01_MG15 (# 934) */, "RA_21_20.RA3233_MG" /* RA01_MG16 (# 935) */, "RA_23_22.RA3435_MG" /* RA01_MG17 (# 936) */, "RA_25_24.RA3637_MG" /* RA01_MG18 (# 937) */, "RA_27_26.RA3839_MG" /* RA01_MG19 (# 938) */, "RA_29_28.RA4041_MG" /* RA01_MG20 (# 939) */, "RA_2B_2A.RA4243_MG" /* RA01_MG21 (# 940) */, "RA_2D_2C.RA4445_MG" /* RA01_MG22 (# 941) */, "RA_2F_2E.RA4647_MG" /* RA01_MG23 (# 942) */, "RA_01_00.RA01_SPAN" /* RA01_SPAN (# 943) */, "RA_03_02.RA23_SPAN" /* RA01_SPAN1 (# 944) */, "RA_05_04.RA45_SPAN" /* RA01_SPAN2 (# 945) */, "RA_07_06.RA67_SPAN" /* RA01_SPAN3 (# 946) */, "RA_09_08.RA89_SPAN" /* RA01_SPAN4 (# 947) */, "RA_0B_0A.RA1101_SPAN" /* RA01_SPAN5 (# 948) */, "RA_0D_0C.RA1321_SPAN" /* RA01_SPAN6 (# 949) */, "RA_0F_0E.RA1541_SPAN" /* RA01_SPAN7 (# 950) */, "RA_11_10.RA1761_SPAN" /* RA01_SPAN8 (# 951) */, "RA_13_12.RA1981_SPAN" /* RA01_SPAN9 (# 952) */, "RA_15_14.RA2021_SPAN" /* RA01_SPAN10 (# 953) */, "RA_17_16.RA2223_SPAN" /* RA01_SPAN11 (# 954) */, "RA_19_18.RA2425_SPAN" /* RA01_SPAN12 (# 955) */, "RA_1B_1A.RA2627_SPAN" /* RA01_SPAN13 (# 956) */, "RA_1D_1C.RA2829_SPAN" /* RA01_SPAN14 (# 957) */, "RA_1F_1E.RA3031_SPAN" /* RA01_SPAN15 (# 958) */, "RA_21_20.RA3233_SPAN" /* RA01_SPAN16 (# 959) */, "RA_23_22.RA3435_SPAN" /* RA01_SPAN17 (# 960) */, "RA_25_24.RA3637_SPAN" /* RA01_SPAN18 (# 961) */, "RA_27_26.RA3839_SPAN" /* RA01_SPAN19 (# 962) */, "RA_29_28.RA4041_SPAN" /* RA01_SPAN20 (# 963) */, "RA_2B_2A.RA4243_SPAN" /* RA01_SPAN21 (# 964) */, "RA_2D_2C.RA4445_SPAN" /* RA01_SPAN22 (# 965) */, "RA_2F_2E.RA4647_SPAN" /* RA01_SPAN23 (# 966) */, "RA_01_00.RA01_TXTAG" /* RA01_TXTAG (# 967) */, "RA_03_02.RA23_TXTAG" /* RA01_TXTAG1 (# 968) */, "RA_05_04.RA45_TXTAG" /* RA01_TXTAG2 (# 969) */, "RA_07_06.RA67_TXTAG" /* RA01_TXTAG3 (# 970) */, "RA_09_08.RA89_TXTAG" /* RA01_TXTAG4 (# 971) */, "RA_0B_0A.RA1101_TXTAG" /* RA01_TXTAG5 (# 972) */, "RA_0D_0C.RA1321_TXTAG" /* RA01_TXTAG6 (# 973) */, "RA_0F_0E.RA1541_TXTAG" /* RA01_TXTAG7 (# 974) */, "RA_11_10.RA1761_TXTAG" /* RA01_TXTAG8 (# 975) */, "RA_13_12.RA1981_TXTAG" /* RA01_TXTAG9 (# 976) */, "RA_15_14.RA2021_TXTAG" /* RA01_TXTAG10 (# 977) */, "RA_17_16.RA2223_TXTAG" /* RA01_TXTAG11 (# 978) */, "RA_19_18.RA2425_TXTAG" /* RA01_TXTAG12 (# 979) */, "RA_1B_1A.RA2627_TXTAG" /* RA01_TXTAG13 (# 980) */, "RA_1D_1C.RA2829_TXTAG" /* RA01_TXTAG14 (# 981) */, "RA_1F_1E.RA3031_TXTAG" /* RA01_TXTAG15 (# 982) */, "RA_21_20.RA3233_TXTAG" /* RA01_TXTAG16 (# 983) */, "RA_23_22.RA3435_TXTAG" /* RA01_TXTAG17 (# 984) */, "RA_25_24.RA3637_TXTAG" /* RA01_TXTAG18 (# 985) */, "RA_27_26.RA3839_TXTAG" /* RA01_TXTAG19 (# 986) */, "RA_29_28.RA4041_TXTAG" /* RA01_TXTAG20 (# 987) */, "RA_2B_2A.RA4243_TXTAG" /* RA01_TXTAG21 (# 988) */, "RA_2D_2C.RA4445_TXTAG" /* RA01_TXTAG22 (# 989) */, "RA_2F_2E.RA4647_TXTAG" /* RA01_TXTAG23 (# 990) */, "RA_01_00.RA01_VALID" /* RA01_VALID (# 991) */, "RA_03_02.RA23_VALID" /* RA01_VALID1 (# 992) */, "RA_05_04.RA45_VALID" /* RA01_VALID2 (# 993) */, "RA_07_06.RA67_VALID" /* RA01_VALID3 (# 994) */, "RA_09_08.RA89_VALID" /* RA01_VALID4 (# 995) */, "RA_0B_0A.RA1101_VALID" /* RA01_VALID5 (# 996) */, "RA_0D_0C.RA1321_VALID" /* RA01_VALID6 (# 997) */, "RA_0F_0E.RA1541_VALID" /* RA01_VALID7 (# 998) */, "RA_11_10.RA1761_VALID" /* RA01_VALID8 (# 999) */, "RA_13_12.RA1981_VALID" /* RA01_VALID9 (# 1000) */, "RA_15_14.RA2021_VALID" /* RA01_VALID10 (# 1001) */, "RA_17_16.RA2223_VALID" /* RA01_VALID11 (# 1002) */, "RA_19_18.RA2425_VALID" /* RA01_VALID12 (# 1003) */, "RA_1B_1A.RA2627_VALID" /* RA01_VALID13 (# 1004) */, "RA_1D_1C.RA2829_VALID" /* RA01_VALID14 (# 1005) */, "RA_1F_1E.RA3031_VALID" /* RA01_VALID15 (# 1006) */, "RA_21_20.RA3233_VALID" /* RA01_VALID16 (# 1007) */, "RA_23_22.RA3435_VALID" /* RA01_VALID17 (# 1008) */, "RA_25_24.RA3637_VALID" /* RA01_VALID18 (# 1009) */, "RA_27_26.RA3839_VALID" /* RA01_VALID19 (# 1010) */, "RA_29_28.RA4041_VALID" /* RA01_VALID20 (# 1011) */, "RA_2B_2A.RA4243_VALID" /* RA01_VALID21 (# 1012) */, "RA_2D_2C.RA4445_VALID" /* RA01_VALID22 (# 1013) */, "RA_2F_2E.RA4647_VALID" /* RA01_VALID23 (# 1014) */, NULL /* RA02_ACT (# 1015) */, NULL /* RA02_ACT1 (# 1016) */, NULL /* RA02_ACT2 (# 1017) */, NULL /* RA02_ACT3 (# 1018) */, NULL /* RA02_ACT4 (# 1019) */, NULL /* RA02_ACT5 (# 1020) */, NULL /* RA02_ACT6 (# 1021) */, NULL /* RA02_ACT7 (# 1022) */, NULL /* RA02_ACT8 (# 1023) */, NULL /* RA02_ACT9 (# 1024) */, NULL /* RA02_ACT10 (# 1025) */, NULL /* RA02_ACT11 (# 1026) */, NULL /* RA02_CV (# 1027) */, NULL /* RA02_CV1 (# 1028) */, NULL /* RA02_CV2 (# 1029) */, NULL /* RA02_CV3 (# 1030) */, NULL /* RA02_CV4 (# 1031) */, NULL /* RA02_CV5 (# 1032) */, NULL /* RA02_CV6 (# 1033) */, NULL /* RA02_CV7 (# 1034) */, NULL /* RA02_CV8 (# 1035) */, NULL /* RA02_CV9 (# 1036) */, NULL /* RA02_CV10 (# 1037) */, NULL /* RA02_CV11 (# 1038) */, NULL /* RA02_MG (# 1039) */, NULL /* RA02_MG1 (# 1040) */, NULL /* RA02_MG2 (# 1041) */, NULL /* RA02_MG3 (# 1042) */, NULL /* RA02_MG4 (# 1043) */, NULL /* RA02_MG5 (# 1044) */, NULL /* RA02_MG6 (# 1045) */, NULL /* RA02_MG7 (# 1046) */, NULL /* RA02_MG8 (# 1047) */, NULL /* RA02_MG9 (# 1048) */, NULL /* RA02_MG10 (# 1049) */, NULL /* RA02_MG11 (# 1050) */, NULL /* RA02_SPAN (# 1051) */, NULL /* RA02_SPAN1 (# 1052) */, NULL /* RA02_SPAN2 (# 1053) */, NULL /* RA02_SPAN3 (# 1054) */, NULL /* RA02_SPAN4 (# 1055) */, NULL /* RA02_SPAN5 (# 1056) */, NULL /* RA02_SPAN6 (# 1057) */, NULL /* RA02_SPAN7 (# 1058) */, NULL /* RA02_SPAN8 (# 1059) */, NULL /* RA02_SPAN9 (# 1060) */, NULL /* RA02_SPAN10 (# 1061) */, NULL /* RA02_SPAN11 (# 1062) */, NULL /* RA02_TXTAG (# 1063) */, NULL /* RA02_TXTAG1 (# 1064) */, NULL /* RA02_TXTAG2 (# 1065) */, NULL /* RA02_TXTAG3 (# 1066) */, NULL /* RA02_TXTAG4 (# 1067) */, NULL /* RA02_TXTAG5 (# 1068) */, NULL /* RA02_TXTAG6 (# 1069) */, NULL /* RA02_TXTAG7 (# 1070) */, NULL /* RA02_TXTAG8 (# 1071) */, NULL /* RA02_TXTAG9 (# 1072) */, NULL /* RA02_TXTAG10 (# 1073) */, NULL /* RA02_TXTAG11 (# 1074) */, NULL /* RA02_VALID (# 1075) */, NULL /* RA02_VALID1 (# 1076) */, NULL /* RA02_VALID2 (# 1077) */, NULL /* RA02_VALID3 (# 1078) */, NULL /* RA02_VALID4 (# 1079) */, NULL /* RA02_VALID5 (# 1080) */, NULL /* RA02_VALID6 (# 1081) */, NULL /* RA02_VALID7 (# 1082) */, NULL /* RA02_VALID8 (# 1083) */, NULL /* RA02_VALID9 (# 1084) */, NULL /* RA02_VALID10 (# 1085) */, NULL /* RA02_VALID11 (# 1086) */, NULL /* RA03_ACT (# 1087) */, NULL /* RA03_ACT1 (# 1088) */, NULL /* RA03_ACT2 (# 1089) */, NULL /* RA03_ACT3 (# 1090) */, NULL /* RA03_ACT4 (# 1091) */, NULL /* RA03_ACT5 (# 1092) */, NULL /* RA03_ACT6 (# 1093) */, NULL /* RA03_ACT7 (# 1094) */, NULL /* RA03_ACT8 (# 1095) */, NULL /* RA03_ACT9 (# 1096) */, NULL /* RA03_ACT10 (# 1097) */, NULL /* RA03_ACT11 (# 1098) */, NULL /* RA03_CV (# 1099) */, NULL /* RA03_CV1 (# 1100) */, NULL /* RA03_CV2 (# 1101) */, NULL /* RA03_CV3 (# 1102) */, NULL /* RA03_CV4 (# 1103) */, NULL /* RA03_CV5 (# 1104) */, NULL /* RA03_CV6 (# 1105) */, NULL /* RA03_CV7 (# 1106) */, NULL /* RA03_CV8 (# 1107) */, NULL /* RA03_CV9 (# 1108) */, NULL /* RA03_CV10 (# 1109) */, NULL /* RA03_CV11 (# 1110) */, NULL /* RA03_MG (# 1111) */, NULL /* RA03_MG1 (# 1112) */, NULL /* RA03_MG2 (# 1113) */, NULL /* RA03_MG3 (# 1114) */, NULL /* RA03_MG4 (# 1115) */, NULL /* RA03_MG5 (# 1116) */, NULL /* RA03_MG6 (# 1117) */, NULL /* RA03_MG7 (# 1118) */, NULL /* RA03_MG8 (# 1119) */, NULL /* RA03_MG9 (# 1120) */, NULL /* RA03_MG10 (# 1121) */, NULL /* RA03_MG11 (# 1122) */, NULL /* RA03_SPAN (# 1123) */, NULL /* RA03_SPAN1 (# 1124) */, NULL /* RA03_SPAN2 (# 1125) */, NULL /* RA03_SPAN3 (# 1126) */, NULL /* RA03_SPAN4 (# 1127) */, NULL /* RA03_SPAN5 (# 1128) */, NULL /* RA03_SPAN6 (# 1129) */, NULL /* RA03_SPAN7 (# 1130) */, NULL /* RA03_SPAN8 (# 1131) */, NULL /* RA03_SPAN9 (# 1132) */, NULL /* RA03_SPAN10 (# 1133) */, NULL /* RA03_SPAN11 (# 1134) */, NULL /* RA03_TXTAG (# 1135) */, NULL /* RA03_TXTAG1 (# 1136) */, NULL /* RA03_TXTAG2 (# 1137) */, NULL /* RA03_TXTAG3 (# 1138) */, NULL /* RA03_TXTAG4 (# 1139) */, NULL /* RA03_TXTAG5 (# 1140) */, NULL /* RA03_TXTAG6 (# 1141) */, NULL /* RA03_TXTAG7 (# 1142) */, NULL /* RA03_TXTAG8 (# 1143) */, NULL /* RA03_TXTAG9 (# 1144) */, NULL /* RA03_TXTAG10 (# 1145) */, NULL /* RA03_TXTAG11 (# 1146) */, NULL /* RA03_VALID (# 1147) */, NULL /* RA03_VALID1 (# 1148) */, NULL /* RA03_VALID2 (# 1149) */, NULL /* RA03_VALID3 (# 1150) */, NULL /* RA03_VALID4 (# 1151) */, NULL /* RA03_VALID5 (# 1152) */, NULL /* RA03_VALID6 (# 1153) */, NULL /* RA03_VALID7 (# 1154) */, NULL /* RA03_VALID8 (# 1155) */, NULL /* RA03_VALID9 (# 1156) */, NULL /* RA03_VALID10 (# 1157) */, NULL /* RA03_VALID11 (# 1158) */, "RCC.BAS" /* RMON_BAS (# 1159) */, "RCC.CAC" /* RMON_CAC (# 1160) */, NULL /* RMON_COUNTER (# 1161) */, "RCSH.COUNTER" /* RMON_HIGH_COUNTER (# 1162) */, "RCSL.COUNTER" /* RMON_LOW_COUNTER (# 1163) */, "RCC.OFFSET" /* RMON_OFFSET (# 1164) */, "RCC.PORTC" /* RMON_PORTC (# 1165) */, "TFA0.ATF0" /* TYPE_FILTER_ATF (# 1166) */, "TFA0.ATF1" /* TYPE_FILTER_ATF1 (# 1167) */, "TFA0.ATF2" /* TYPE_FILTER_ATF2 (# 1168) */, "TFA0.ATF3" /* TYPE_FILTER_ATF3 (# 1169) */, "TFA0.ATF4" /* TYPE_FILTER_ATF4 (# 1170) */, "TFA0.ATF5" /* TYPE_FILTER_ATF5 (# 1171) */, "TFA0.ATF6" /* TYPE_FILTER_ATF6 (# 1172) */, "TFA0.ATF7" /* TYPE_FILTER_ATF7 (# 1173) */, "TFA1.QTF0" /* TYPE_FILTER_QTF (# 1174) */, "TFA1.QTF1" /* TYPE_FILTER_QTF1 (# 1175) */, "TFA1.QTF2" /* TYPE_FILTER_QTF2 (# 1176) */, "TFA1.QTF3" /* TYPE_FILTER_QTF3 (# 1177) */, "TFA1.QTF4" /* TYPE_FILTER_QTF4 (# 1178) */, "TFA1.QTF5" /* TYPE_FILTER_QTF5 (# 1179) */, "TFA1.QATF6" /* TYPE_FILTER_QTF6 (# 1180) */, "TFA1.QATF7" /* TYPE_FILTER_QTF7 (# 1181) */, NULL /* TYPE_FILTER_VCET0 (# 1182) */, NULL /* TYPE_FILTER_VCET01 (# 1183) */, NULL /* TYPE_FILTER_VCET02 (# 1184) */, NULL /* TYPE_FILTER_VCET03 (# 1185) */, NULL /* TYPE_FILTER_VCET1 (# 1186) */, NULL /* TYPE_FILTER_VCET11 (# 1187) */, NULL /* TYPE_FILTER_VCET12 (# 1188) */, NULL /* TYPE_FILTER_VCET13 (# 1189) */, "TF0.VCET" /* TYPE_FILTER_VCET_ALL (# 1190) */, "TF1.VCET" /* TYPE_FILTER_VCET_ALL1 (# 1191) */, "TF2.VCET" /* TYPE_FILTER_VCET_ALL2 (# 1192) */, "TF3.VCET" /* TYPE_FILTER_VCET_ALL3 (# 1193) */, "TF4.VCET" /* TYPE_FILTER_VCET_ALL4 (# 1194) */, "TF5.VCET" /* TYPE_FILTER_VCET_ALL5 (# 1195) */, "TF6.VCET" /* TYPE_FILTER_VCET_ALL6 (# 1196) */, "TF7.VCET" /* TYPE_FILTER_VCET_ALL7 (# 1197) */, "VF0H.M" /* VLAN_FILTER_M (# 1198) */, "VF1H.M" /* VLAN_FILTER_M1 (# 1199) */, "VF2H.M" /* VLAN_FILTER_M2 (# 1200) */, "VF3H.M" /* VLAN_FILTER_M3 (# 1201) */, "VF4H.M" /* VLAN_FILTER_M4 (# 1202) */, "VF5H.M" /* VLAN_FILTER_M5 (# 1203) */, "VF6H.M" /* VLAN_FILTER_M6 (# 1204) */, "VF7H.M" /* VLAN_FILTER_M7 (# 1205) */, "VF8H.M" /* VLAN_FILTER_M8 (# 1206) */, "VF9H.M" /* VLAN_FILTER_M9 (# 1207) */, "VF10H.M" /* VLAN_FILTER_M10 (# 1208) */, "VF11H.M" /* VLAN_FILTER_M11 (# 1209) */, "VF12H.M" /* VLAN_FILTER_M12 (# 1210) */, "VF13H.M" /* VLAN_FILTER_M13 (# 1211) */, "VF14H.M" /* VLAN_FILTER_M14 (# 1212) */, "VF15H.M" /* VLAN_FILTER_M15 (# 1213) */, "VF0H.TM" /* VLAN_FILTER_TM (# 1214) */, "VF1H.TM" /* VLAN_FILTER_TM1 (# 1215) */, "VF2H.TM" /* VLAN_FILTER_TM2 (# 1216) */, "VF3H.TM" /* VLAN_FILTER_TM3 (# 1217) */, "VF4H.TM" /* VLAN_FILTER_TM4 (# 1218) */, "VF5H.TM" /* VLAN_FILTER_TM5 (# 1219) */, "VF6H.TM" /* VLAN_FILTER_TM6 (# 1220) */, "VF7H.TM" /* VLAN_FILTER_TM7 (# 1221) */, "VF8H.TM" /* VLAN_FILTER_TM8 (# 1222) */, "VF9H.TM" /* VLAN_FILTER_TM9 (# 1223) */, "VF10H.TM" /* VLAN_FILTER_TM10 (# 1224) */, "VF11H.TM" /* VLAN_FILTER_TM11 (# 1225) */, "VF12H.TM" /* VLAN_FILTER_TM12 (# 1226) */, "VF13H.TM" /* VLAN_FILTER_TM13 (# 1227) */, "VF14H.TM" /* VLAN_FILTER_TM14 (# 1228) */, "VF15H.TM" /* VLAN_FILTER_TM15 (# 1229) */, "VF0H.FID" /* VLAN_FILTER_VFID (# 1230) */, "VF1H.FID" /* VLAN_FILTER_VFID1 (# 1231) */, "VF2H.FID" /* VLAN_FILTER_VFID2 (# 1232) */, "VF3H.FID" /* VLAN_FILTER_VFID3 (# 1233) */, "VF4H.FID" /* VLAN_FILTER_VFID4 (# 1234) */, "VF5H.FID" /* VLAN_FILTER_VFID5 (# 1235) */, "VF6H.FID" /* VLAN_FILTER_VFID6 (# 1236) */, "VF7H.FID" /* VLAN_FILTER_VFID7 (# 1237) */, "VF8H.FID" /* VLAN_FILTER_VFID8 (# 1238) */, "VF9H.FID" /* VLAN_FILTER_VFID9 (# 1239) */, "VF10H.FID" /* VLAN_FILTER_VFID10 (# 1240) */, "VF11H.FID" /* VLAN_FILTER_VFID11 (# 1241) */, "VF12H.FID" /* VLAN_FILTER_VFID12 (# 1242) */, "VF13H.FID" /* VLAN_FILTER_VFID13 (# 1243) */, "VF14H.FID" /* VLAN_FILTER_VFID14 (# 1244) */, "VF15H.FID" /* VLAN_FILTER_VFID15 (# 1245) */, "VF0L.VID" /* VLAN_FILTER_VID (# 1246) */, "VF1L.VID" /* VLAN_FILTER_VID1 (# 1247) */, "VF2L.VID" /* VLAN_FILTER_VID2 (# 1248) */, "VF3L.VID" /* VLAN_FILTER_VID3 (# 1249) */, "VF4L.VID" /* VLAN_FILTER_VID4 (# 1250) */, "VF5L.VID" /* VLAN_FILTER_VID5 (# 1251) */, "VF6L.VID" /* VLAN_FILTER_VID6 (# 1252) */, "VF7L.VID" /* VLAN_FILTER_VID7 (# 1253) */, "VF8L.VID" /* VLAN_FILTER_VID8 (# 1254) */, "VF9L.VID" /* VLAN_FILTER_VID9 (# 1255) */, "VF10L.VID" /* VLAN_FILTER_VID10 (# 1256) */, "VF11L.VID" /* VLAN_FILTER_VID11 (# 1257) */, "VF12L.VID" /* VLAN_FILTER_VID12 (# 1258) */, "VF13L.VID" /* VLAN_FILTER_VID13 (# 1259) */, "VF14L.VID" /* VLAN_FILTER_VID14 (# 1260) */, "VF15L.VID" /* VLAN_FILTER_VID15 (# 1261) */, "VF0L.VP" /* VLAN_FILTER_VP (# 1262) */, "VF1L.VP" /* VLAN_FILTER_VP1 (# 1263) */, "VF2L.VP" /* VLAN_FILTER_VP2 (# 1264) */, "VF3L.VP" /* VLAN_FILTER_VP3 (# 1265) */, "VF4L.VP" /* VLAN_FILTER_VP4 (# 1266) */, "VF5L.VP" /* VLAN_FILTER_VP5 (# 1267) */, "VF6L.VP" /* VLAN_FILTER_VP6 (# 1268) */, "VF7L.VP" /* VLAN_FILTER_VP7 (# 1269) */, "VF8L.VP" /* VLAN_FILTER_VP8 (# 1270) */, "VF9L.VP" /* VLAN_FILTER_VP9 (# 1271) */, "VF10L.VP" /* VLAN_FILTER_VP10 (# 1272) */, "VF11L.VP" /* VLAN_FILTER_VP11 (# 1273) */, "VF12L.VP" /* VLAN_FILTER_VP12 (# 1274) */, "VF13L.VP" /* VLAN_FILTER_VP13 (# 1275) */, "VF14L.VP" /* VLAN_FILTER_VP14 (# 1276) */, "VF15L.VP" /* VLAN_FILTER_VP15 (# 1277) */, "VF0L.VV" /* VLAN_FILTER_VV (# 1278) */, "VF1L.VV" /* VLAN_FILTER_VV1 (# 1279) */, "VF2L.VV" /* VLAN_FILTER_VV2 (# 1280) */, "VF3L.VV" /* VLAN_FILTER_VV3 (# 1281) */, "VF4L.VV" /* VLAN_FILTER_VV4 (# 1282) */, "VF5L.VV" /* VLAN_FILTER_VV5 (# 1283) */, "VF6L.VV" /* VLAN_FILTER_VV6 (# 1284) */, "VF7L.VV" /* VLAN_FILTER_VV7 (# 1285) */, "VF8L.VV" /* VLAN_FILTER_VV8 (# 1286) */, "VF9L.VV" /* VLAN_FILTER_VV9 (# 1287) */, "VF10L.VV" /* VLAN_FILTER_VV10 (# 1288) */, "VF11L.VV" /* VLAN_FILTER_VV11 (# 1289) */, "VF12L.VV" /* VLAN_FILTER_VV12 (# 1290) */, "VF13L.VV" /* VLAN_FILTER_VV13 (# 1291) */, "VF14L.VV" /* VLAN_FILTER_VV14 (# 1292) */, "VF15L.VV" /* VLAN_FILTER_VV15 (# 1293) */, /* Last Element (# 1294) */ NULL }; #endif /* #ifdef IFX_ETHSW_DEBUG */