#ifndef _QCOM_QTIMER_
#define _QCOM_QTIMER_
#include <linux/types.h>
#include <asm/fixmap.h>


typedef enum {
    qtim0_v1 = 1,
    qtim0_v2 = 2,
    qtim1_v1 = 3,
    qtim2_v1 = 4,
    qtim3_v1 = 5,
    qtim4_v1 = 6,
    qtim5_v1 = 7,
    qtim6_v1 = 8
} qtimer;

void qtimer_set_next_event(qtimer qtim, unsigned int cycles);

void qtimer_enable(qtimer qtim, uint8_t enable, uint8_t mask_irq);

unsigned int avm_get_profiling_clk_rate_MHzX10(void);

extern const void* __iomem apcs_qtmr_base ;

#define APCS_QTMR_AC_CNTFRQ          apcs_qtmr_base + 0x0
#define APCS_QTMR_AC_CNTSR           apcs_qtmr_base + 0x4
#define APCS_QTMR_AC_CNTTID          apcs_qtmr_base + 0x8
#define APCS_QTMR_AC_CNTACR_n(n)     apcs_qtmr_base + 0x40 + 0x4 * n
#define APCS_QTMR_AC_CNTVOFF_LO_n(n) apcs_qtmr_base + 0x80 + 0x8 * n
#define APCS_QTMR_AC_CNTVOFF_HI_n(n) apcs_qtmr_base + 0x84 + 0x8 * n
#define APCS_QTMR_AC_CFG             apcs_qtmr_base + 0xFC0

#define APCS_F0_QTMR_V1_OFFSET 0x1000
#define APCS_F0_QTMR_V2_OFFSET 0x2000
#define APCS_F1_QTMR_V1_OFFSET 0x3000
#define APCS_F2_QTMR_V1_OFFSET 0x4000
#define APCS_F3_QTMR_V1_OFFSET 0x5000
#define APCS_F4_QTMR_V1_OFFSET 0x6000
#define APCS_F5_QTMR_V1_OFFSET 0x7000
#define APCS_F6_QTMR_V1_OFFSET 0x8000

#define APCS_QTMR_CNTPCT_LO             0x0
#define APCS_QTMR_CNTPCT_HI             0x4
#define APCS_QTMR_CNTVCT_LO             0x8
#define APCS_QTMR_CNTVCT_HI             0xC
#define APCS_QTMR_CNTFRQ                0x10
#define APCS_QTMR_CNTPL0ACR             0x14
#define APCS_QTMR_CNTVOFF_LO            0x18
#define APCS_QTMR_CNTVOFF_HI            0x1C
#define APCS_QTMR_CNTP_CVAL_LO          0x20
#define APCS_QTMR_CNTP_CVAL_HI          0x24
#define APCS_QTMR_CNTP_TVAL             0x28
#define APCS_QTMR_CNTP_CTL              0x2C
#define APCS_QTMR_CNTV_CVAL_LO          0x30
#define APCS_QTMR_CNTV_CVAL_HI          0x34
#define APCS_QTMR_CNTV_TVAL             0x38
#define APCS_QTMR_CNTV_CTL              0x3C

#define APCS_F0_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F0_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F0_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F0_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F0_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F0_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F0_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F0_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F0_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F0_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F0_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F0_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F0_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F0_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F0_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F0_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F0_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL    

#define APCS_F0_QTMR_V2_CNTPCT_LO       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F0_QTMR_V2_CNTPCT_HI       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F0_QTMR_V2_CNTVCT_LO       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F0_QTMR_V2_CNTVCT_HI       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F0_QTMR_V2_CNTFRQ          apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F0_QTMR_V2_CNTPL0ACR       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F0_QTMR_V2_CNTVOFF_LO      apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F0_QTMR_V2_CNTVOFF_HI      apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F0_QTMR_V2_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F0_QTMR_V2_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F0_QTMR_V2_CNTP_TVAL       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F0_QTMR_V2_CNTP_CTL        apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F0_QTMR_V2_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F0_QTMR_V2_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F0_QTMR_V2_CNTV_TVAL       apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F0_QTMR_V2_CNTV_CTL        apcs_qtmr_base + APCS_F0_QTMR_V2_OFFSET + APCS_QTMR_CNTV_CTL    

#define APCS_F1_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F1_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F1_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F1_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F1_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F1_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F1_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F1_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F1_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F1_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F1_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F1_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F1_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F1_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F1_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F1_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F1_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL    

#define APCS_F2_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F2_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F2_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F2_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F2_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F2_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F2_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F2_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F2_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F2_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F2_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F2_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F2_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F2_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F2_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F2_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F2_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL   

#define APCS_F3_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F3_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F3_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F3_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F3_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F3_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F3_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F3_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F3_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F3_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F3_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F3_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F3_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F3_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F3_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F3_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F3_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL   

#define APCS_F4_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F4_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F4_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F4_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F4_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F4_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F4_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F4_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F4_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F4_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F4_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F4_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F4_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F4_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F4_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F4_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F4_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL   

#define APCS_F5_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F5_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F5_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F5_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F5_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F5_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F5_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F5_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F5_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F5_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F5_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F5_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F5_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F5_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F5_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F5_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F5_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL  

#define APCS_F6_QTMR_V1_CNTPCT_LO       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_LO
#define APCS_F6_QTMR_V1_CNTPCT_HI       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTPCT_HI   
#define APCS_F6_QTMR_V1_CNTVCT_LO       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_LO   
#define APCS_F6_QTMR_V1_CNTVCT_HI       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTVCT_HI   
#define APCS_F6_QTMR_V1_CNTFRQ          apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTFRQ      
#define APCS_F6_QTMR_V1_CNTPL0ACR       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTPL0ACR   
#define APCS_F6_QTMR_V1_CNTVOFF_LO      apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_LO  
#define APCS_F6_QTMR_V1_CNTVOFF_HI      apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTVOFF_HI  
#define APCS_F6_QTMR_V1_CNTP_CVAL_LO    apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_LO
#define APCS_F6_QTMR_V1_CNTP_CVAL_HI    apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CVAL_HI
#define APCS_F6_QTMR_V1_CNTP_TVAL       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTP_TVAL   
#define APCS_F6_QTMR_V1_CNTP_CTL        apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTP_CTL    
#define APCS_F6_QTMR_V1_CNTV_CVAL_LO    apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_LO
#define APCS_F6_QTMR_V1_CNTV_CVAL_HI    apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CVAL_HI
#define APCS_F6_QTMR_V1_CNTV_TVAL       apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTV_TVAL   
#define APCS_F6_QTMR_V1_CNTV_CTL        apcs_qtmr_base + APCS_F6_QTMR_V1_OFFSET + APCS_QTMR_CNTV_CTL  

#endif