--- zzzz-none-000/linux-4.4.271/arch/arm/Kconfig	2021-06-03 06:22:09.000000000 +0000
+++ hawkeye-5590-750/linux-4.4.271/arch/arm/Kconfig	2023-04-19 10:22:27.000000000 +0000
@@ -34,10 +34,13 @@
 	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
 	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
+	select HAVE_ARCH_KASAN
 	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
 	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARM_SMCCC if CPU_V7
+	select HAVE_AVM_RTE if AVM_TZ_EXTENSIONS
+	select AVM_FASTIRQ_ARCH_ARM_COMMON
 	select HAVE_BPF_JIT
 	select HAVE_CC_STACKPROTECTOR
 	select HAVE_CONTEXT_TRACKING
@@ -51,6 +54,7 @@
 	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
 	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
+	select HAVE_GCC_PLUGINS
 	select HAVE_GENERIC_DMA_COHERENT
 	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 	select HAVE_IDE if PCI || ISA || PCMCIA
@@ -72,6 +76,7 @@
 	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_SYSCALL_TRACEPOINTS
+	select IOMMU_DMA if IOMMU_SUPPORT
 	select HAVE_UID16
 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
 	select IRQ_FORCED_THREADING
@@ -229,6 +234,9 @@
 config ARCH_MTD_XIP
 	bool
 
+config ARCH_WANT_KMAP_ATOMIC_FLUSH
+	bool
+
 config VECTORS_BASE
 	hex
 	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
@@ -324,7 +332,7 @@
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_HAS_SG_CHAIN
 	select ARM_PATCH_PHYS_VIRT
-	select AUTO_ZRELADDR
+	select AUTO_ZRELADDR if !ARCH_QCOM
 	select CLKSRC_OF
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
@@ -1217,6 +1225,16 @@
 	  relevant cache maintenance functions and sets a specific bit
 	  in the diagnostic control register of the SCU.
 
+config ARM_ERRATA_764369_AVM_A53
+	bool "ARM errata: Special partial implementation of errata 764369 for Cortex-A53"
+	depends on CPU_V7 && SMP
+	help
+	  Despite not being mentioned in the errata notice for the Cortex-A53,
+	  parts of the implementation of erratum 764369 for Cortex-A9 have been
+	  found to be beneficial for Cortex-A53 devices as well, such as the
+	  Hawkeye-based 4060 (see JZ-93302 and #1229). This workaround adds a DSB
+	  instruction before relevant cache maintenance functions.
+
 config ARM_ERRATA_775420
        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
        depends on CPU_V7
@@ -1246,6 +1264,18 @@
 	  loop buffer may deliver incorrect instructions. This
 	  workaround disables the loop buffer to avoid the erratum.
 
+config ARM_ERRATA_814220
+	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+	depends on CPU_V7
+	help
+	  The v7 ARM states that all cache and branch predictor maintenance
+	  operations that do not specify an address execute, relative to
+	  each other, in program order.
+	  However, because of this erratum, an L2 set/way cache maintenance
+	  operation can overtake an L1 set/way cache maintenance operation.
+	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
+	  r0p4, r0p5.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1468,6 +1498,12 @@
 	default 0xB0000000 if VMSPLIT_3G_OPT
 	default 0xC0000000
 
+config KASAN_SHADOW_OFFSET
+	hex
+	default 0x1f000000 if VMSPLIT_1G
+	default 0x5f000000 if VMSPLIT_2G
+	default 0x9f000000
+
 config NR_CPUS
 	int "Maximum number of CPUs (2-32)"
 	range 2 32
@@ -1819,6 +1855,67 @@
 	help
 	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
 
+config AVM_TZ_EXTENSIONS
+	bool
+
+choice
+	prompt "Choose TrustZone implementation"
+	default AVM_TZ_TYPE_QSDK
+	help
+	  This enables distinguishing between TrustZone implementations
+	  (e.g. ATF or QCA's proprietary implementation) wherever necessary.
+
+config AVM_TZ_TYPE_QSDK
+	bool "Use proprietary QCA SDK TrustZone implementation"
+	default n
+	help
+	  This option states whether this platform uses the proprietary QCA TrustZone as included in the QSDK.
+
+config AVM_TZ_TYPE_QCA_RTE
+	bool "Use QCA TrustZone with RTE support"
+	depends on ARCH_IPQ40XX || ARCH_IPQ807x
+	select AVM_TZ_EXTENSIONS
+	default n
+	help
+	  This option states whether this platform uses the QCA TrustZone with RTE support.
+
+
+config AVM_TZ_TYPE_ATF_RTE
+	bool "Use ARM Trusted Firmware (ATF) TrustZone with RTE support"
+	depends on ARCH_IPQ5018 && QCOM_SCM
+	select AVM_TZ_EXTENSIONS
+	default n
+	help
+	  This option states whether this platform uses the ATF TrustZone with RTE support.
+
+endchoice
+
+
+config AVM_FASTIRQ_ARCH_ARM_COMMON
+	bool
+
+if HAVE_AVM_RTE
+
+config AVM_FASTIRQ
+	def_bool y
+
+config AVM_FASTIRQ_TZ
+	bool "AVM fast interrupt with trust zone support"
+	depends on AVM_FASTIRQ && AVM_TZ_EXTENSIONS
+	default n
+	help
+	  This option enables fast interrupt support via trust zone for cortex boards.
+
+config AVM_FASTIRQ_DEBUG
+	bool "AVM firq protection checking"
+	depends on AVM_FASTIRQ_TZ
+	default n
+	help
+	   Some protection checks by fastirq-usage versus linux-os
+
+endif
+
+
 endmenu
 
 menu "Boot options"