--- zzzz-none-000/linux-4.4.271/arch/arm/boot/dts/qcom-ipq8064.dtsi 2021-06-03 06:22:09.000000000 +0000 +++ hawkeye-5590-750/linux-4.4.271/arch/arm/boot/dts/qcom-ipq8064.dtsi 2023-04-19 10:22:27.000000000 +0000 @@ -1,9 +1,28 @@ +/* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ /dts-v1/; #include "skeleton.dtsi" #include +#include #include #include +#include +#include +#include / { model = "Qualcomm IPQ8064"; @@ -22,6 +41,12 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; + core-supply = <&smb208_s2a>; + voltage-tolerance = <5>; + cpu_fab_threshold = <1000000000>; }; cpu@1 { @@ -32,11 +57,379 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; + core-supply = <&smb208_s2b>; + cpu_fab_threshold = <1000000000>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; + clocks = <&kraitcc 4>; + clock-names = "cache"; + cache-points-kHz = < + /* kHz uV CPU kHz */ + 1200000 1150000 1200000 + 1000000 1100000 600000 + 384000 1100000 384000 + >; + vdd_dig-supply = <&smb208_s1a>; + }; + }; + + thermal-zones { + tsens_tz_sensor0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 0>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor8 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; + }; + + tsens_tz_sensor10 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical-hi { + temperature = <125>; + hysteresis = <2>; + type = "critical_high"; + }; + + cpu-config-hi { + temperature = <105>; + hysteresis = <2>; + type = "configurable_hi"; + }; + + cpu-config-lo { + temperature = <95>; + hysteresis = <2>; + type = "configurable_lo"; + }; + + cpu-critical-low { + temperature = <0>; + hysteresis = <2>; + type = "critical_low"; + }; + }; }; }; @@ -55,10 +448,25 @@ no-map; }; - smem@41000000 { + smem: smem@41000000 { reg = <0x41000000 0x200000>; no-map; }; + + wifi_dump@44000000 { + reg = <0x44000000 0x600000>; + no-map; + }; + + wigig_dump@44400000 { + reg = <0x44400000 0x200000>; + no-map; + }; + + tzapp: tzapp@44600000 { /* TZAPPs */ + reg = <0x44600000 0x200000>; + no-map; + }; }; clocks { @@ -69,6 +477,83 @@ }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + #clock-cells = <1>; + }; + + qcom,pvs { + qcom,pvs-format-a; + qcom,speed0-pvs0-bin-v0 = + < 1400000000 1250000 >, + < 1200000000 1200000 >, + < 1000000000 1150000 >, + < 800000000 1100000 >, + < 600000000 1050000 >, + < 384000000 1000000 >; + + qcom,speed0-pvs1-bin-v0 = + < 1400000000 1175000 >, + < 1200000000 1125000 >, + < 1000000000 1075000 >, + < 800000000 1025000 >, + < 600000000 975000 >, + < 384000000 925000 >; + + qcom,speed0-pvs2-bin-v0 = + < 1400000000 1125000 >, + < 1200000000 1075000 >, + < 1000000000 1025000 >, + < 800000000 995000 >, + < 600000000 925000 >, + < 384000000 875000 >; + + qcom,speed0-pvs3-bin-v0 = + < 1400000000 1050000 >, + < 1200000000 1000000 >, + < 1000000000 950000 >, + < 800000000 900000 >, + < 600000000 850000 >, + < 384000000 800000 >; + }; + + nss-common { + compatible = "qcom,nss-common"; + reg = <0x03000000 0x00001000>; + reg-names = "nss_fpb_base"; + clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>, + <&nss_fabric0_clk>, <&nss_fabric1_clk>; + clock-names = "nss-core-clk", "nss-tcm-clk", "nss-fab0-clk", + "nss-fab0-clk"; + nss_core-supply = <&smb208_s1b>; + nss_core_vdd_nominal = <1100000>; + nss_core_vdd_high = <1150000>; + nss_core_threshold_freq = <733000000>; + }; + + fab-scaling { + compatible = "qcom,fab-scaling"; + clocks = <&apps_fabric_clk>, <&ebi1_clk>; + clock-names = "apps-fab-clk", "ddr-fab-clk"; + fab_freq_high = <533000000>; + fab_freq_nominal = <400000000>; + }; + + qseecom { + compatible = "ipq8064-qseecom"; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq806x"; + }; + qfprom_sec { + compatible = "qcom,qfprom-sec"; + img-addr = <0x44000000>; + img-size = <0x600000>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -90,6 +575,129 @@ reg-names = "lpass-lpaif"; }; + nss0: nss@40000000 { + compatible = "qcom,nss"; + qcom,low-frequency = <110000000>; + qcom,mid-frequency = <550000000>; + qcom,max-frequency = <733000000>; + }; + + nss1: nss@40800000 { + compatible = "qcom,nss"; + qcom,low-frequency = <110000000>; + qcom,mid-frequency = <550000000>; + qcom,max-frequency = <733000000>; + }; + + rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <0 19 0>, + <0 21 0>, + <0 22 0>; + interrupt-names = "ack", + "err", + "wakeup"; + + #address-cells = <1>; + #size-cells = <0>; + + regulators { + compatible = "qcom,rpm-smb208-regulators"; + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; + + cxo_clk: cxo-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "cxo"; + qcom,rpm-clk-freq = <25000000>; + qcom,rpm-clk-active-only; + }; + + pxo_clk: pxo-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "pxo"; + qcom,rpm-clk-freq = <25000000>; + qcom,rpm-clk-active-only; + }; + + ebi1_clk: ebi1-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "ebi1"; + qcom,rpm-clk-freq = <533000000>; + qcom,rpm-clk-active-only; + }; + + apps_fabric_clk: apps-fabric-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "apps-fabric"; + qcom,rpm-clk-freq = <533000000>; + qcom,rpm-clk-active-only; + }; + + nss_fabric0_clk: nss-fabric0-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "nss-fabric0"; + qcom,rpm-clk-freq = <533000000>; + qcom,rpm-clk-active-only; + }; + + nss_fabric1_clk: nss-fabric1-clk { + #clock-cells = <0>; + compatible = "qcom,rpm-clk"; + reg = ; + qcom,rpm-clk-name = "nss-fabric1"; + qcom,rpm-clk-freq = <266500000>; + qcom,rpm-clk-active-only; + }; + }; + + qcom,rpm-log@10c0c8 { + compatible = "qcom,rpm-log"; + reg = <0x0010c0c8 0x00002000>; + qcom,offset-version = <4>; + qcom,reg-offsets = <0x00000080 0x000000A0>; + qcom,rpm-log-len = <0x1800>; + }; + qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; reg = <0x800000 0x4000>; @@ -99,6 +707,33 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 16 0x4>; + + pcie0_pins: pcie0_pinmux { + mux { + pins = "gpio3"; + function = "pcie1_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie1_pins: pcie1_pinmux { + mux { + pins = "gpio48"; + function = "pcie2_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie2_pins: pcie2_pinmux { + mux { + pins = "gpio63"; + function = "pcie3_rst"; + drive-strength = <12>; + bias-disable; + }; + }; }; intc: interrupt-controller@2000000 { @@ -124,16 +759,28 @@ cpu-offset = <0x80000>; }; + tzlog: qca,tzlog { + compatible = "qca,tzlog_ipq806x"; + }; + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; }; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; + }; + saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -146,6 +793,32 @@ regulator; }; + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x1000>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <0 194 0>; + + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + }; + gsbi2: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <2>; @@ -159,7 +832,7 @@ syscon-tcsr = <&tcsr>; - serial@12490000 { + uart2: serial@12490000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, <0x12480000 0x1000>; @@ -197,7 +870,7 @@ syscon-tcsr = <&tcsr>; - gsbi4_serial: serial@16340000 { + uart4: serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, <0x16300000 0x1000>; @@ -205,6 +878,7 @@ clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; status = "disabled"; + tx-watermark = <0>; }; i2c@16380000 { @@ -234,7 +908,7 @@ syscon-tcsr = <&tcsr>; - serial@1a240000 { + uart5: serial@1a240000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, <0x1a200000 0x1000>; @@ -283,7 +957,7 @@ }; sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; + compatible = "qcom,ipq806x-ahci"; reg = <0x29000000 0x180>; interrupts = <0 209 0x0>; @@ -291,9 +965,10 @@ clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, <&gcc SATA_A_CLK>, + <&gcc SATA_CLK_SRC>, <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", + clock-names = "slave_face", "iface", "core", "src", "rxoob", "pmalive"; assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; @@ -301,6 +976,8 @@ phys = <&sata_phy>; phy-names = "sata-phy"; + + ports-implemented = <0x1>; status = "disabled"; }; @@ -310,6 +987,20 @@ qcom,controller-type = "pmic-arbiter"; }; + qfprom: qfprom@700000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0x700000 0x1000>; + status = "okay"; + tsens_calib: calib@400 { + reg = <0x400 0x10>; + }; + tsens_backup: backup@410 { + reg = <0x410 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-ipq8064"; reg = <0x00900000 0x4000>; @@ -317,6 +1008,15 @@ #reset-cells = <1>; }; + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + reg = <0x900000 0x3680>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <0 178 0>; + #thermal-sensor-cells = <1>; + }; + tcsr: syscon@1a400000 { compatible = "qcom,tcsr-ipq8064", "syscon"; reg = <0x1a400000 0x100>; @@ -329,5 +1029,551 @@ #reset-cells = <1>; }; + hs_phy_0: phy@110f8800 { + compatible = "qcom,dwc3-hs-usb-phy"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + ss_phy_0: phy@110f8830 { + compatible = "qcom,dwc3-ss-usb-phy"; + reg = <0x110f8830 0x30>; + + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + usb30@0 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "usb30_mstr_rst"; + + status = "disabled"; + + dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <0 110 0x4>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@100f8800 { + compatible = "qcom,dwc3-hs-usb-phy"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + ss_phy_1: phy@100f8830 { + compatible = "qcom,dwc3-ss-usb-phy"; + reg = <0x100f8830 0x30>; + + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + + #phy-cells = <0>; + status = "disabled"; + }; + + usb30@1 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + status = "disabled"; + + dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <0 205 0x4>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + sfpb_mutex_block: syscon@1200600 { + compatible = "syscon"; + reg = <0x01200600 0x100>; + }; + + pcie0: pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000 + 0x1b502000 0x80 + 0x1b600000 0x100 + 0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi", "int_link_up", "int_link_down"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + phy-tx0-term-offset = <0>; + + status = "disabled"; + }; + + pcie1: pci@1b700000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b700000 0x1000 + 0x1b702000 0x80 + 0x1b800000 0x100 + 0x31f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi", "int_link_up", "int_link_down"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_1_A_CLK>, + <&gcc PCIE_1_H_CLK>, + <&gcc PCIE_1_PHY_CLK>, + <&gcc PCIE_1_AUX_CLK>, + <&gcc PCIE_1_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_1_ACLK_RESET>, + <&gcc PCIE_1_HCLK_RESET>, + <&gcc PCIE_1_POR_RESET>, + <&gcc PCIE_1_PCI_RESET>, + <&gcc PCIE_1_PHY_RESET>, + <&gcc PCIE_1_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + + perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + phy-tx0-term-offset = <0>; + + status = "disabled"; + }; + + pcie2: pci@1b900000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b900000 0x1000 + 0x1b902000 0x80 + 0x1ba00000 0x100 + 0x35f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi", "int_link_up", "int_link_down"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_2_A_CLK>, + <&gcc PCIE_2_H_CLK>, + <&gcc PCIE_2_PHY_CLK>, + <&gcc PCIE_2_AUX_CLK>, + <&gcc PCIE_2_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_2_ACLK_RESET>, + <&gcc PCIE_2_HCLK_RESET>, + <&gcc PCIE_2_POR_RESET>, + <&gcc PCIE_2_PCI_RESET>, + <&gcc PCIE_2_PHY_RESET>, + <&gcc PCIE_2_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; + + perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + phy-tx0-term-offset = <0>; + + status = "disabled"; + }; + + + nand@1ac00000 { + compatible = "qcom,qcom_nand","qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + nandcs@0 { + compatible = "qcom,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; + }; + + adm_dma: dma@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <0 170 0>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + + nss_common: syscon@03000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; + + qsgmii_csr: syscon@1bb00000 { + compatible = "syscon"; + reg = <0x1bb00000 0x000001FF>; + }; + + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac1: ethernet@37200000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37200000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE2_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE2_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac2: ethernet@37400000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37400000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE3_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE3_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac3: ethernet@37600000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37600000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE4_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE4_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + watchdog@208a000 { + compatible = "qcom,kpss-wdt-ipq8064"; + reg = <0x0208a000 0x100>; + reg-names = "kpss_wdt"; + interrupt-names = "bark_irq"; + interrupts = <0 3 0>; + timeout-sec = <10>; + clocks = <&sleep_clk>; + }; + }; + + sfpb_mutex: sfpb-mutex { + compatible = "qcom,sfpb-mutex"; + syscon = <&sfpb_mutex_block 4 4>; + + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem>; + hwlocks = <&sfpb_mutex 3>; + }; + + qcom,msm-imem@2a03f000 { + compatible = "qcom,msm-imem"; + reg = <0x2a03f000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x2A03F000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + download_mode@0 { + compatible = "qcom,msm-imem-download_mode"; + reg = <0x0 8>; + #address-cells = <1>; + #size-cells = <1>; + + l2_dump_offset@14 { + compatible = "qcom,msm-imem-l2_dump_offset"; + reg = <0x14 8>; + }; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + l2_dump_offset@14 { + compatible = "qcom,msm-imem-l2_dump_offset"; + reg = <0x14 8>; + }; + + qcom,cache_dump { + compatible = "qcom,cache_dump"; + qcom,l1-dump-size = <0x100000>; + qcom,l2-dump-size = <0x200000>; + }; + }; + + qcom,restart_reason { + compatible = "qcom,restart_reason"; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8"; + }; + + /* Fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdcc1bam:dma@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <0 98 0>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc3bam:dma@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <0 96 0>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + #mmc-ddr-1_8v; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; }; };