--- zzzz-none-000/linux-4.4.271/arch/mips/ath79/irq.c 2021-06-03 06:22:09.000000000 +0000 +++ hawkeye-5590-750/linux-4.4.271/arch/mips/ath79/irq.c 2023-04-19 10:22:28.000000000 +0000 @@ -26,6 +26,16 @@ #include "common.h" #include "machtypes.h" +#if defined(CONFIG_AVM_POWER) +#include +#endif +#if defined(CONFIG_AVM_SIMPLE_PROFILING) +#include +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ + +static struct irq_chip ip2_chip; +static struct irq_chip ip3_chip; + static void ath79_misc_irq_handler(struct irq_desc *desc) { void __iomem *base = ath79_reset_base; @@ -41,8 +51,13 @@ while (pending) { int bit = __ffs(pending); - +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + avm_simple_profiling_log(avm_profile_data_type_hw_irq_begin, (unsigned int)(irq_desc + ATH79_MISC_IRQ(bit)), ATH79_MISC_IRQ(bit)); +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ generic_handle_irq(ATH79_MISC_IRQ(bit)); +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + avm_simple_profiling_log(avm_profile_data_type_hw_irq_end, (unsigned int)(irq_desc + ATH79_MISC_IRQ(bit)), ATH79_MISC_IRQ(bit)); +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ pending &= ~BIT(bit); } } @@ -105,7 +120,11 @@ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x() || - soc_is_qca955x()) + soc_is_qca953x() || + soc_is_qca955x() || + soc_is_qca956x() || + soc_is_qcn550x() || + soc_is_tp9343()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -142,12 +161,39 @@ for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } +static void qca953x_ip2_irq_dispatch(struct irq_desc *desc) +{ + u32 status; + + status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); + + if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { + ath79_ddr_wb_flush(3); + generic_handle_irq(ATH79_IP2_IRQ(0)); + } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { + ath79_ddr_wb_flush(4); + generic_handle_irq(ATH79_IP2_IRQ(1)); + } else { + spurious_interrupt(); + } +} + +static void qca953x_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); +} + static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; @@ -207,15 +253,13 @@ for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); for (i = ATH79_IP3_IRQ_BASE; i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); } @@ -234,26 +278,196 @@ -1, -1, -1, -1, -1, -1, -1, -1, }; -asmlinkage void plat_irq_dispatch(void) +static void qca956x_ip2_irq_dispatch(struct irq_desc *desc) { - unsigned long pending; - int irq; + u32 status; - pending = read_c0_status() & read_c0_cause() & ST0_IM; + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL; - if (!pending) { + if (status == 0) { spurious_interrupt(); return; } - pending >>= CAUSEB_IP; - while (pending) { + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(0)); + } + + if (status & QCA956X_EXT_INT_WMAC_ALL) { + /* TODO: flsuh DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(1)); + } +} + +static void qca956x_ip3_irq_dispatch(struct irq_desc *desc) +{ + u32 status; + + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); + status &= QCA956X_EXT_INT_PCIE_RC2_ALL | + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2; + + if (status == 0) { + spurious_interrupt(); + return; + } + + if (status & QCA956X_EXT_INT_USB1) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(0)); + } + + if (status & QCA956X_EXT_INT_USB2) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(1)); + } + + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(2)); + } +} + +static void qca956x_qcn550x_enable_timer_cb(void) +{ + u32 misc; + + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); +} + +static void qca956x_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); + + /* QCA956x timer init workaround has to be applied right before setting + * up the clock. Else, there will be no jiffies */ + late_time_init = &qca956x_qcn550x_enable_timer_cb; +} + +static void qcn550x_ip2_irq_dispatch(struct irq_desc *desc) +{ + u32 status; + + status = ath79_reset_rr(QCN550X_RESET_REG_EXT_INT_STATUS); + status &= QCN550X_EXT_INT_PCIE_RC1_ALL | QCN550X_EXT_INT_WMAC_ALL; + + if (status == 0) { + spurious_interrupt(); + return; + } + + if (status & QCN550X_EXT_INT_PCIE_RC1_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(0)); + } + + if (status & QCN550X_EXT_INT_WMAC_ALL) { + /* TODO: flsuh DDR? */ + generic_handle_irq(ATH79_IP2_IRQ(1)); + } +} + +static void qcn550x_ip3_irq_dispatch(struct irq_desc *desc) +{ + u32 status; + + status = ath79_reset_rr(QCN550X_RESET_REG_EXT_INT_STATUS); + status &= QCN550X_EXT_INT_PCIE_RC2_ALL | + QCN550X_EXT_INT_USB1; + + if (status == 0) { + spurious_interrupt(); + return; + } + + if (status & QCN550X_EXT_INT_USB1) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(0)); + } + + if (status & QCN550X_EXT_INT_PCIE_RC2_ALL) { + /* TODO: flush DDR? */ + generic_handle_irq(ATH79_IP3_IRQ(2)); + } +} + +static void qcn550x_irq_init(void) +{ + int i; + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qcn550x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qcn550x_ip3_irq_dispatch); + + /* QCN550x timer init workaround has to be applied right before setting + * up the clock. Else, there will be no jiffies + */ + late_time_init = &qca956x_qcn550x_enable_timer_cb; +} + +#if defined(CONFIG_AVM_SIMPLE_PROFILING) +asmlinkage void plat_irq_dispatch(struct pt_regs *regs __maybe_unused) +#else +asmlinkage void plat_irq_dispatch(void) +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ +{ + unsigned long pending; + int irq; + +#if defined(CONFIG_AVM_POWER) + avm_cpu_wait_end(); /*--- auch wenn es r4k_wait_irqoff gibt: trotzdem aufrufen, um system-load-Ausgabe zu triggern ---*/ +#endif/*--- #if defined(CONFIG_AVM_POWER) ---*/ + +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + avm_simple_profiling_enter_irq_context(regs->cp0_epc, regs->regs[31]); +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ + + do { + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (!pending) { + spurious_interrupt(); + return; + } + + pending >>= CAUSEB_IP; + irq = fls(pending) - 1; if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1) ath79_ddr_wb_flush(irq_wb_chan[irq]); +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + avm_simple_profiling_log(avm_profile_data_type_hw_irq_begin, MIPS_CPU_IRQ_BASE + irq, irq); +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ do_IRQ(MIPS_CPU_IRQ_BASE + irq); +#if defined(CONFIG_AVM_SIMPLE_PROFILING) + avm_simple_profiling_log(avm_profile_data_type_hw_irq_end, MIPS_CPU_IRQ_BASE + irq, irq); +#endif /*--- #if defined(CONFIG_AVM_SIMPLE_PROFILING) ---*/ pending &= ~BIT(irq); - } + } while(pending); } #ifdef CONFIG_IRQCHIP @@ -268,6 +482,28 @@ .map = misc_map, }; +static int ip2_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + irq_set_chip_and_handler(irq, &ip2_chip, handle_level_irq); + return 0; +} + +static const struct irq_domain_ops ip2_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = ip2_map, +}; + +static int ip3_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + irq_set_chip_and_handler(irq, &ip3_chip, handle_level_irq); + return 0; +} + +static const struct irq_domain_ops ip3_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = ip3_map, +}; + static int __init ath79_misc_intc_of_init( struct device_node *node, struct device_node *parent) { @@ -288,7 +524,6 @@ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); - irq_set_chained_handler(irq, ath79_misc_irq_handler); return 0; @@ -314,6 +549,66 @@ IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc", ar7240_misc_intc_of_init); +static int __init ath79_ip2_irq_of_init( + struct device_node *node, struct device_node *parent) +{ + struct irq_domain *domain; + int irq; + + irq = irq_of_parse_and_map(node, 0); + if (!irq) + panic("Failed to get IP2 IRQ"); + + domain = irq_domain_add_legacy(node, ATH79_IP2_IRQ_COUNT, + ATH79_IP2_IRQ_BASE, 0, &ip2_irq_domain_ops, NULL); + if (!domain) + panic("Failed to add IP2 irqdomain"); + + if (soc_is_ar934x()) + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + else if (soc_is_qca953x()) + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); + else if (soc_is_qca955x()) + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); + else if (soc_is_qca956x() || soc_is_tp9343()) + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); + else if (soc_is_qcn550x()) + irq_set_chained_handler(ATH79_CPU_IRQ(2), qcn550x_ip2_irq_dispatch); + + return 0; +} + +IRQCHIP_DECLARE(ath79_ip2_intc, "qca,ath79-ip2-intc", + ath79_ip2_irq_of_init); + +static int __init ath79_ip3_irq_of_init( + struct device_node *node, struct device_node *parent) +{ + struct irq_domain *domain; + int irq; + + irq = irq_of_parse_and_map(node, 0); + if (!irq) + panic("Failed to get IP3 IRQ"); + + domain = irq_domain_add_legacy(node, ATH79_IP3_IRQ_COUNT, + ATH79_IP3_IRQ_BASE, 0, &ip3_irq_domain_ops, NULL); + if (!domain) + panic("Failed to add IP3 irqdomain"); + if (soc_is_qca955x()) + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); + else if (soc_is_qca956x() || soc_is_tp9343()) { + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); + } else if (soc_is_qcn550x()) { + irq_set_chained_handler(ATH79_CPU_IRQ(3), qcn550x_ip3_irq_dispatch); + } + + return 0; +} + +IRQCHIP_DECLARE(ath79_ip3_intc, "qca,ath79-ip3-intc", + ath79_ip3_irq_of_init); + static int __init ar79_cpu_intc_of_init( struct device_node *node, struct device_node *parent) { @@ -351,10 +646,47 @@ #endif +static void ath79_ip2_disable(struct irq_data *data) +{ + disable_irq(ATH79_CPU_IRQ(2)); +} + +static void ath79_ip2_enable(struct irq_data *data) +{ + enable_irq(ATH79_CPU_IRQ(2)); +} + +static void ath79_ip3_disable(struct irq_data *data) +{ + disable_irq(ATH79_CPU_IRQ(3)); +} + +static void ath79_ip3_enable(struct irq_data *data) +{ + enable_irq(ATH79_CPU_IRQ(3)); +} + void __init arch_init_irq(void) { - if (mips_machtype == ATH79_MACH_GENERIC_OF) { + ip2_chip = dummy_irq_chip; + ip2_chip.irq_disable = ath79_ip2_disable; + ip2_chip.irq_enable = ath79_ip2_enable; + + ip3_chip = dummy_irq_chip; + ip3_chip.irq_disable = ath79_ip3_disable; + ip3_chip.irq_enable = ath79_ip3_enable; + + if (mips_machtype == ATH79_MACH_GENERIC_OF || + ath79_mach_is_avm(mips_machtype)) { irqchip_init(); + if (soc_is_qca956x() || soc_is_tp9343() || soc_is_qcn550x()) { + /* + * QCA956x timer init workaround has to be applied + * right before setting up the clock. Else, there will + * be no jiffies + */ + late_time_init = &qca956x_qcn550x_enable_timer_cb; + } return; } @@ -362,7 +694,7 @@ soc_is_ar913x() || soc_is_ar933x()) { irq_wb_chan[2] = 3; irq_wb_chan[3] = 2; - } else if (soc_is_ar934x()) { + } else if (soc_is_ar934x() || soc_is_qca953x()) { irq_wb_chan[3] = 2; } @@ -371,6 +703,12 @@ if (soc_is_ar934x()) ar934x_ip2_irq_init(); + else if (soc_is_qca953x()) + qca953x_irq_init(); else if (soc_is_qca955x()) qca955x_irq_init(); + else if (soc_is_qca956x() || soc_is_tp9343()) + qca956x_irq_init(); + else if (soc_is_qcn550x()) + qcn550x_irq_init(); }