--- zzzz-none-000/linux-4.4.271/arch/mips/include/asm/mach-ath79/ath79.h 2021-06-03 06:22:09.000000000 +0000 +++ hawkeye-5590-750/linux-4.4.271/arch/mips/include/asm/mach-ath79/ath79.h 2023-04-19 10:22:28.000000000 +0000 @@ -32,8 +32,12 @@ ATH79_SOC_AR9341, ATH79_SOC_AR9342, ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, ATH79_SOC_QCA9556, ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA956X, + ATH79_SOC_QCN5502, }; extern enum ath79_soc_type ath79_soc; @@ -100,6 +104,16 @@ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); } +static inline int soc_is_qca9533(void) +{ + return ath79_soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(void) +{ + return soc_is_qca9533(); +} + static inline int soc_is_qca9556(void) { return ath79_soc == ATH79_SOC_QCA9556; @@ -115,8 +129,51 @@ return soc_is_qca9556() || soc_is_qca9558(); } +static inline int soc_is_tp9343(void) +{ + return ath79_soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(void) +{ + return ath79_soc == ATH79_SOC_QCA956X; +} + +static inline int soc_is_qca9563(void) +{ + return ath79_soc == ATH79_SOC_QCA956X; +} + +static inline int soc_is_qca956x(void) +{ + return soc_is_qca9561() || soc_is_qca9563(); +} + +static inline int is_qca9558(void) { + return ath79_soc == ATH79_SOC_QCA9558; +} + +static inline int is_qca9556(void) { + return ath79_soc == ATH79_SOC_QCA9556; +} + +static inline int is_qca956x(void) { + return ath79_soc == ATH79_SOC_QCA956X; +} + +static inline int soc_is_qcn5502(void) +{ + return ath79_soc == ATH79_SOC_QCN5502; +} + +static inline int soc_is_qcn550x(void) +{ + return soc_is_qcn5502(); +} + void ath79_ddr_set_pci_windows(void); +extern void __iomem *ath79_gpio_base; extern void __iomem *ath79_pll_base; extern void __iomem *ath79_reset_base; @@ -143,5 +200,9 @@ void ath79_device_reset_set(u32 mask); void ath79_device_reset_clear(u32 mask); +u32 ath79_device_reset_get(u32 mask); + +void ath79_flash_acquire(void); +void ath79_flash_release(void); #endif /* __ASM_MACH_ATH79_H */