--- zzzz-none-000/linux-4.4.271/drivers/hwtracing/coresight/coresight-priv.h 2021-06-03 06:22:09.000000000 +0000 +++ hawkeye-5590-750/linux-4.4.271/drivers/hwtracing/coresight/coresight-priv.h 2023-04-19 10:22:28.000000000 +0000 @@ -1,4 +1,4 @@ -/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2012, 2016 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -32,7 +32,9 @@ #define CORESIGHT_DEVTYPE 0xfcc #define TIMEOUT_US 100 +#define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb)) #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define BVAL(val, n) ((val & BIT(n)) >> n) static inline void CS_LOCK(void __iomem *addr) { @@ -52,6 +54,27 @@ } while (0); } +static inline bool coresight_authstatus_enabled(void __iomem *addr) +{ + int ret; + unsigned auth_val; + + if (!addr) + return false; + + auth_val = readl_relaxed(addr + CORESIGHT_AUTHSTATUS); + + if ((0x2 == BMVAL(auth_val, 0, 1)) || + (0x2 == BMVAL(auth_val, 2, 3)) || + (0x2 == BMVAL(auth_val, 4, 5)) || + (0x2 == BMVAL(auth_val, 6, 7))) + ret = false; + else + ret = true; + + return ret; +} + #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X extern int etm_readl_cp14(u32 off, unsigned int *val); extern int etm_writel_cp14(u32 off, u32 val); @@ -60,4 +83,17 @@ static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } #endif +#ifdef CONFIG_CORESIGHT_CSR +extern void msm_qdss_csr_enable_bam_to_usb(void); +extern void msm_qdss_csr_disable_bam_to_usb(void); +extern void msm_qdss_csr_disable_flush(void); +extern int coresight_csr_hwctrl_set(uint64_t addr, uint32_t val); +#else +static inline void msm_qdss_csr_enable_bam_to_usb(void) {} +static inline void msm_qdss_csr_disable_bam_to_usb(void) {} +static inline void msm_qdss_csr_disable_flush(void) {} +static inline int coresight_csr_hwctrl_set(uint64_t addr, + uint32_t val) { return -EINVAL; } +#endif + #endif