--- zzzz-none-000/linux-4.4.271/drivers/mtd/spi-nor/spi-nor.c	2021-06-03 06:22:09.000000000 +0000
+++ hawkeye-5590-750/linux-4.4.271/drivers/mtd/spi-nor/spi-nor.c	2023-04-19 10:22:29.000000000 +0000
@@ -270,7 +270,7 @@
 	return -ETIMEDOUT;
 }
 
-static int spi_nor_wait_till_ready(struct spi_nor *nor)
+int spi_nor_wait_till_ready(struct spi_nor *nor)
 {
 	return spi_nor_wait_till_ready_with_timeout(nor,
 						    DEFAULT_READY_WAIT_JIFFIES);
@@ -697,9 +697,17 @@
 	{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
 
 	/* GigaDevice */
+	{ "md25d40",  INFO(0x514013, 0, 64 * 1024,  8,  SECT_4K) },
+	{ "gd25d20",  INFO(0xc84012, 0, 64 * 1024,  4,  SECT_4K) },
+	{ "gd25d40",  INFO(0xc84013, 0, 64 * 1024,  8,  SECT_4K) },
+	{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, SECT_4K) },
 	{ "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64, SECT_4K) },
+	{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024,  64, SECT_4K) },
 	{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
+	{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, SECT_4K) },
+	{ "gd25lb256e", INFO(0xc86719, 0, 4 * 1024, 8192, SECT_4K)},
+	{ "gd25lb128d", INFO(0xc86018, 0, 4 * 1024, 4096, SECT_4K)},
 
 	/* Intel/Numonyx -- xxxs33b */
 	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },
@@ -715,6 +723,9 @@
 	{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 
+	/* ISSI */
+	{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },
+
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },
 	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
@@ -724,13 +735,18 @@
 	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, 0) },
 	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
 	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, 0) },
+	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, 0) },
+	{ "mx25u3235f",  INFO(0xc22536, 0, 64 * 1024, 64, 0) },
 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+	{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256, SECT_4K) },
 	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
 	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
 	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
 	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
 	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
+	{ "mx66u1g45gm", INFO(0xc2253b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
+	{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
 
 	/* Micron */
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
@@ -800,6 +816,7 @@
 	{ "m25p32",  INFO(0x202016,  0,  64 * 1024,  64, 0) },
 	{ "m25p64",  INFO(0x202017,  0,  64 * 1024, 128, 0) },
 	{ "m25p128", INFO(0x202018,  0, 256 * 1024,  64, 0) },
+	{ "m25q256a", INFO(0x20bb19,  0, 64 * 1024,  512, 0) },
 
 	{ "m25p05-nonjedec",  INFO(0, 0,  32 * 1024,   2, 0) },
 	{ "m25p10-nonjedec",  INFO(0, 0,  32 * 1024,   4, 0) },
@@ -840,6 +857,7 @@
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
@@ -854,6 +872,54 @@
 	{ },
 };
 
+static bool spi_nor_4byte_cmd_support(struct device_node *np)
+{
+	return of_property_read_bool(np, "support-4byte-cmd");
+}
+
+static int spi_nor_default_config(struct spi_nor *nor,
+			struct device_node *np, struct flash_info *def_id)
+{
+	int ret;
+	u32 jedec, density_def;
+	u16 ext_jedec;
+	bool use_def_sizes;
+
+	use_def_sizes = of_property_read_bool(np, "use-default-sizes");
+	if (!use_def_sizes)
+		return -ENOENT;
+
+	ret = of_property_read_u32(np, "sector-size", &def_id->sector_size);
+	if (ret) {
+		dev_err(nor->dev, "Failed to find sector-size\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "density", &density_def);
+	if (ret) {
+		dev_err(nor->dev, "Failed to find density\n");
+		return ret;
+	}
+
+	def_id->n_sectors = (u32) (density_def / def_id->sector_size);
+
+	ret = nor->read_reg(nor, SPINOR_OP_RDID, def_id->id,
+					SPI_NOR_MAX_ID_LEN);
+	if (ret < 0) {
+		dev_dbg(nor->dev, " error %d reading JEDEC ID\n", ret);
+		return ret;
+	}
+
+	jedec = def_id->id[0] << 16 | def_id->id[1] << 8 | def_id->id[2];
+	ext_jedec = def_id->id[3] << 8 | def_id->id[4];
+	def_id->name = "default";
+	def_id->id_len = !(jedec) ? 0 : (3 + ((ext_jedec) ? 2 : 0));
+	def_id->page_size = 256;
+	def_id->flags = 0;
+
+	return 0;
+}
+
 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
 {
 	int			tmp;
@@ -1118,11 +1184,13 @@
 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
 {
 	const struct flash_info *info = NULL;
+	struct flash_info def_id;
 	struct device *dev = nor->dev;
 	struct mtd_info *mtd = &nor->mtd;
 	struct device_node *np = nor->flash_node;
 	int ret;
 	int i;
+	bool is_default_config = false;
 
 	ret = spi_nor_check(nor);
 	if (ret)
@@ -1133,14 +1201,21 @@
 	/* Try to auto-detect if chip name wasn't specified or not found */
 	if (!info)
 		info = spi_nor_read_id(nor);
-	if (IS_ERR_OR_NULL(info))
-		return -ENOENT;
+	if (IS_ERR_OR_NULL(info)) {
+		/*fall back to default configuration */
+		ret = spi_nor_default_config(nor, np, &def_id);
+		if (ret)
+			return ret;
+
+		info = &def_id;
+		is_default_config = true;
+	}
 
 	/*
 	 * If caller has specified name of flash model that can normally be
 	 * detected using JEDEC, let's verify it.
 	 */
-	if (name && info->id_len) {
+	if (name && info->id_len && !is_default_config) {
 		const struct flash_info *jinfo;
 
 		jinfo = spi_nor_read_id(nor);
@@ -1163,8 +1238,8 @@
 	mutex_init(&nor->lock);
 
 	/*
-	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
-	 * with the software protection bits set
+	 * Atmel, SST and Intel/Numonyx serial nor tend to power
+	 * up with the software protection bits set
 	 */
 
 	if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
@@ -1281,7 +1356,10 @@
 	else if (mtd->size > 0x1000000) {
 		/* enable 4-byte addressing if the device exceeds 16MiB */
 		nor->addr_width = 4;
-		if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
+		if ((JEDEC_MFR(info) == SNOR_MFR_SPANSION) ||
+			(JEDEC_MFR(info) == SNOR_MFR_MACRONIX) ||
+			(JEDEC_MFR(info) == SNOR_MFR_MICRON) ||
+			spi_nor_4byte_cmd_support(np)) {
 			/* Dedicated 4-byte command set */
 			switch (nor->flash_read) {
 			case SPI_NOR_QUAD: