--- zzzz-none-000/linux-4.4.271/drivers/pinctrl/qcom/pinctrl-msm.h	2021-06-03 06:22:09.000000000 +0000
+++ hawkeye-5590-750/linux-4.4.271/drivers/pinctrl/qcom/pinctrl-msm.h	2023-04-19 10:22:29.000000000 +0000
@@ -49,6 +49,7 @@
  * @oe_bit:               Offset in @ctl_reg for controlling output enable.
  * @in_bit:               Offset in @io_reg for the input bit value.
  * @out_bit:              Offset in @io_reg for the output bit value.
+ * @od_bit:		  Offset in @io_reg for controlling output drain.
  * @intr_enable_bit:      Offset in @intr_cfg_reg for enabling the interrupt for this group.
  * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt
  *                        status.
@@ -84,6 +85,9 @@
 	unsigned oe_bit:5;
 	unsigned in_bit:5;
 	unsigned out_bit:5;
+	unsigned od_bit:5;
+	unsigned vm_bit:5;
+	unsigned pull_res:5;
 
 	unsigned intr_enable_bit:5;
 	unsigned intr_status_bit:5;
@@ -98,6 +102,16 @@
 };
 
 /**
+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
+ */
+struct msm_pinctrl_gpio_pull {
+	unsigned no_pull;
+	unsigned pull_down;
+	unsigned pull_up;
+	unsigned keeper;
+};
+
+/**
  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
  * @pins:       An array describing all pins the pin controller affects.
  * @npins:      The number of entries in @pins.
@@ -106,6 +120,7 @@
  * @groups:     An array describing all pin groups the pin SoC supports.
  * @ngroups:    The numbmer of entries in @groups.
  * @ngpio:      The number of pingroups the driver should expose as GPIOs.
+ * @gpio_pull_val: The pull value bit field descriptor.
  */
 struct msm_pinctrl_soc_data {
 	const struct pinctrl_pin_desc *pins;
@@ -115,8 +130,38 @@
 	const struct msm_pingroup *groups;
 	unsigned ngroups;
 	unsigned ngpios;
+	const struct msm_pinctrl_gpio_pull *gpio_pull;
+};
+
+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
+	.no_pull = 0,
+	.pull_down = 1,
+	.keeper = 2,
+	.pull_up = 3,
 };
 
+#define DRV_TYPE_D		0
+#define DRV_TYPE_C		1
+#define DRV_TYPE_B		3
+#define DRV_TYPE_A		7
+
+enum drv_cap {
+	DRV_CAP_HIGH,
+	DRV_CAP_HALF,
+	DRV_CAP_QUARTER,
+};
+
+enum pull_res {
+	RES_10_KOHM,
+	RES_1_5_KOHM,
+	RES_35_KOHM,
+	RES_20_KOHM,
+};
+
+#define HP_1_8V		1
+#define HP_2_8V		0
+#define HP_3_3V		0
+
 int msm_pinctrl_probe(struct platform_device *pdev,
 		      const struct msm_pinctrl_soc_data *soc_data);
 int msm_pinctrl_remove(struct platform_device *pdev);