--- zzzz-none-000/linux-4.4.271/drivers/spi/spi-ath79.c 2021-06-03 06:22:09.000000000 +0000 +++ hawkeye-5590-750/linux-4.4.271/drivers/spi/spi-ath79.c 2023-04-19 10:22:29.000000000 +0000 @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include #include #include @@ -33,6 +36,14 @@ #define ATH79_SPI_RRW_DELAY_FACTOR 12000 #define MHZ (1000 * 1000) +#define ATH79_SPI_CS_LINE_MAX 2 +#define FLASH_16M_SIZE 0x1000000 + +enum ath79_spi_state { + ATH79_SPI_STATE_WAIT_CMD = 0, + ATH79_SPI_STATE_WAIT_READ, +}; + struct ath79_spi { struct spi_bitbang bitbang; u32 ioc_base; @@ -40,6 +51,13 @@ void __iomem *base; struct clk *clk; unsigned rrw_delay; + + enum ath79_spi_state state; + u32 clk_div; + unsigned long read_addr; + unsigned long ahb_rate; + bool is_flash; + struct spi_transfer *read_cmd; }; static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) @@ -78,31 +96,31 @@ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); } - if (spi->chip_select) { + if (spi->cs_gpio >= 0) { /* SPI is normally active-low */ - gpio_set_value(spi->cs_gpio, cs_high); + if (gpio_cansleep(spi->cs_gpio)) + gpio_set_value_cansleep(spi->cs_gpio, cs_high); + else + gpio_set_value(spi->cs_gpio, cs_high); } else { if (cs_high) - sp->ioc_base |= AR71XX_SPI_IOC_CS0; + sp->ioc_base |= AR71XX_SPI_IOC_CS(spi->chip_select); else - sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; - - ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + sp->ioc_base &= ~AR71XX_SPI_IOC_CS(spi->chip_select); } - } static void ath79_spi_enable(struct ath79_spi *sp) { + /* Disable DATA mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_DATA_CTRL, 0x0); + /* enable GPIO mode */ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); /* save CTRL register */ sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); - - /* TODO: setup speed? */ - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); } static void ath79_spi_disable(struct ath79_spi *sp) @@ -116,15 +134,11 @@ static int ath79_spi_setup_cs(struct spi_device *spi) { struct ath79_spi *sp = ath79_spidev_to_sp(spi); + unsigned long flags; int status; - if (spi->chip_select && !gpio_is_valid(spi->cs_gpio)) - return -EINVAL; - status = 0; - if (spi->chip_select) { - unsigned long flags; - + if (spi->cs_gpio >= 0) { flags = GPIOF_DIR_OUT; if (spi->mode & SPI_CS_HIGH) flags |= GPIOF_INIT_LOW; @@ -134,6 +148,10 @@ status = gpio_request_one(spi->cs_gpio, flags, dev_name(&spi->dev)); } else { + if (spi->chip_select > ATH79_SPI_CS_LINE_MAX) { + status = -EINVAL; + return status; + } if (spi->mode & SPI_CS_HIGH) sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; else @@ -141,15 +159,13 @@ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); } - return status; } static void ath79_spi_cleanup_cs(struct spi_device *spi) { - if (spi->chip_select) { + if (spi->cs_gpio >= 0) gpio_free(spi->cs_gpio); - } } static int ath79_spi_setup(struct spi_device *spi) @@ -204,6 +220,164 @@ return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); } +static int ath79_spi_do_read_flash_data(struct spi_device *spi, + struct spi_transfer *t) +{ + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + + /* disable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); + + memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len); + + /* enable GPIO mode */ + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); + + /* restore IOC register */ + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + + return t->len; +} + +/** + * Return true, If requested addr + len is grater than 16M + * Otherwise, return false (First 16M are memory mapped). + */ +static bool ath79_spi_is_addr_grater_than_16m(struct spi_device *spi, + struct spi_transfer *t) +{ + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + + return ((sp->read_addr + t->len) > FLASH_16M_SIZE); +} + +static int ath79_spi_do_read_flash_cmd(struct spi_device *spi, + struct spi_transfer *t) +{ + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int len; + const u8 *p; + + sp->read_addr = 0; + + len = t->len - 1; + + if (t->dummy) + len -= 1; + + p = t->tx_buf; + + while (len--) { + p++; + sp->read_addr <<= 8; + sp->read_addr |= *p; + } + + return t->len; +} + +static bool ath79_spi_is_read_cmd(struct spi_device *spi, + struct spi_transfer *t) +{ + return t->type == SPI_TRANSFER_FLASH_READ_CMD; +} + +static bool ath79_spi_is_data_read(struct spi_device *spi, + struct spi_transfer *t) +{ + return t->type == SPI_TRANSFER_FLASH_READ_DATA; +} + +static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int ret; + + switch (sp->state) { + case ATH79_SPI_STATE_WAIT_CMD: + if (ath79_spi_is_read_cmd(spi, t)) { + ret = ath79_spi_do_read_flash_cmd(spi, t); + sp->state = ATH79_SPI_STATE_WAIT_READ; + sp->read_cmd = t; + } else { + ret = spi_bitbang_bufs(spi, t); + } + break; + + case ATH79_SPI_STATE_WAIT_READ: + if (ath79_spi_is_data_read(spi, t)) { + if (ath79_spi_is_addr_grater_than_16m(spi, t) || + (spi->chip_select == 1)) { + spi_bitbang_bufs(spi, sp->read_cmd); + ret = spi_bitbang_bufs(spi, t); + } else { + ret = ath79_spi_do_read_flash_data(spi, t); + } + } else { + dev_warn(&spi->dev, "flash data read expected\n"); + ret = -EIO; + } + sp->state = ATH79_SPI_STATE_WAIT_CMD; + break; + + default: + BUG(); + } + + return ret; +} + +static int ath79_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int ret; + + ret = spi_bitbang_setup_transfer(spi, t); + if (ret) + return ret; + + if (sp->is_flash) + sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs; + else + sp->bitbang.txrx_bufs = spi_bitbang_bufs; + + return ret; +} + +void ath79_spi_fixup_mac_addr(void) +{ + const u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + char node[20]; + const void *eth; + int idx, off, ret; + + if (!of_aliases) { + pr_err("%s: No /aliases in DT\n", __func__); + return; + } + + for (idx = 0; idx < 2; idx++, art += ETH_ALEN) { + snprintf(node, sizeof(node), "eth%d", idx); + eth = of_get_property(of_aliases, node, NULL); + if (!eth) { + pr_err("%s: No eth%d alias in DT\n", __func__, + idx); + continue; + } + + off = fdt_path_offset(initial_boot_params, eth); + if (off < 0) + pr_err("%s: No eth%d node in DT (%d)\n",__func__, + idx, off); + ret = fdt_setprop_inplace(initial_boot_params, off, + "local-mac-address", art, ETH_ALEN); + if (ret) + pr_err("%s: Set local-mac-address failed for eth%d (%d)\n", + __func__, idx, ret); + } +} + static int ath79_spi_probe(struct platform_device *pdev) { struct spi_master *master; @@ -212,6 +386,7 @@ struct resource *r; unsigned long rate; int ret; + u32 num_cs; master = spi_alloc_master(&pdev->dev, sizeof(*sp)); if (master == NULL) { @@ -223,20 +398,32 @@ master->dev.of_node = pdev->dev.of_node; platform_set_drvdata(pdev, sp); - pdata = dev_get_platdata(&pdev->dev); + sp->state = ATH79_SPI_STATE_WAIT_CMD; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); master->setup = ath79_spi_setup; master->cleanup = ath79_spi_cleanup; - if (pdata) { + + if (master->dev.of_node == NULL) { + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; master->bus_num = pdata->bus_num; master->num_chipselect = pdata->num_chipselect; - } + } else { + sp->is_flash = of_property_read_bool(master->dev.of_node, + "ath79,is-flash"); + if (of_property_read_u32(master->dev.of_node, "num-cs", + &num_cs)) + num_cs = 1; + master->num_chipselect = num_cs; + master->bus_num = of_alias_get_id(master->dev.of_node, "spi"); + } sp->bitbang.master = master; sp->bitbang.chipselect = ath79_spi_chipselect; sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; - sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; + sp->bitbang.setup_transfer = ath79_spi_setup_transfer; sp->bitbang.flags = SPI_CS_HIGH; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -256,7 +443,8 @@ if (ret) goto err_put_master; - rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); + sp->ahb_rate = clk_get_rate(sp->clk); + rate = DIV_ROUND_UP(sp->ahb_rate, MHZ); if (!rate) { ret = -EINVAL; goto err_clk_disable; @@ -266,6 +454,9 @@ dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", sp->rrw_delay); + if (master->dev.of_node != NULL) + ath79_spi_fixup_mac_addr(); + ath79_spi_enable(sp); ret = spi_bitbang_start(&sp->bitbang); if (ret)