--- zzzz-none-000/linux-4.4.271/include/linux/irqchip/arm-gic.h	2021-06-03 06:22:09.000000000 +0000
+++ hawkeye-5590-750/linux-4.4.271/include/linux/irqchip/arm-gic.h	2023-04-19 10:22:30.000000000 +0000
@@ -22,7 +22,7 @@
 #define GIC_CPU_IDENT			0xfc
 #define GIC_CPU_DEACTIVATE		0x1000
 
-#define GICC_ENABLE			0x1
+#define GICC_ENABLE			0x0b
 #define GICC_INT_PRI_THRESHOLD		0xf0
 
 #define GIC_CPU_CTRL_EOImodeNS		(1 << 9)
@@ -47,10 +47,11 @@
 #define GIC_DIST_SGI_PENDING_CLEAR	0xf10
 #define GIC_DIST_SGI_PENDING_SET	0xf20
 
-#define GICD_ENABLE			0x1
+#define GICD_ENABLE			0x3
 #define GICD_DISABLE			0x0
 #define GICD_INT_ACTLOW_LVLTRIG		0x0
 #define GICD_INT_EN_CLR_X32		0xffffffff
+#define GICD_INT_DEF_NONSEC		0xffffffff
 #define GICD_INT_EN_SET_SGI		0x0000ffff
 #define GICD_INT_EN_CLR_PPI		0xffff0000
 #define GICD_INT_DEF_PRI		0xa0
@@ -113,5 +114,10 @@
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
+struct irq_domain *get_irq_domain(void);
+void __iomem *get_dist_base(unsigned int gic_nr);
+void __iomem *get_cpu_base(unsigned int gic_nr);
+extern raw_spinlock_t irq_controller_lock;
+
 #endif /* __ASSEMBLY */
 #endif