--- zzzz-none-000/linux-4.4.60/arch/mips/include/asm/r4kcache.h	2017-04-08 07:53:53.000000000 +0000
+++ jet-2400-727/linux-4.4.60/arch/mips/include/asm/r4kcache.h	2021-03-17 14:36:41.000000000 +0000
@@ -226,7 +226,7 @@
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
+	"	.set "MIPS_ISA_ARCH_LEVEL"					\n"	\
 	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
 	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
 	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
@@ -252,7 +252,7 @@
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
+	"	.set "MIPS_ISA_ARCH_LEVEL"					\n"	\
 	"	cache %1, 0x000(%0); cache %1, 0x020(%0)	\n"	\
 	"	cache %1, 0x040(%0); cache %1, 0x060(%0)	\n"	\
 	"	cache %1, 0x080(%0); cache %1, 0x0a0(%0)	\n"	\
@@ -278,7 +278,7 @@
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
+	"	.set "MIPS_ISA_ARCH_LEVEL"					\n"	\
 	"	cache %1, 0x000(%0); cache %1, 0x040(%0)	\n"	\
 	"	cache %1, 0x080(%0); cache %1, 0x0c0(%0)	\n"	\
 	"	cache %1, 0x100(%0); cache %1, 0x140(%0)	\n"	\
@@ -304,7 +304,7 @@
 	__asm__ __volatile__(						\
 	"	.set push					\n"	\
 	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
+	"	.set "MIPS_ISA_ARCH_LEVEL"					\n"	\
 	"	cache %1, 0x000(%0); cache %1, 0x080(%0)	\n"	\
 	"	cache %1, 0x100(%0); cache %1, 0x180(%0)	\n"	\
 	"	cache %1, 0x200(%0); cache %1, 0x280(%0)	\n"	\
@@ -661,16 +661,48 @@
 						    unsigned long end)	\
 {									\
 	unsigned long lsize = cpu_##desc##_line_size();			\
+	unsigned long lsize_2 = lsize * 2;				\
+	unsigned long lsize_3 = lsize * 3;				\
+	unsigned long lsize_4 = lsize * 4;				\
+	unsigned long lsize_5 = lsize * 5;				\
+	unsigned long lsize_6 = lsize * 6;				\
+	unsigned long lsize_7 = lsize * 7;				\
+	unsigned long lsize_8 = lsize * 8;				\
 	unsigned long addr = start & ~(lsize - 1);			\
-	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+	unsigned long aend = (end + lsize - 1) & ~(lsize - 1);		\
+	int lines = (aend - addr) / lsize;				\
 									\
 	__##pfx##flush_prologue						\
 									\
-	while (1) {							\
+	while (lines >= 8) {						\
+		prot##cache_op(hitop, addr);				\
+		prot##cache_op(hitop, addr + lsize);			\
+		prot##cache_op(hitop, addr + lsize_2);			\
+		prot##cache_op(hitop, addr + lsize_3);			\
+		prot##cache_op(hitop, addr + lsize_4);			\
+		prot##cache_op(hitop, addr + lsize_5);			\
+		prot##cache_op(hitop, addr + lsize_6);			\
+		prot##cache_op(hitop, addr + lsize_7);			\
+		addr += lsize_8;					\
+		lines -= 8;						\
+	}								\
+									\
+	if (lines & 0x4) {						\
+		prot##cache_op(hitop, addr);				\
+		prot##cache_op(hitop, addr + lsize);			\
+		prot##cache_op(hitop, addr + lsize_2);			\
+		prot##cache_op(hitop, addr + lsize_3);			\
+		addr += lsize_4;					\
+	}								\
+									\
+	if (lines & 0x2) {						\
+		prot##cache_op(hitop, addr);				\
+		prot##cache_op(hitop, addr + lsize);			\
+		addr += lsize_2;					\
+	}								\
+									\
+	if (lines & 0x1) {						\
 		prot##cache_op(hitop, addr);				\
-		if (addr == aend)					\
-			break;						\
-		addr += lsize;						\
 	}								\
 									\
 	__##pfx##flush_epilogue						\