// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/dts-v1/;

#include "ipq9574-avm-common.dtsi"
#include "ipq9574-default-memory.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "AVM Alder Evalboard 01";

	soc {
		pinctrl@1000000 {
			/* HW-specific pin configuration */
			spi_0_pins: spi-0-pins {
				pins = "gpio11", "gpio12", "gpio13", "gpio14";
				function = "blsp0_spi";
				drive-strength = <8>;
				bias-disable;
			};

		};

		avm_mac_addr_maceth_4: dp6 {
			status = "ok";
			devname = "wan";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <8>;
		};
		avm_mac_addr_maceth_3: dp4 {
			status = "ok";
			devname = "eth3";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <4>;
		};
		avm_mac_addr_maceth_2: dp3 {
			status = "ok";
			devname = "eth2";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <3>;
		};
		avm_mac_addr_maceth_1: dp2 {
			status = "ok";
			devname = "eth1";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <2>;
		};
		avm_mac_addr_maceth_0: dp1 {
			status = "ok";
			devname = "eth0";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <1>;
		};

		pcie0_x1: pci@28000000 {
			perst-gpio = <&tlmm 23 1>;
			status = "ok";
			pcie0_rp {
				#address-cells = <0x5>;
				#size-cells = <0x0>;
				reg = <0 0 0 0 0>;

				qcom,mhi@0 {
					reg = <0 0 0 0 0>;
					qrtr_instance_id = <0x21>;
					memory-region = <0>, <&mhi_region1>;
				};
			};
		};

		pcie0_phy: phy@84000 {
			status = "ok";
		};

		pcie2_x2: pci@20000000 {
			perst-gpio = <&tlmm 29 1>;
			status = "ok";
			pcie2_rp {
				#address-cells = <0x5>;
				#size-cells = <0x0>;
				reg = <0 0 0 0 0>;

#if defined(__CNSS2__)
				qcom,mhi@2 {
					reg = <0 0 0 0 0>;
					qrtr_instance_id = <0x20>;
					memory-region = <0>, <&mhi_region0>;
					status = "ok";
				};
#endif
			};
		};

		pcie2_phy: phy@8c000 {
			status = "ok";
		};

		mdio@90000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "ok";
			pinctrl-0 = <&mdio_pins>;
			pinctrl-names = "default";
			phy-reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW &tlmm 57 GPIO_ACTIVE_LOW>;
			phyaddr_fixup = <0xC90F018>;
			uniphyaddr_fixup = <0xC90F014>;
			mdio_clk_fixup; /* MDIO clock sequence fix up flag */

			phy0: ethernet-phy@0 {
				reg = <1>;
				fixup;
			};
			phy1: ethernet-phy@1 {
				reg = <2>;
				fixup;
			};
			phy2: ethernet-phy@2 {
				reg = <3>;
				fixup;
			};
			phy3: ethernet-phy@3 {
				reg = <4>;
				fixup;
			};
			phy4: ethernet-phy@4 {
				compatible ="ethernet-phy-ieee802.3-c45";
				reg = <8>;
			};
		};

		ess-instance {
			num_devices = <0x1>;
			ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0x5e>; /* lan port bitmap */
				switch_wan_bmp = <0x00>; /* wan port bitmap */
				switch_mac_mode = <0x15>; /* mac mode for uniphy instance0*/
				switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
				switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
				bm_tick_mode = <0>; /* bm tick mode */
				tm_tick_mode = <1>; /* tm tick mode */

				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						phy_address = <1>;
					};
					port@1 {
						port_id = <2>;
						phy_address = <2>;
					};
					port@2 {
						port_id = <3>;
						phy_address = <3>;
					};
					port@3 {
						port_id = <4>;
						phy_address = <4>;
					};
					port@4 {
						port_id = <6>;
						phy_address = <8>;
						ethernet-phy-ieee802.3-c45;
					};
				};
			};
		};
	};
};

&spi_0 {
	status = "ok";
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	cs-select = <0>;

	m25p80@0 {
		compatible = "n25q128a11";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-max-frequency = <50000000>;
	};
};

&wifi0 {
	qcom,board_id = <0x10>;
	status = "ok";
};

&wifi1 {
	/* QCN9000 tgt-mem-mode=0 layout - 53MB
	 * +=========+==============+=========+
	 * |  Region | Start Offset |   Size  |
	 * +---------+--------------+---------+
	 * | HREMOTE |  0x4DD00000  |   35MB  |
	 * +---------+--------------+---------+
	 * | M3 Dump |  0x50000000  |   1MB   |
	 * +---------+--------------+---------+
	 * |   ETR   |  0x50100000  |   1MB   |
	 * +---------+--------------+---------+
	 * |  Caldb  |  0x50200000  |   8MB   |
	 * +---------+--------------+---------+
	 * | Pageable|  0x50A00000  |   8MB   |
	 * +==================================+
	 */
	base-addr = <0x4DD00000>;
	m3-dump-addr = <0x50000000>;
	etr-addr = <0x50100000>;
	caldb-addr = <0x50200000>;
	pageable-addr = <0x50A00000>;
	hremote-size = <0x2300000>;
	pageable-size = <0x800000>;
	tgt-mem-mode = <0x0>;
	hremote_node = <&qcn9000_pcie0>;
	caldb-size = <0x800000>;
	board_id = <0xa2>;
	status = "ok";
};

&wifi2 {
	/* QCN9000 tgt-mem-mode=0 layout - 53MB
	 * +=========+==============+=========+
	 * |  Region | Start Offset |   Size  |
	 * +---------+--------------+---------+
	 * | HREMOTE |  0x51200000  |   35MB  |
	 * +---------+--------------+---------+
	 * | M3 Dump |  0x53500000  |   1MB   |
	 * +---------+--------------+---------+
	 * |   ETR   |  0x53600000  |   1MB   |
	 * +---------+--------------+---------+
	 * |  Caldb  |  0x53700000  |   8MB   |
	 * +---------+--------------+---------+
	 * | Pageable|  0x53F00000  |   8MB   |
	 * +==================================+
	 */
	base-addr = <0x51200000>;
	m3-dump-addr = <0x53500000>;
	etr-addr = <0x53600000>;
	caldb-addr = <0x53700000>;
	pageable-addr = <0x53F00000>;
	hremote-size = <0x2300000>;
	pageable-size = <0x800000>;
	tgt-mem-mode = <0x0>;
	hremote_node = <&qcn9000_pcie1>;
	caldb-size = <0x800000>;
	board_id = <0xa0>;
	status = "ok";
};

/* Remove unused avm special mac address definitions */
/delete-node/ &avm_mac_addr_macrouter_3;