// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/dts-v1/;

#include "ipq9574-avm-common.dtsi"
#include "ipq9574-wkk-default-memory.dtsi"
#include <dt-bindings/pwm/pwm.h>

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "FRITZ!Box 5690 Pro";

	soc {
		pinctrl@1000000 {
			/* HW-specific pin configuration */
			blsp1_uart4_pins: blsp1_uart4_pinmux {
				pins = "gpio50", "gpio51", "gpio52", "gpio53";
				function = "blsp4_uart";
				drive-strength = <8>;
				bias-disable;
			};

			/* ina2xx pins*/
			i2c_1_pins: i2c-1-pins {
				pins = "gpio36", "gpio37"; /* SCL, SDA */
				function = "blsp1_i2c";
				drive-strength = <8>;
				bias-disable;
			};

			/* RTL UART */
			blsp1_uart0_pins: blsp1_uart0_pinmux {
				pins = "gpio13", "gpio14";
				function = "blsp0_uart";
				drive-strength = <8>;
				bias-disable;
			};

			usb_pw_en_pins: usb_pwr_en_pinmux {
				pins = "gpio12";
				function = "gpio";
				drive-strength = <8>;
				bias-disable;
				output-low;
			};
		};

		avm_mac_addr_maceth_0: dp1 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a001000 0x200>;
			qcom,mactype = <0>;
			qcom,link-poll = <1>;
			devname = "eth0";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <0>;
			phy-mode = "sgmii";
		};

		avm_mac_addr_maceth_1: dp2 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a001200 0x200>;
			qcom,mactype = <0>;
			qcom,link-poll = <1>;
			devname = "eth1";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <1>;
			phy-mode = "sgmii";
		};

		avm_mac_addr_maceth_2: dp3 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <3>;
			reg = <0x3a001400 0x200>;
			qcom,mactype = <0>;
			qcom,link-poll = <1>;
			devname = "eth2";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <2>;
			phy-mode = "sgmii";
		};

		avm_mac_addr_maceth_3: dp4 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <4>;
			reg = <0x3a001600 0x200>;
			qcom,mactype = <0>;
			qcom,link-poll = <1>;
			devname = "eth3";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <3>;
			phy-mode = "sgmii";
		};

		dp5 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <5>;
			reg = <0x3a510000 0x4000>;
			qcom,mactype = <1>;
			mac-address = [1CED6F8C44B7]; /* AVM/TMA: Assigned via JZ-107264 */
			devname = "wanmodem";
			phy-mode = "internal";
			/delete-property/ qcom,link-poll;
			/delete-property/ qcom,phy-mdio-addr;
		};

		avm_mac_addr_maceth_4: dp6 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <6>;
			reg = <0x3a514000 0x4000>;
			qcom,mactype = <0>;
			qcom,link-poll = <1>;
			devname = "wan";
			mac-address = [000000000000];
			qcom,phy-mdio-addr = <28>;
			phy-mode = "sgmii";
		};

		mdio:mdio@90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			status = "ok";
			pinctrl-0 = <&mdio_pins>;
			pinctrl-names = "default";
			phy-reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW
					&tlmm 15 GPIO_ACTIVE_LOW>;

			phy0: ethernet-phy@0 {
				reg = <0>;
			};
			phy1: ethernet-phy@1 {
				reg = <1>;
			};
			phy2: ethernet-phy@2 {
				reg = <2>;
			};
			phy3: ethernet-phy@3 {
				reg = <3>;
			};
			phy5: ethernet-phy@5 {
				reg = <28>;
			};
		};

		ess_switch: ess-instance {
			status = "ok";
			num_devices = <0x1>;
			ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;
				switch_lan_bmp = <0x7e>;
				switch_wan_bmp = <0x00>;
				switch_mac_mode = <0x00>; /* Malibu */
				switch_mac_mode1 = <0x0c>; /* Realtek, 0x0c -> SGMII+, 0x14 -> SGMII */
				switch_mac_mode2 = <0x0c>; /* Nappa */
				bm_tick_mode = <0>;
				tm_tick_mode = <0>;

				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						phy_address = <0>;
					};
					port@1 {
						port_id = <2>;
						phy_address = <1>;
					};
					port@2 {
						port_id = <3>;
						phy_address = <2>;
					};
					port@3 {
						port_id = <4>;
						phy_address = <3>;
					};
					port@4 {
						port_id = <5>;
						forced-speed = <2500>;
						forced-duplex = <1>;
					};
					port@5 {
						port_id = <6>;
						phy_address = <28>;
						port_mac_sel = "QGMAC_PORT";
					};
				};
			};
		};

		nss-macsec1 {
			compatible = "qcom,nss-macsec";
			phy_addr = <0x1c>;
			mdiobus = <&mdio>;
		};

		pcie0_x1: pci@28000000 {
			perst-gpio = <&tlmm 23 1>;
			status = "ok";
			max-payload-size = <1>;
			pcie0_rp {
				#address-cells = <5>;
				#size-cells = <0>;
				reg = <0 0 0 0 0>;

				wifi@0 {
					reg = <0 0 0 0 0>;
					license-file = "qcn9224/license.dat";
					qrtr_node_id = <0x30>;
					memory-region = <0>,<&mhi_region0>;
					qti,disable-rddm-prealloc;
					qti,rddm-seg-len = <0x1000>;
					status = "ok";
				};
			};
		};

		pcie0_phy: phy@84000 {
			status = "ok";
		};

		pcie1_x1: pci@10000000 {
			status = "ok";
		};

		pcie1_phy: phy@fc000 {
			status = "ok";
		};

		pcie2_x2: pci@20000000 {
			perst-gpio = <&tlmm 29 1>;
			status = "ok";
			max-payload-size = <1>;
			pcie2_rp {
				#address-cells = <5>;
				#size-cells = <0>;
				reg = <0 0 0 0 0>;

				wifi@1 {
					reg = <0 0 0 0 0>;
					license-file = "qcn9224/license.dat";
					qrtr_node_id = <0x31>;
					memory-region = <0>,<&mhi_region1>;
					qti,disable-rddm-prealloc;
					qti,rddm-seg-len = <0x1000>;
					status = "ok";
				};
			};
		};

		pcie2_phy: phy@8c000 {
			status = "ok";
		};

		// NVME slot
		pcie3_x2: pci@18000000 {
			perst-gpio = <&tlmm 32 1>;
			status = "disabled";

			pcie3_rp {
				#address-cells = <5>;
				#size-cells = <0>;
				reg = <0 0 0 0 0>;

				qcom,mhi@3 {
					reg = <0 0 0 0 0>;
				};
			};
		};

		pcie3_phy: phy@f4000 {
			status = "disabled";
		};
	};

	avm-usb-en-gpio {
		compatible = "avm,gpio-aggregator";
		pinctrl-0 = <&usb_pw_en_pins>;
		pinctrl-names = "default";

		gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
		gpio-line-names = "usb-pwr-en";
	};

	reserved-memory {
		ramoops@60000000 {
			pmsg-size = <0x20000 0x20000>;
		};
	};
};

&blsp1_uart0 {
	pinctrl-0 = <&blsp1_uart0_pins>;
	pinctrl-names = "default";
	status = "ok";
};

&blsp1_uart4 {
	pinctrl-0 = <&blsp1_uart4_pins>;
	pinctrl-names = "default";
	status = "ok";
};

&edma {
	/delete-property/ qcom,ppeds-num;
	/delete-property/ interrupts;

	qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
	/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
	qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
			<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
	interrupts = <0 367 4>,			/* Tx complete ring id #4 IRQ info */
				   <0 368 4>,			/* Tx complete ring id #5 IRQ info */
				   <0 369 4>,			/* Tx complete ring id #6 IRQ info */
				   <0 370 4>,			/* Tx complete ring id #7 IRQ info */
				   <0 371 4>,			/* Tx complete ring id #8 IRQ info */
				   <0 372 4>,			/* Tx complete ring id #9 IRQ info */
				   <0 373 4>,			/* Tx complete ring id #10 IRQ info */
				   <0 374 4>,			/* Tx complete ring id #11 IRQ info */
				   <0 375 4>,			/* Tx complete ring id #12 IRQ info */
				   <0 376 4>,			/* Tx complete ring id #13 IRQ info */
				   <0 377 4>,			/* Tx complete ring id #14 IRQ info */
				   <0 378 4>,			/* Tx complete ring id #15 IRQ info */
				   <0 379 4>,			/* Tx complete ring id #16 IRQ info */
				   <0 380 4>,			/* Tx complete ring id #17 IRQ info */
				   <0 381 4>,			/* Tx complete ring id #18 IRQ info */
				   <0 382 4>,			/* Tx complete ring id #19 IRQ info */
				   <0 383 4>,			/* Tx complete ring id #20 IRQ info */
				   <0 384 4>,			/* Tx complete ring id #21 IRQ info */
				   <0 509 4>,			/* Tx complete ring id #22 IRQ info */
				   <0 508 4>,			/* Tx complete ring id #23 IRQ info */
				   <0 507 4>,			/* Tx complete ring id #24 IRQ info */
				   <0 506 4>,			/* Tx complete ring id #25 IRQ info */
				   <0 505 4>,			/* Tx complete ring id #26 IRQ info */
				   <0 504 4>,			/* Tx complete ring id #27 IRQ info */
				   <0 503 4>,			/* Tx complete ring id #28 IRQ info */
				   <0 502 4>,			/* Tx complete ring id #29 IRQ info */
				   <0 501 4>,			/* Tx complete ring id #30 IRQ info */
				   <0 500 4>,			/* Tx complete ring id #31 IRQ info */
				   <0 351 4>,			/* Rx desc ring id #20 IRQ info */
				   <0 352 4>,			/* Rx desc ring id #21 IRQ info */
				   <0 353 4>,			/* Rx desc ring id #22 IRQ info */
				   <0 354 4>,			/* Rx desc ring id #23 IRQ info */
				   <0 261 4>,			/* Misc error IRQ info */
				   <0 364 4>,			/* PPEDS Node #0(TxComp ring id #1) TxComplete IRQ info */
				   <0 332 4>,			/* PPEDS Node #0(Rx Desc ring id #1) Rx Desc IRQ info */
				   <0 356 4>,			/* PPEDS Node #0(RxFill Desc ring id #1) Rx Fill IRQ info */
				   <0 365 4>,			/* PPEDS Node #1(TxComp ring id #2) TxComplete IRQ info */
				   <0 333 4>,			/* PPEDS Node #1(Rx Desc ring id #2) Rx Desc IRQ info */
				   <0 357 4>;			/* PPEDS Node #1(RxFill Desc ring id #2) Rx Fill IRQ info */
};

&q6_region {
	status = "ok";
};

&m3_dump {
	status = "ok";
};

&q6_etr_region {
	status = "ok";
};

&q6_caldb_region {
	status = "ok";
};

&wifi0 {
	qcom,board_id = <0x10>;
	status = "ok";
};

&qcn9224_pcie0 {
	status = "ok";
};

&mhi_region0 {
	status = "ok";
	size = <0x0 0x00f00000>;
};

&qcn9224_pcie1 {
	status = "ok";
};

&mhi_region1 {
	status = "ok";
	size = <0x0 0x00f00000>;
};

&mlo_global_mem0 {
	size = <0x0 0xD00000>;
	status = "ok";
};

&wifi4 {
	hremote_node = <&qcn9224_pcie0>;
	board_id = <0x0002>;
	status = "ok";
};

&wifi5 {
	hremote_node = <&qcn9224_pcie1>;
	board_id = <0x000c>;
	status = "ok";
};

&i2c_1 {
	pinctrl-0 = <&i2c_1_pins>;
	pinctrl-names = "default";
	status = "ok";

	ina236@40 {
		compatible = "ti,ina236";
		reg = <0x40>;
		shunt-resistor = <15000>;
		alert-type = <12>; /* bus undervoltage */
		alert-limit = <10800>; /* 10,8V */
	};
};