// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ5332 DB-MI03.1 board device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 */

/dts-v1/;

#include "ipq5332.dtsi"
#include "ipq5332-memory.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ5332/DB-MI03.1";
	compatible = "qcom,ipq5332-db-mi03.1", "qcom,ipq5332";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &blsp1_uart0;
		ethernet0 = "/soc/dp1";
		ethernet1 = "/soc/dp2";
	};

	chosen {
		stdout-path = "serial0";
		bootargs-append = " clk_ignore_unused";
	};

	soc {
		pinctrl@1000000 {
			spi_0_pins: spi0-pinmux {
				spi_clock {
					pins = "gpio14";
					function = "blsp0_spi";
					drive-strength = <8>;
					bias-pull-up;
				};

				spi_mosi {
					pins = "gpio15";
					function = "blsp0_spi";
					drive-strength = <8>;
					bias-pull-up;
				};

				spi_miso {
					pins = "gpio16";
					function = "blsp0_spi";
					drive-strength = <8>;
					bias-pull-up;
				};

				spi_cs {
					pins = "gpio17";
					function = "blsp0_spi";
					drive-strength = <8>;
					bias-pull-up;
				};
			};

			serial_0_pins: serial0-pinmux {
				pins = "gpio18", "gpio19";
				function = "blsp0_uart0";
				drive-strength = <8>;
				bias-pull-up;
			};

			leds_pins: leds_pinmux {
				led0_2g {
					pins = "gpio36";
					function = "gpio";
					drive-strength = <8>;
					bias-pull-down;
				};
			};

			mdio1_pins: mdio_pinmux {
				mux_0 {
					pins = "gpio27";
					function = "mdc1";
					drive-strength = <8>;
					bias-pull-up;
				};
				mux_1 {
					pins = "gpio28";
					function = "mdio1";
					drive-strength = <8>;
					bias-pull-up;
				};
			};
		};

		mdio:mdio@90000 {
			status = "ok";
			pinctrl-0 = <&mdio1_pins>;
			pinctrl-names = "default";
			/*gpio22 and gpio24 for aqr reset*/
			//phy-reset-gpio = <&tlmm 22 0 &tlmm 24 0>;

			phy0: ethernet-phy@0 {
				reg = <8>;
				compatible ="ethernet-phy-ieee802.3-c45";
			};
			phy1: ethernet-phy@1 {
				reg = <0>;
				compatible ="ethernet-phy-ieee802.3-c45";
			};
		};

		ess-instance {
			ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0x2>; /* lan port bitmap */
				switch_wan_bmp = <0x4>; /* wan port bitmap */
				switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/
				switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						phy_address = <8>;
						ethernet-phy-ieee802.3-c45;
					};
					port@1 {
						port_id = <2>;
						phy_address = <0>;
						ethernet-phy-ieee802.3-c45;
					};
				};
			};
		};

		serial@78af000 {
			pinctrl-0 = <&serial_0_pins>;
			pinctrl-names = "default";
			status = "ok";
		};

		spi@78b5000 {
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			cs-select = <0>;
			status = "ok";

			m25p80@0 {
				compatible = "n25q128a11";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				spi-max-frequency = <50000000>;
			};
		};

		dma@7984000 {
			status = "ok";
		};

		nand: nand@79b0000 {
			pinctrl-0 = <&qspi_nand_pins>;
			pinctrl-names = "default";
			status = "ok";
		};

		usb3@8A00000 {
			status = "ok";
			qcom,select-utmi-as-pipe-clk;
			dwc_0: dwc3@8A00000 {
				/delete-property/ #phy-cells;
				/delete-property/ phys;
				/delete-property/ phy-names;
			};
		};

		hs_m31phy_0: hs_m31phy@7b000 {
			status = "ok";
		};

		leds {
			compatible = "gpio-leds";
			pinctrl-0 = <&leds_pins>;
			pinctrl-names = "default";
			led@36 {
				label = "led0_2g";
				gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
				linux,default-trigger = "led_2g";
				default-state = "off";
			};
		};

		pcie0_phy: phy@4b0000 {
			status = "ok";
		};

		pcie1_phy_x2: phy_x2@4b1000 {
			status = "ok";
		};

		pcie1: pcie@18000000 {
			status = "ok";
			pcie1_rp {
				reg = <0 0 0 0 0>;

				qcom,mhi@1 {
					reg = <0 0 0 0 0>;
				};
			};
		};

		pcie0: pcie@20000000 {
			status = "ok";
			pcie0_rp {
				reg = <0 0 0 0 0>;

				qcom,mhi@2 {
					reg = <0 0 0 0 0>;
				};
			};
		};

		q6v5_wcss: remoteproc@d100000 {

			memory-region = <&q6_region>;
		};

		/delete-node/ tmc@4048000;
		/delete-node/ replicator@4046000;
		/delete-node/ etf@4047000;
		/delete-node/ funnel@4045000;
		/delete-node/ funnel@4041000;
		/delete-node/ funnel@4042000;
		/delete-node/ stm@4002000;
		/delete-node/ funnel@50a1000;
		/delete-node/ etm@509c000;
		/delete-node/ etm@509d000;
		/delete-node/ etm@509e000;
		/delete-node/ etm@509f000;

		dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a504000 0x4000>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
			qcom,phy-mdio-addr = <0>;
			qcom,link-poll = <1>;
			phy-mode = "sgmii";
		};

		dp2 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a500000 0x4000>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
			qcom,phy-mdio-addr = <8>;
			qcom,link-poll = <1>;
			phy-mode = "sgmii";
			qcom,ppe-offload-disabled = <1>;
		};

		/* EDMA host driver configuration for the board */
		edma@3ab00000 {
			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
					  <12 13 14 15>,	/* Port1 per-core Tx ring map */
					  <4 5 6 7>;		/* used only for packets from  vp*/
			qcom,txdesc-fc-grp-map = <1 2>;		/* Per GMAC flow control group map */
			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
			qcom,rx-queue-start = <0>;		/* Rx queue start */
			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
				   <0 191 4>,			/* Misc error IRQ info */
				   <0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
				   <0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
				   <0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
				   <0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
				   <0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
				   <0 153 4>;			/* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
		};
	};
};