// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ5332 AP-MI01.6 board device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
 */

/dts-v1/;

#include "ipq5332.dtsi"

#ifdef __IPQ_MEM_PROFILE_512_MB__
#include "ipq5332-512MB-memory.dtsi"
#else
#include "ipq5332-default-memory.dtsi"
#endif

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ5332/AP-MI01.6";
	compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &blsp1_uart0;
		ethernet0 = "/soc/dp1";
		ethernet1 = "/soc/dp2";
	};

	chosen {
		stdout-path = "serial0";
	};

	soc {
		pinctrl@1000000 {
			spi_0_pins: spi0-pinmux {
				spi_clock {
					pins = "gpio14";
					function = "blsp0_spi";
					drive-strength = <2>;
					bias-pull-down;
				};

				spi_mosi {
					pins = "gpio15";
					function = "blsp0_spi";
					drive-strength = <2>;
					bias-pull-down;
				};

				spi_miso {
					pins = "gpio16";
					function = "blsp0_spi";
					drive-strength = <2>;
					bias-pull-down;
				};

				spi_cs {
					pins = "gpio17";
					function = "blsp0_spi";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			serial_0_pins: serial0-pinmux {
				pins = "gpio18", "gpio19";
				function = "blsp0_uart0";
				drive-strength = <8>;
				bias-pull-up;
			};

			serial_1_pins: serial1-pinmux {
				pins = "gpio33", "gpio34", "gpio35", "gpio36";
				function = "blsp1_uart2";
				drive-strength = <8>;
				bias-pull-up;
			};

			i2c_1_pins: i2c-1-pinmux {
				pins = "gpio29", "gpio30";
				function = "blsp1_i2c0";
				drive-strength = <8>;
				bias-pull-up;
			};

			leds_pins: leds_pinmux {
				led0_2g {
					pins = "gpio36";
					function = "gpio";
					drive-strength = <8>;
					bias-pull-down;
				};
			};

			mdio0_pins: mdio0_pinmux {
				mux_0 {
					pins = "gpio25";
					function = "mdc0";
					drive-strength = <2>;
					bias-pull-up;
				};
				mux_1 {
					pins = "gpio26";
					function = "mdio0";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			mdio1_pins: mdio1_pinmux {
				mux_0 {
					pins = "gpio27";
					function = "mdc1";
					drive-strength = <8>;
					bias-disable;
				};
				mux_1 {
					pins = "gpio28";
					function = "mdio1";
					drive-strength = <8>;
					bias-pull-up;
				};
			};

			audio_pins_pri: audio_pinmux_pri {
				mux_1 {
					pins = "gpio29";
					function = "audio_pri";
					drive-strength = <8>;
					bias-pull-down;
				};

				mux_2 {
					pins = "gpio30";
					function = "audio_pri";
					drive-strength = <8>;
					bias-pull-down;
				};

				mux_3 {
					pins = "gpio31";
					function = "audio_pri";
					drive-strength = <4>;
					bias-pull-down;
				};

				mux_4 {
					pins = "gpio32";
					function = "audio_pri";
					drive-strength = <4>;
					bias-pull-down;
				};
			};

			spi_2_pins: spi-2-pins {
				pins = "gpio33", "gpio34", "gpio35", "gpio36";
				function = "blsp2_spi0";
				drive-strength = <8>;
				bias-pull-down;
			};
		};

		dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a504000 0x4000>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
			mdio-bus = <&mdio>;
			qcom,phy-mdio-addr = <4>;
			qcom,link-poll = <1>;
			phy-mode = "sgmii";
		};

		dp2 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a500000 0x4000>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
			phy-mode = "sgmii";
			qcom,ppe-offload-disabled = <1>;
			qcom,is_switch_connected = <1>;
			qcom,mht-dev = <1>;
		};

		mdio:mdio@90000 {
			status = "ok";
			pinctrl-0 = <&mdio1_pins &mdio0_pins>;
			pinctrl-names = "default";
			/*gpio51 for manhattan reset*/
			phy-reset-gpio = <&tlmm 51 0>;
			phyaddr_fixup = <0xC90F018>;
			uniphyaddr_fixup = <0xC90F014>;
			mdio_clk_fixup; /* MDIO clock sequence fix up flag */

			phy0: ethernet-phy@0 {
				reg = <1>;
				fixup;
			};
			phy1: ethernet-phy@1 {
				reg = <2>;
				fixup;
			};
			phy2: ethernet-phy@2 {
				reg = <3>;
				fixup;
			};
			phy3: ethernet-phy@3 {
				reg = <4>;
				fixup;
			};
		};


		pcm: pcm@0xA3C0000{
			pinctrl-0 = <&audio_pins_pri>;
			pinctrl-names = "primary";
			status = "disabled";
		};

		ess-instance {
			num_devices = <0x2>;
			ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0x2>; /* lan port bitmap */
				switch_wan_bmp = <0x4>; /* wan port bitmap */
				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/
				switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/

				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						forced-speed = <2500>;
						forced-duplex = <1>;
					};
					port@1 {
						port_id = <2>;
						phy_address = <4>;
					};
				};

				led_source@5 {
					source = <5>;
					mode = "normal";
					speed = "all";
					blink_en = "enable";
					active = "high";
				};
			};

			ess-switch1@1 {
				compatible = "qcom,ess-switch-qca8386";
				device_id = <1>;
				switch_access_mode = "mdio";
				mdio-bus = <&mdio>;
				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0 */
				switch_mac_mode1 = <0xff>; /* mac mode1 for uniphy instance1 */
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0xe>; /* lan port bitmap */
				switch_wan_bmp = <0x0>;  /* wan port bitmap */
				link-polling-required = <0>;
				fdb_sync = "interrupt";
				link-intr-gpio = <&tlmm 23 0>;
				qcom,port_phyinfo {
					port@0 {
						port_id = <0>;
						forced-speed = <2500>;
						forced-duplex = <1>;
					};
					port@1 {
						port_id = <1>;
						phy_address = <1>;
					};
					port@2 {
						port_id = <2>;
						phy_address = <2>;
					};
					port@3 {
						port_id = <3>;
						phy_address = <3>;
					};
				};

				led_source@2 {
					source = <2>;
					mode = "normal";
					speed = "all";
					blink_en = "enable";
					active = "high";
				};
				led_source@5 {
					source = <5>;
					mode = "normal";
					speed = "all";
					blink_en = "enable";
					active = "high";
				};
				led_source@8 {
					source = <8>;
					mode = "normal";
					speed = "all";
					blink_en = "enable";
					active = "high";
                                };
			};
		};

		/* EDMA host driver configuration for the board */
		edma@3ab00000 {
			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
			qcom,mht-txdesc-rings = <8>;            /* Extra Tx desc rings to be provisioned for MHT SW ports. */
			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
			qcom,mht-txcmpl-rings = <8>;            /* Extra Tx complete rings to be provisioned for mht sw ports. */
			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
					  <12 13 14 15>,	/* MHT-Port1 per-core Tx ring map */
					  <4 5 6 7>,            /* MHT-Port2 per-core Tx ring map/packets from  vp*/
					  <16 17 18 19>,        /* MHT-Port3 per-core Tx ring map */
					  <20 21 22 23>;        /* MHT-Port4 per-core Tx ring map */
			qcom,txdesc-fc-grp-map = <1 2 3 4 5>;   /* Per GMAC flow control group map */
			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
			qcom,rx-queue-start = <0>;		/* Rx queue start */
			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
				   <0 191 4>,			/* Misc error IRQ info */
				<0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
				<0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
				<0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
				<0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
				<0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
				<0 153 4>,			/* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
				   <0 175 4>,			/* MHT port Tx complete ring id #16 IRQ info */
				   <0 176 4>,			/* MHT port Tx complete ring id #17 IRQ info */
				   <0 177 4>,			/* MHT port Tx complete ring id #18 IRQ info */
				   <0 178 4>,			/* MHT port Tx complete ring id #19 IRQ info */
				   <0 179 4>,			/* MHT port Tx complete ring id #20 IRQ info */
				   <0 180 4>,			/* MHT port Tx complete ring id #21 IRQ info */
				   <0 181 4>,			/* MHT port Tx complete ring id #22 IRQ info */
				   <0 182 4>;			/* MHT port Tx complete ring id #23 IRQ info */
		};

		serial@78af000 {
			pinctrl-0 = <&serial_0_pins>;
			pinctrl-names = "default";
			status = "ok";
		};

		serial@78b0000 {
			pinctrl-0 = <&serial_1_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

		spi@78b5000 {
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			cs-select = <0>;
			status = "ok";

			m25p80@0 {
				compatible = "n25q128a11";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				spi-max-frequency = <50000000>;
			};
		};

		spi_2: spi@78b7000 {
			pinctrl-0 = <&spi_2_pins>;
			pinctrl-names = "default";
			cs-select = <0>;
			status = "disabled";
		};

		i2c_1: i2c@78b6000 {
			pinctrl-0 = <&i2c_1_pins>;
			pinctrl-names = "default";
		};

		dma@7984000 {
			status = "ok";
		};

		nand: nand@79b0000 {
			pinctrl-0 = <&qspi_nand_pins>;
			pinctrl-names = "default";
			status = "ok";
		};

		usb3@8A00000 {
			status = "ok";
			qcom,multiplexed-phy;
		};

		ssuniphy_0: ssuniphy@4b0000 {
			status = "ok";
		};

		hs_m31phy_0: hs_m31phy@7b000 {
			status = "ok";
		};

		leds {
			compatible = "gpio-leds";
			pinctrl-0 = <&leds_pins>;
			pinctrl-names = "default";
			led@36 {
				label = "led0_2g";
				gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
				linux,default-trigger = "led_2g";
				default-state = "off";
			};
		};

		pcie1_phy_x2: phy_x2@4b1000 {
			status = "ok";
		};

		wsi: wsi {
			id = <0>;
			num_chip = <2>;
		};

		pcie1: pcie@18000000 {
			status = "ok";
			pcie1_rp {
				reg = <0 0 0 0 0>;

				qcom,mhi@1 {
					reg = <0 0 0 0 0>;
					qti,disable-rddm-prealloc;
					qti,rddm-seg-len = <0x1000>;
#if defined(__CNSS2__)
					qrtr_node_id = <0x31>;
					memory-region = <0>, <&mhi_region1>;
#else
					memory-region = <&qcn9224_pcie1>;
					qcom,board_id = <0x1019>;
					qcom,wsi = <&wsi>;
#endif
				};
			};
		};
	};
};

&wifi0 {
	qcom,rproc = <&q6_wcss_pd1>;
	qcom,rproc_rpd = <&q6v5_wcss>;
	qcom,multipd_arch;
	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
#if defined(__CNSS2__)
	mem-region = <&q6_region>;
#else
	memory-region = <&q6_region>;
	qcom,wsi = <&wsi>;
#endif
	qcom,board_id = <0x16>;
	status = "ok";
};

&mhi_region1 {
	status = "ok";
};

&qcn9224_pcie1 {
	status = "ok";
};

/* QCN9224 5G+6G */
&wifi2 {
	hremote_node = <&qcn9224_pcie1>;
	board_id = <0x1019>;
	status = "ok";
};