// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
 */
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK14";
	compatible = "qcom,ipq8074-ap-hk14", "qcom,ipq8074";
	qcom,msm-id = <0x157 0x0>, <0x187 0x0>;
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &blsp1_uart5;
		/* Aliases as required by u-boot to patch MAC addresses */
		ethernet0 = "/soc/dp1";
		ethernet1 = "/soc/dp2";
		ethernet2 = "/soc/dp3";
		ethernet3 = "/soc/dp4";
		ethernet4 = "/soc/dp5";
	};

	chosen {
		stdout-path = "serial0";
	};

	reserved-memory {
/* No Pine attach in 256M profile */
#if !defined(__IPQ_MEM_PROFILE_256_MB__)
#ifdef __IPQ_MEM_PROFILE_512_MB__
	/*                      512 MB Profile
	 * +========+==============+=========================+
	 * | Region | Start Offset |          Size           |
	 * +--------+--------------+-------------------------+
	 * |  NSS   |  0x40000000  |          16MB           |
	 * +--------+--------------+-------------------------+
	 * | Linux  |  0x41000000  | Depends on total memory |
	 * +--------+--------------+-------------------------+
	 * | TZ APP |  0x4A400000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | uboot  |  0x4A600000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |  SBL   |  0x4AA00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  smem  |  0x4AB00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |   TZ   |  0x4AC00000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |   Q6   |  0x4B000000  |          55MB           |
	 * +--------+--------------+-------------------------+
	 * |  QDSS  |  0x4E700000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | M3 Dump|  0x4E800000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  Pine  |  0x4E900000  |          26MB           |
	 * +--------+--------------+-------------------------+
	 * |  MHI0  |  0x50300000  |          9MB            |
	 * +--------+--------------+-------------------------+
	 * |                                                 |
	 * |      Rest of the memory for Linux               |
	 * |                                                 |
	 * +=================================================+
	 */
		qcn9000_pcie0: qcn9000_pcie0@4e900000 {
			no-map;
			reg = <0x0 0x4e900000 0x0 0x01A00000>;
		};

#if defined(__CNSS2__)
		mhi_region0: dma_pool0@50300000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x50300000 0x0 0x00900000>;
		};
#endif
#else
	/*                   Default Profile
	 * +========+==============+=========================+
	 * | Region | Start Offset |          Size           |
	 * +--------+--------------+-------------------------+
	 * |  NSS   |  0x40000000  |          16MB           |
	 * +--------+--------------+-------------------------+
	 * | Linux  |  0x41000000  | Depends on total memory |
	 * +--------+--------------+-------------------------+
	 * | TZ APP |  0x4A400000  |           2MB           |
	 * +--------+--------------+-------------------------+
	 * | uboot  |  0x4A600000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |  SBL   |  0x4AA00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  smem  |  0x4AB00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |   TZ   |  0x4AC00000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |   Q6   |  0x4B000000  |          95MB           |
	 * +--------+--------------+-------------------------+
	 * |  QDSS  |  0x50F00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | M3 Dump|  0x51000000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  Pine0 |  0x51100000  |          53MB           |
	 * +--------+--------------+-------------------------+
	 * |  MHI0  |  0x54600000  |           9MB           |
	 * +--------+--------------+-------------------------+
	 * |                                                 |
	 * |          Rest of the memory for Linux           |
	 * |                                                 |
	 * +=================================================+
	 */
		qcn9000_pcie0: qcn9000_pcie0@51100000 {
			no-map;
			reg = <0x0 0x51100000 0x0 0x03500000>;
		};

#if defined(__CNSS2__)
		mhi_region0: dma_pool0@54600000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x54600000 0x0 0x00900000>;
		};
#endif
#endif
#endif
	};

	soc {
		pinctrl@1000000 {
			button_pins: button_pins {
				wps_button {
					pins = "gpio34";
					function = "gpio";
					drive-strength = <8>;
					bias-pull-up;
				};
			};

			pcie0_pins: pcie_pins {
				pcie0_rst {
					pins = "gpio58";
					function = "pcie0_rst";
					drive-strength = <8>;
					bias-pull-down;
				};
				pcie0_wake {
					pins = "gpio59";
					function = "pcie0_wake";
					drive-strength = <8>;
					bias-pull-down;
				};
			};

			mdio_pins: mdio_pinmux {
				mux_0 {
					pins = "gpio68";
					function = "mdc";
					drive-strength = <8>;
					bias-pull-up;
				};
				mux_1 {
					pins = "gpio69";
					function = "mdio";
					drive-strength = <8>;
					bias-pull-up;
				};
				mux_2 {
					pins = "gpio44";
					function = "gpio";
					bias-pull-up;
				};
			};

			uniphy_pins: uniphy_pinmux {
				mux {
					pins = "gpio60";
					function = "rx2";
					bias-disable;
				};
			};

			led_pins: led_pins {
				led_2g {
					pins = "gpio42";
					function = "gpio";
					drive-strength = <8>;
					bias-pull-down;
				};

				led_5g {
					pins = "gpio43";
					function = "gpio";
					drive-strength = <8>;
					bias-pull-down;
				};
			};
		};

		serial@78b3000 {
			status = "ok";
		};

		spi@78b5000 {
			status = "ok";
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			cs-select = <0>;

			m25p80@0 {
				  compatible = "n25q128a11";
				  #address-cells = <1>;
				  #size-cells = <1>;
				  reg = <0>;
				  spi-max-frequency = <50000000>;
			};
		};

		dma@7984000 {
			 status = "ok";
		};

		nand@79b0000 {
			status = "ok";

			nand@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <1>;

				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				nand-bus-width = <8>;
			};
		};

		qusb@79000 {
			status = "ok";
		};

		ssphy@78000 {
			status = "ok";
		};

		usb3@8A00000 {
			status = "ok";
		};

		qcom,test@0 {
			status = "ok";
		};

		phy@84000 {
			status = "ok";
		};

		phy@86000 {
			status = "ok";
		};

		pci@20000000 {
			perst-gpio = <&tlmm 58 1>;
			status = "ok";

			pcie0_rp: pcie0_rp {
				reg = <0 0 0 0 0>;
			};
		};

		phy@8e000 {
			status = "ok";
		};

		pci@10000000 {
			perst-gpio = <&tlmm 61 0x1>;
			status = "ok";
		};

		mdio@90000 {
			pinctrl-0 = <&mdio_pins>;
			pinctrl-names = "default";
			phy-reset-gpio = <&tlmm 37 0>;
			phy0: ethernet-phy@0 {
				reg = <0>;
			};
			phy1: ethernet-phy@1 {
				reg = <1>;
			};
			phy2: ethernet-phy@2 {
				reg = <2>;
			};
			phy3: ethernet-phy@3 {
				reg = <3>;
			};
			phy4: ethernet-phy@4 {
				reg = <4>;
			};
			phy5: ethernet-phy@5 {
				compatible ="ethernet-phy-ieee802.3-c45";
				reg = <7>;
			};
		};

		ess-switch@3a000000 {
			pinctrl-0 = <&uniphy_pins>;
			pinctrl-names = "default";
			switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
			switch_lan_bmp = <0x1e>; /* lan port bitmap */
			switch_wan_bmp = <0x40>; /* wan port bitmap */
			switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
			switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
			switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
			bm_tick_mode = <0>; /* bm tick mode */
			tm_tick_mode = <0>; /* tm tick mode */
			qcom,port_phyinfo {
				port@0 {
					port_id = <1>;
					phy_address = <0>;
				};
				port@1 {
					port_id = <2>;
					phy_address = <1>;
				};
				port@2 {
					port_id = <3>;
					phy_address = <2>;
				};
				port@3 {
					port_id = <4>;
					phy_address = <3>;
				};
				port@4 {
					port_id = <6>;
					phy_address = <7>;
					ethernet-phy-ieee802.3-c45;
				};
			};
			port_scheduler_resource {
				port@0 {
					port_id = <0>;
					ucast_queue = <0 143>;
					mcast_queue = <256 271>;
					l0sp = <0 35>;
					l0cdrr = <0 47>;
					l0edrr = <0 47>;
					l1cdrr = <0 7>;
					l1edrr = <0 7>;
				};
				port@1 {
					port_id = <1>;
					ucast_queue = <144 159>;
					mcast_queue = <272 275>;
					l0sp = <36 39>;
					l0cdrr = <48 63>;
					l0edrr = <48 63>;
					l1cdrr = <8 11>;
					l1edrr = <8 11>;
				};
				port@2 {
					port_id = <2>;
					ucast_queue = <160 175>;
					mcast_queue = <276 279>;
					l0sp = <40 43>;
					l0cdrr = <64 79>;
					l0edrr = <64 79>;
					l1cdrr = <12 15>;
					l1edrr = <12 15>;
				};
				port@3 {
					port_id = <3>;
					ucast_queue = <176 191>;
					mcast_queue = <280 283>;
					l0sp = <44 47>;
					l0cdrr = <80 95>;
					l0edrr = <80 95>;
					l1cdrr = <16 19>;
					l1edrr = <16 19>;
				};
				port@4 {
					port_id = <4>;
					ucast_queue = <192 207>;
					mcast_queue = <284 287>;
					l0sp = <48 51>;
					l0cdrr = <96 111>;
					l0edrr = <96 111>;
					l1cdrr = <20 23>;
					l1edrr = <20 23>;
				};
				port@5 {
					port_id = <5>;
					ucast_queue = <208 223>;
					mcast_queue = <288 291>;
					l0sp = <52 55>;
					l0cdrr = <112 127>;
					l0edrr = <112 127>;
					l1cdrr = <24 27>;
					l1edrr = <24 27>;
				};
				port@6 {
					port_id = <6>;
					ucast_queue = <224 239>;
					mcast_queue = <292 295>;
					l0sp = <56 59>;
					l0cdrr = <128 143>;
					l0edrr = <128 143>;
					l1cdrr = <28 31>;
					l1edrr = <28 31>;
				};
				port@7 {
					port_id = <7>;
					ucast_queue = <240 255>;
					mcast_queue = <296 299>;
					l0sp = <60 63>;
					l0cdrr = <144 159>;
					l0edrr = <144 159>;
					l1cdrr = <32 35>;
					l1edrr = <32 35>;
				};
			};
			port_scheduler_config {
				port@0 {
					port_id = <0>;
					l1scheduler {
						group@0 {
							sp = <0 1>; /*L0 SPs*/
							/*cpri cdrr epri edrr*/
							cfg = <0 0 0 0>;
						};
					};
					l0scheduler {
						group@0 {
							/*unicast queues*/
							ucast_queue = <0 4 8>;
							/*multicast queues*/
							mcast_queue = <256 260>;
							/*sp cpri cdrr epri edrr*/
							cfg = <0 0 0 0 0>;
						};
						group@1 {
							ucast_queue = <1 5 9>;
							mcast_queue = <257 261>;
							cfg = <0 1 1 1 1>;
						};
						group@2 {
							ucast_queue = <2 6 10>;
							mcast_queue = <258 262>;
							cfg = <0 2 2 2 2>;
						};
						group@3 {
							ucast_queue = <3 7 11>;
							mcast_queue = <259 263>;
							cfg = <0 3 3 3 3>;
						};
					};
				};
				port@1 {
					port_id = <1>;
					l1scheduler {
						group@0 {
							sp = <36>;
							cfg = <0 8 0 8>;
						};
						group@1 {
							sp = <37>;
							cfg = <1 9 1 9>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <144>;
							ucast_loop_pri = <16>;
							mcast_queue = <272>;
							mcast_loop_pri = <4>;
							cfg = <36 0 48 0 48>;
						};
					};
				};
				port@2 {
					port_id = <2>;
					l1scheduler {
						group@0 {
							sp = <40>;
							cfg = <0 12 0 12>;
						};
						group@1 {
							sp = <41>;
							cfg = <1 13 1 13>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <160>;
							ucast_loop_pri = <16>;
							mcast_queue = <276>;
							mcast_loop_pri = <4>;
							cfg = <40 0 64 0 64>;
						};
					};
				};
				port@3 {
					port_id = <3>;
					l1scheduler {
						group@0 {
							sp = <44>;
							cfg = <0 16 0 16>;
						};
						group@1 {
							sp = <45>;
							cfg = <1 17 1 17>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <176>;
							ucast_loop_pri = <16>;
							mcast_queue = <280>;
							mcast_loop_pri = <4>;
							cfg = <44 0 80 0 80>;
						};
					};
				};
				port@4 {
					port_id = <4>;
					l1scheduler {
						group@0 {
							sp = <48>;
							cfg = <0 20 0 20>;
						};
						group@1 {
							sp = <49>;
							cfg = <1 21 1 21>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <192>;
							ucast_loop_pri = <16>;
							mcast_queue = <284>;
							mcast_loop_pri = <4>;
							cfg = <48 0 96 0 96>;
						};
					};
				};
				port@5 {
					port_id = <5>;
					l1scheduler {
						group@0 {
							sp = <52>;
							cfg = <0 24 0 24>;
						};
						group@1 {
							sp = <53>;
							cfg = <1 25 1 25>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <208>;
							ucast_loop_pri = <16>;
							mcast_queue = <288>;
							mcast_loop_pri = <4>;
							cfg = <52 0 112 0 112>;
						};
					};
				};
				port@6 {
					port_id = <6>;
					l1scheduler {
						group@0 {
							sp = <56>;
							cfg = <0 28 0 28>;
						};
						group@1 {
							sp = <57>;
							cfg = <1 29 1 29>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <224>;
							ucast_loop_pri = <16>;
							mcast_queue = <292>;
							mcast_loop_pri = <4>;
							cfg = <56 0 128 0 128>;
						};
					};
				};
				port@7 {
					port_id = <7>;
					l1scheduler {
						group@0 {
							sp = <60>;
							cfg = <0 32 0 32>;
						};
						group@1 {
							sp = <61>;
							cfg = <1 33 1 33>;
						};
					};
					l0scheduler {
						group@0 {
							ucast_queue = <240>;
							ucast_loop_pri = <16>;
							mcast_queue = <296>;
							cfg = <60 0 144 0 144>;
						};
					};
				};
			};
		};
		gpio_keys {
			compatible = "gpio-keys";
			pinctrl-0 = <&button_pins>;
			pinctrl-names = "default";
			status = "ok";

			button@1 {
				label = "wps";
				linux,code = <KEY_WPS_BUTTON>;
				gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
				linux,input-type = <1>;
				debounce-interval = <60>;
			};
		};

		leds {
			compatible = "gpio-leds";
			pinctrl-0 = <&led_pins>;
			pinctrl-names = "default";

			led_2g {
				label = "led_2g";
				gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};

			led_5g {
				label = "led_5g";
				gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};
		};

		dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a001000 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
			qcom,link-poll = <1>;
			qcom,phy-mdio-addr = <0>;
			phy-mode = "sgmii";
		};

		dp2 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a001200 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
			qcom,link-poll = <1>;
			qcom,phy-mdio-addr = <1>;
			phy-mode = "sgmii";
		};

		dp3 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <3>;
			reg = <0x3a001400 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
			qcom,link-poll = <1>;
			qcom,phy-mdio-addr = <2>;
			phy-mode = "sgmii";
		};

		dp4 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <4>;
			reg = <0x3a001600 0x200>;
			qcom,mactype = <0>;
			local-mac-address = [000000000000];
			qcom,link-poll = <1>;
			qcom,phy-mdio-addr = <3>;
			phy-mode = "sgmii";
		};

		dp5 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <6>;
			reg = <0x3a007000 0x3fff>;
			qcom,mactype = <1>;
			local-mac-address = [000000000000];
			qcom,link-poll = <1>;
			qcom,phy-mdio-addr = <7>;
			phy-mode = "sgmii";
		};
	};
};

&npu_cpr {
	status = "disabled";
};

&nss0 {
	npu-supply = <&dummy_reg>;
	mx-supply = <&dummy_reg>;
};

#ifndef __IPQ_MEM_PROFILE_256_MB__
&nss1 {
	npu-supply = <&dummy_reg>;
	mx-supply = <&dummy_reg>;
};
#endif

&wifi0 {
	status = "disabled";
};

&wifi1 {
	qcom,board_id = <0x294>;
	status = "ok";
};

#if !defined(__IPQ_MEM_PROFILE_256_MB__)
&wifi2 {
#ifdef __IPQ_MEM_PROFILE_512_MB__
      /* QCN9000 tgt-mem-mode=1 layout - 26MB
       * +=========+==============+=========+
       * |  Region | Start Offset |   Size  |
       * +---------+--------------+---------+
       * | HREMOTE |  0x4E900000  |   12MB  |
       * +---------+--------------+---------+
       * | M3 Dump |  0x4F500000  |   1MB   |
       * +---------+--------------+---------+
       * |   ETR   |  0x4F600000  |   1MB   |
       * +---------+--------------+---------+
       * |  Caldb  |  0x4F700000  |   8MB   |
       * +---------+--------------+---------+
       * | Pageable|  0x4FF00000  |   4MB   |
       * +==================================+
       */
	base-addr = <0x4E900000>;
	m3-dump-addr = <0x4F500000>;
	etr-addr = <0x4F600000>;
	caldb-addr = <0x4F700000>;
	pageable-addr = <0x4FF00000>;
	hremote-size = <0xC00000>;
	tgt-mem-mode = <0x1>;
	pageable-size = <0x400000>;
#else
      /* QCN9000 tgt-mem-mode=0 layout - 45MB
       * +=========+==============+=========+
       * |  Region | Start Offset |   Size  |
       * +---------+--------------+---------+
       * | HREMOTE |  0x51100000  |   35MB  |
       * +---------+--------------+---------+
       * | M3 DUMP |  0x53400000  |   1MB   |
       * +---------+--------------+---------+
       * |   ETR   |  0x53500000  |   1MB   |
       * +---------+--------------+---------+
       * |  Caldb  |  0x53600000  |   8MB   |
       * +---------+--------------+---------+
       * | Pageable|  0x53E00000  |   8MB   |
       * +==================================+
       */
	base-addr = <0x51100000>;
	m3-dump-addr = <0x53400000>;
	etr-addr = <0x53500000>;
	caldb-addr = <0x53600000>;
	pageable-addr = <0x53E00000>;
	hremote-size = <0x2300000>;
	tgt-mem-mode = <0x0>;
	pageable-size = <0x800000>;
#endif
	caldb-size = <0x800000>;
	hremote_node = <&qcn9000_pcie0>;
	board_id = <0xa4>;
	status = "ok";
};
#endif

&wifi3 {
	status = "disabled";
};

&pcie0_rp {
	status = "ok";

#if defined(__CNSS2__)
	mhi_0: qcom,mhi@0 {
		reg = <0 0 0 0 0 >;
		qrtr_instance_id = <0x20>;
		#address-cells = <0x2>;
		#size-cells = <0x2>;
#if !defined(__IPQ_MEM_PROFILE_256_MB__)
		memory-region = <0>,<&mhi_region0>;
#endif
	};
#else
	mhi_0: wifi@0 {
		reg = <0 0 0 0 0 >;
		qrtr_instance_id = <0x20>;
		qcom,board_id= <0xa4>;
		memory-region = <&qcn9000_pcie0>;

		pcie0_mhi: pcie0_mhi {
			status = "ok";
		};
	};
#endif
};