/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_RESET_QCOM_NSS_CC_IPQ5332_H
#define _DT_BINDINGS_RESET_QCOM_NSS_CC_IPQ5332_H

#define NSS_CC_CE_APB_CLK_ARES					0
#define NSS_CC_CE_AXI_CLK_ARES					1
#define NSS_CC_DEBUG_CLK_ARES					2
#define NSS_CC_EIP_CLK_ARES					3
#define NSS_CC_NSS_CSR_CLK_ARES					4
#define NSS_CC_NSSNOC_CE_APB_CLK_ARES				5
#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES				6
#define NSS_CC_NSSNOC_EIP_CLK_ARES				7
#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES				8
#define NSS_CC_NSSNOC_PPE_CLK_ARES				9
#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES				10
#define NSS_CC_PORT1_MAC_CLK_ARES				11
#define NSS_CC_PORT1_RX_CLK_ARES				12
#define NSS_CC_PORT1_TX_CLK_ARES				13
#define NSS_CC_PORT2_MAC_CLK_ARES				14
#define NSS_CC_PORT2_RX_CLK_ARES				15
#define NSS_CC_PORT2_TX_CLK_ARES				16
#define NSS_CC_PPE_BCR						17
#define NSS_CC_PPE_EDMA_CLK_ARES				18
#define NSS_CC_PPE_EDMA_CFG_CLK_ARES				19
#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES				20
#define NSS_CC_PPE_SWITCH_CLK_ARES				21
#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES				22
#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES				23
#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES				24
#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES				25
#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES				26
#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES				27
#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES				28
#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES				29

#endif