/*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ #ifndef _mcbsp_h_ #define _mcbsp_h_ /* * Copyright 2002 by Texas Instruments Incorporated. * All rights reserved. Property of Texas Instruments Incorporated. * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ /* "@(#) DSP/BIOS 4.61.12 05-31-02 (barracuda-j21)" */ /******************************************************************************\ * Copyright (C) 1999-2001 Texas Instruments Incorporated. * All Rights Reserved *------------------------------------------------------------------------------ * FILENAME...... csl_mcbsphal.h * DATE CREATED.. 06/12/1999 * LAST MODIFIED. 10/02/2001 * - 6713 device addition *------------------------------------------------------------------------------ * REGISTERS * * DRR0 - serial port 0 data receive register * DRR1 - serial port 1 data receive register * DRR2 - serial port 2 data receive register (1) * DXR0 - serial port 0 data transmit register * DXR1 - serial port 1 data transmit register * DXR2 - serial port 2 data transmit register (1) * SPCR0 - serial port 0 control register * SPCR1 - serial port 1 control register * SPCR2 - serial port 2 control register (1) * RCR0 - serial port 0 receive control register * RCR1 - serial port 1 receive control register * RCR2 - serial port 2 receive control register (1) * XCR0 - serial port 0 transmit control register * XCR1 - serial port 1 transmit control register * XCR2 - serial port 2 transmit control register (1) * SRGR0 - serial port 0 sample rate generator register * SRGR1 - serial port 1 sample rate generator register * SRGR2 - serial port 2 sample rate generator register (1) * MCR0 - serial port 0 multichannel control register * MCR1 - serial port 1 multichannel control register * MCR2 - serial port 2 multichannel control register (1) * RCER0 - serial port 0 receive channel enable register * RCER1 - serial port 1 receive channel enable register * RCER2 - serial port 2 receive channel enable register (1) * XCER0 - serial port 0 transmit channel enable register * XCER1 - serial port 1 transmit channel enable register * XCER2 - serial port 2 transmit channel enable register (1) * RCERE00 - serial port 0 Enhanced receive channel enable register 0 (2) * RCERE01 - serial port 1 Enhanced receive channel enable register 0 (2) * RCERE02 - serial port 2 Enhanced receive channel enable register 0 (2) * RCERE10 - serial port 0 Enhanced receive channel enable register 1 (2) * RCERE11 - serial port 1 Enhanced receive channel enable register 1 (2) * RCERE12 - serial port 2 Enhanced receive channel enable register 1 (2) * RCERE20 - serial port 0 Enhanced receive channel enable register 2 (2) * RCERE21 - serial port 1 Enhanced receive channel enable register 2 (2) * RCERE22 - serial port 2 Enhanced receive channel enable register 2 (2) * RCERE30 - serial port 0 Enhanced receive channel enable register 3 (2) * RCERE31 - serial port 1 Enhanced receive channel enable register 3 (2) * RCERE32 - serial port 2 Enhanced receive channel enable register 3 (2) * XCERE00 - serial port 0 Enhanced transmit channel enable register 0 (2) * XCERE01 - serial port 1 Enhanced transmit channel enable register 0 (2) * XCERE02 - serial port 2 Enhanced transmit channel enable register 0 (2) * XCERE10 - serial port 0 Enhanced transmit channel enable register 1 (2) * XCERE11 - serial port 1 Enhanced transmit channel enable register 1 (2) * XCERE12 - serial port 2 Enhanced transmit channel enable register 1 (2) * XCERE20 - serial port 0 Enhanced transmit channel enable register 2 (2) * XCERE21 - serial port 1 Enhanced transmit channel enable register 2 (2) * XCERE22 - serial port 2 Enhanced transmit channel enable register 2 (2) * XCERE30 - serial port 0 Enhanced transmit channel enable register 3 (2) * XCERE31 - serial port 1 Enhanced transmit channel enable register 3 (2) * XCERE32 - serial port 2 Enhanced transmit channel enable register 3 (2) * PCR0 - serial port 0 pin control register * PCR1 - serial port 1 pin control register * PCR2 - serial port 2 pin control register (1) * * (1) only supported on devices with three serial ports * (2) supported by C64x devices except 6412 (RCERx replaced by RCERE0x, XCERx replaced by by XCERE0x) * \******************************************************************************/ /******************************************************************************\ * MISC section \******************************************************************************/ #define _MCBSP_PORT_CNT 2 #define _MCBSP_BASE_PORT0 0x018C0000u #define _MCBSP_BASE_PORT1 0x01900000u /******************************************************************************\ * _____________________ * | | * | D R R | * |___________________| * * DRR0 - serial port 0 data receive register * DRR1 - serial port 1 data receive register * DRR2 - serial port 2 data receive register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (r) DR * \******************************************************************************/ #define _MCBSP_DRR_OFFSET 0 #define _MCBSP_DRR0_ADDR 0x018C0000u #define _MCBSP_DRR1_ADDR 0x01900000u /******************************************************************************\ * _____________________ * | | * | D X R | * |___________________| * * DXR0 - serial port 0 data transmit register * DXR1 - serial port 1 data transmit register * DXR2 - serial port 2 data transmit register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (w) DX * \******************************************************************************/ #define _MCBSP_DXR_OFFSET 1 #define _MCBSP_DXR0_ADDR 0x018C0004u #define _MCBSP_DXR1_ADDR 0x01900004u /******************************************************************************\ * _____________________ * | | * | S P C R | * |___________________| * * SPCR0 - serial port 0 control register * SPCR1 - serial port 1 control register * SPCR2 - serial port 2 control register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) FREE (2) * (rw) SOFT (2) * (rw) FRST * (rw) GRST * (rw) XINTM * (rw) XSYNCERR * (r) XEMPTY * (r) XRDY * (rw) XRST * (rw) DLB * (rw) RJUST * (rw) CLKSTP * (rw) DXENA (2) * (rw) RINTM * (rw) RSYNCERR * (r) RFULL * (r) RRDY * (rw) RRST * * (2) - C11_SUPPORT/C64_SUPPORT/C6713 only * \******************************************************************************/ #define _MCBSP_SPCR_OFFSET 2 #define _MCBSP_SPCR0_ADDR 0x018C0008u #define _MCBSP_SPCR1_ADDR 0x01900008u #define _MCBSP_SPCR_FRST_MASK 0x00800000u #define _MCBSP_SPCR_FRST_SHIFT 0x00000017u #define MCBSP_SPCR_FRST_YES 0x00000000u #define MCBSP_SPCR_FRST_0 0x00000000u #define MCBSP_SPCR_FRST_NO 0x00000001u #define MCBSP_SPCR_FRST_1 0x00000001u #define _MCBSP_SPCR_GRST_MASK 0x00400000u #define _MCBSP_SPCR_GRST_SHIFT 0x00000016u #define MCBSP_SPCR_GRST_YES 0x00000000u #define MCBSP_SPCR_GRST_0 0x00000000u #define MCBSP_SPCR_GRST_NO 0x00000001u #define MCBSP_SPCR_GRST_1 0x00000001u #define _MCBSP_SPCR_XINTM_MASK 0x00300000u #define _MCBSP_SPCR_XINTM_SHIFT 0x00000014u #define MCBSP_SPCR_XINTM_XRDY 0x00000000u #define MCBSP_SPCR_XINTM_EOS 0x00000001u #define MCBSP_SPCR_XINTM_FRM 0x00000002u #define MCBSP_SPCR_XINTM_XSYNCERR 0x00000003u #define _MCBSP_SPCR_XSYNCERR_MASK 0x00080000u #define _MCBSP_SPCR_XSYNCERR_SHIFT 0x00000013u #define MCBSP_SPCR_XSYNCERR_NO 0x00000000u #define MCBSP_SPCR_XSYNCERR_0 0x00000000u #define MCBSP_SPCR_XSYNCERR_YES 0x00000001u #define MCBSP_SPCR_XSYNCERR_1 0x00000001u #define _MCBSP_SPCR_XEMPTY_MASK 0x00040000u #define _MCBSP_SPCR_XEMPTY_SHIFT 0x00000012u #define MCBSP_SPCR_XEMPTY_YES 0x00000000u #define MCBSP_SPCR_XEMPTY_0 0x00000000u #define MCBSP_SPCR_XEMPTY_NO 0x00000001u #define MCBSP_SPCR_XEMPTY_1 0x00000001u #define _MCBSP_SPCR_XRDY_MASK 0x00020000u #define _MCBSP_SPCR_XRDY_SHIFT 0x00000011u #define MCBSP_SPCR_XRDY_NO 0x00000000u #define MCBSP_SPCR_XRDY_YES 0x00000001u #define _MCBSP_SPCR_XRST_MASK 0x00010000u #define _MCBSP_SPCR_XRST_SHIFT 0x00000010u #define MCBSP_SPCR_XRST_YES 0x00000000u #define MCBSP_SPCR_XRST_0 0x00000000u #define MCBSP_SPCR_XRST_NO 0x00000001u #define MCBSP_SPCR_XRST_1 0x00000001u #define _MCBSP_SPCR_DLB_MASK 0x00008000u #define _MCBSP_SPCR_DLB_SHIFT 0x0000000Fu #define MCBSP_SPCR_DLB_OFF 0x00000000u #define MCBSP_SPCR_DLB_ON 0x00000001u #define _MCBSP_SPCR_RJUST_MASK 0x00006000u #define _MCBSP_SPCR_RJUST_SHIFT 0x0000000Du #define MCBSP_SPCR_RJUST_RZF 0x00000000u #define MCBSP_SPCR_RJUST_RSE 0x00000001u #define MCBSP_SPCR_RJUST_LZF 0x00000002u #define _MCBSP_SPCR_CLKSTP_MASK 0x00001800u #define _MCBSP_SPCR_CLKSTP_SHIFT 0x0000000Bu #define MCBSP_SPCR_CLKSTP_DISABLE 0x00000000u #define MCBSP_SPCR_CLKSTP_NODELAY 0x00000002u #define MCBSP_SPCR_CLKSTP_DELAY 0x00000003u #define _MCBSP_SPCR_RINTM_MASK 0x00000030u #define _MCBSP_SPCR_RINTM_SHIFT 0x00000004u #define MCBSP_SPCR_RINTM_RRDY 0x00000000u #define MCBSP_SPCR_RINTM_EOS 0x00000001u #define MCBSP_SPCR_RINTM_FRM 0x00000002u #define MCBSP_SPCR_RINTM_RSYNCERR 0x00000003u #define _MCBSP_SPCR_RSYNCERR_MASK 0x00000008u #define _MCBSP_SPCR_RSYNCERR_SHIFT 0x00000003u #define MCBSP_SPCR_RSYNCERR_NO 0x00000000u #define MCBSP_SPCR_RSYNCERR_0 0x00000000u #define MCBSP_SPCR_RSYNCERR_YES 0x00000001u #define MCBSP_SPCR_RSYNCERR_1 0x00000001u #define _MCBSP_SPCR_RFULL_MASK 0x00000004u #define _MCBSP_SPCR_RFULL_SHIFT 0x00000002u #define MCBSP_SPCR_RFULL_NO 0x00000000u #define MCBSP_SPCR_RFULL_YES 0x00000001u #define _MCBSP_SPCR_RRDY_MASK 0x00000002u #define _MCBSP_SPCR_RRDY_SHIFT 0x00000001u #define MCBSP_SPCR_RRDY_NO 0x00000000u #define MCBSP_SPCR_RRDY_YES 0x00000001u #define _MCBSP_SPCR_RRST_MASK 0x00000001u #define _MCBSP_SPCR_RRST_SHIFT 0x00000000u #define MCBSP_SPCR_RRST_YES 0x00000000u #define MCBSP_SPCR_RRST_0 0x00000000u #define MCBSP_SPCR_RRST_NO 0x00000001u #define MCBSP_SPCR_RRST_1 0x00000001u /******************************************************************************\ * _____________________ * | | * | R C R | * |___________________| * * RCR0 - serial port 0 receive control register * RCR1 - serial port 1 receive control register * RCR2 - serial port 2 receive control register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) RPHASE * (rw) RFRLEN2 * (rw) RWDLEN2 * (rw) RCOMPAND * (rw) RFIG * (rw) RDATDLY * (rw) RFRLEN1 * (rw) RWDLEN1 * (rw) RWDREVRS (2) * * (2) - C11_SUPPORT / C64_SUPPORT/ C6713 only * \******************************************************************************/ #define _MCBSP_RCR_OFFSET 3 #define _MCBSP_RCR0_ADDR 0x018C000Cu #define _MCBSP_RCR1_ADDR 0x0190000Cu #define _MCBSP_RCR_RPHASE_MASK 0x80000000u #define _MCBSP_RCR_RPHASE_SHIFT 0x0000001Fu #define MCBSP_RCR_RPHASE_SINGLE 0x00000000u #define MCBSP_RCR_RPHASE_DUAL 0x00000001u #define _MCBSP_RCR_RFRLEN2_MASK 0x7F000000u #define _MCBSP_RCR_RFRLEN2_SHIFT 0x00000018u #define _MCBSP_RCR_RWDLEN2_MASK 0x00E00000u #define _MCBSP_RCR_RWDLEN2_SHIFT 0x00000015u #define MCBSP_RCR_RWDLEN2_8BIT 0x00000000u #define MCBSP_RCR_RWDLEN2_12BIT 0x00000001u #define MCBSP_RCR_RWDLEN2_16BIT 0x00000002u #define MCBSP_RCR_RWDLEN2_20BIT 0x00000003u #define MCBSP_RCR_RWDLEN2_24BIT 0x00000004u #define MCBSP_RCR_RWDLEN2_32BIT 0x00000005u #define _MCBSP_RCR_RCOMPAND_MASK 0x00180000u #define _MCBSP_RCR_RCOMPAND_SHIFT 0x00000013u #define MCBSP_RCR_RCOMPAND_MSB 0x00000000u #define MCBSP_RCR_RCOMPAND_8BITLSB 0x00000001u #define MCBSP_RCR_RCOMPAND_ULAW 0x00000002u #define MCBSP_RCR_RCOMPAND_ALAW 0x00000003u #define _MCBSP_RCR_RFIG_MASK 0x00040000u #define _MCBSP_RCR_RFIG_SHIFT 0x00000012u #define MCBSP_RCR_RFIG_NO 0x00000000u #define MCBSP_RCR_RFIG_YES 0x00000001u #define _MCBSP_RCR_RDATDLY_MASK 0x00030000u #define _MCBSP_RCR_RDATDLY_SHIFT 0x00000010u #define MCBSP_RCR_RDATDLY_0BIT 0x00000000u #define MCBSP_RCR_RDATDLY_1BIT 0x00000001u #define MCBSP_RCR_RDATDLY_2BIT 0x00000002u #define _MCBSP_RCR_RFRLEN1_MASK 0x00007F00u #define _MCBSP_RCR_RFRLEN1_SHIFT 0x00000008u #define _MCBSP_RCR_RWDLEN1_MASK 0x000000E0u #define _MCBSP_RCR_RWDLEN1_SHIFT 0x00000005u #define MCBSP_RCR_RWDLEN1_8BIT 0x00000000u #define MCBSP_RCR_RWDLEN1_12BIT 0x00000001u #define MCBSP_RCR_RWDLEN1_16BIT 0x00000002u #define MCBSP_RCR_RWDLEN1_20BIT 0x00000003u #define MCBSP_RCR_RWDLEN1_24BIT 0x00000004u #define MCBSP_RCR_RWDLEN1_32BIT 0x00000005u /******************************************************************************\ * _____________________ * | | * | X C R | * |___________________| * * XCR0 - serial port 0 transmit control register * XCR1 - serial port 1 transmit control register * XCR2 - serial port 2 transmit control register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) XPHASE * (rw) XFRLEN2 * (rw) XWDLEN2 * (rw) XCOMPAND * (rw) XFIG * (rw) XDATDLY * (rw) XFRLEN1 * (rw) XWDLEN1 * (rw) XWDREVRS (2) * * (2) - C11_SUPPORT /C64_SUPPORT/C6713 only * \******************************************************************************/ #define _MCBSP_XCR_OFFSET 4 #define _MCBSP_XCR0_ADDR 0x01840010u #define _MCBSP_XCR1_ADDR 0x01900010u #define _MCBSP_XCR_XPHASE_MASK 0x80000000u #define _MCBSP_XCR_XPHASE_SHIFT 0x0000001Fu #define MCBSP_XCR_XPHASE_SINGLE 0x00000000u #define MCBSP_XCR_XPHASE_DUAL 0x00000001u #define _MCBSP_XCR_XFRLEN2_MASK 0x7F000000u #define _MCBSP_XCR_XFRLEN2_SHIFT 0x00000018u #define _MCBSP_XCR_XWDLEN2_MASK 0x00E00000u #define _MCBSP_XCR_XWDLEN2_SHIFT 0x00000015u #define MCBSP_XCR_XWDLEN2_8BIT 0x00000000u #define MCBSP_XCR_XWDLEN2_12BIT 0x00000001u #define MCBSP_XCR_XWDLEN2_16BIT 0x00000002u #define MCBSP_XCR_XWDLEN2_20BIT 0x00000003u #define MCBSP_XCR_XWDLEN2_24BIT 0x00000004u #define MCBSP_XCR_XWDLEN2_32BIT 0x00000005u #define _MCBSP_XCR_XCOMPAND_MASK 0x00180000u #define _MCBSP_XCR_XCOMPAND_SHIFT 0x00000013u #define MCBSP_XCR_XCOMPAND_MSB 0x00000000u #define MCBSP_XCR_XCOMPAND_8BITLSB 0x00000001u #define MCBSP_XCR_XCOMPAND_ULAW 0x00000002u #define MCBSP_XCR_XCOMPAND_ALAW 0x00000003u #define _MCBSP_XCR_XFIG_MASK 0x00040000u #define _MCBSP_XCR_XFIG_SHIFT 0x00000012u #define MCBSP_XCR_XFIG_NO 0x00000000u #define MCBSP_XCR_XFIG_YES 0x00000001u #define _MCBSP_XCR_XDATDLY_MASK 0x00030000u #define _MCBSP_XCR_XDATDLY_SHIFT 0x00000010u #define MCBSP_XCR_XDATDLY_0BIT 0x00000000u #define MCBSP_XCR_XDATDLY_1BIT 0x00000001u #define MCBSP_XCR_XDATDLY_2BIT 0x00000002u #define _MCBSP_XCR_XFRLEN1_MASK 0x00007F00u #define _MCBSP_XCR_XFRLEN1_SHIFT 0x00000008u #define _MCBSP_XCR_XWDLEN1_MASK 0x000000E0u #define _MCBSP_XCR_XWDLEN1_SHIFT 0x00000005u #define MCBSP_XCR_XWDLEN1_8BIT 0x00000000u #define MCBSP_XCR_XWDLEN1_12BIT 0x00000001u #define MCBSP_XCR_XWDLEN1_16BIT 0x00000002u #define MCBSP_XCR_XWDLEN1_20BIT 0x00000003u #define MCBSP_XCR_XWDLEN1_24BIT 0x00000004u #define MCBSP_XCR_XWDLEN1_32BIT 0x00000005u /******************************************************************************\ * _____________________ * | | * | S R G R | * |___________________| * * SRGR0 - serial port 0 sample rate generator register * SRGR1 - serial port 1 sample rate generator register * SRGR2 - serial port 2 sample rate generator register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) GSYNC * (rw) CLKSP * (rw) CLKSM * (rw) FSGM * (rw) FPER * (rw) FWID * (rw) CLKGDV * \******************************************************************************/ #define _MCBSP_SRGR_OFFSET 5 #define _MCBSP_SRGR0_ADDR 0x018C0014u #define _MCBSP_SRGR1_ADDR 0x01900014u #define _MCBSP_SRGR_GSYNC_MASK 0x80000000u #define _MCBSP_SRGR_GSYNC_SHIFT 0x0000001Fu #define MCBSP_SRGR_GSYNC_FREE 0x00000000u #define MCBSP_SRGR_GSYNC_SYNC 0x00000001u #define _MCBSP_SRGR_CLKSP_MASK 0x40000000u #define _MCBSP_SRGR_CLKSP_SHIFT 0x0000001Eu #define MCBSP_SRGR_CLKSP_RISING 0x00000000u #define MCBSP_SRGR_CLKSP_FALLING 0x00000001u #define _MCBSP_SRGR_CLKSM_MASK 0x20000000u #define _MCBSP_SRGR_CLKSM_SHIFT 0x0000001Du #define MCBSP_SRGR_CLKSM_CLKS 0x00000000u #define MCBSP_SRGR_CLKSM_INTERNAL 0x00000001u #define _MCBSP_SRGR_FSGM_MASK 0x10000000u #define _MCBSP_SRGR_FSGM_SHIFT 0x0000001Cu #define MCBSP_SRGR_FSGM_DXR2XSR 0x00000000u #define MCBSP_SRGR_FSGM_FSG 0x00000001u #define _MCBSP_SRGR_FPER_MASK 0x0FFF0000u #define _MCBSP_SRGR_FPER_SHIFT 0x00000010u #define _MCBSP_SRGR_FWID_MASK 0x0000FF00u #define _MCBSP_SRGR_FWID_SHIFT 0x00000008u #define _MCBSP_SRGR_CLKGDV_MASK 0x000000FFu #define _MCBSP_SRGR_CLKGDV_SHIFT 0x00000000u /******************************************************************************\ * _____________________ * | | * | M C R | * |___________________| * * MCR0 - serial port 0 multichannel control register * MCR1 - serial port 1 multichannel control register * MCR2 - serial port 2 multichannel control register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) XMCME (1) * (rw) XPBBLK * (rw) XPABLK * (r) XCBLK * (rw) XMCM * (rw) RMCME (1) * (rw) RPBBLK * (rw) RPABLK * (r) RCBLK * (rw) RMCM * * (1) C64_SUPPORT only \******************************************************************************/ #define _MCBSP_MCR_OFFSET 6 #define _MCBSP_MCR0_ADDR 0x018C0018u #define _MCBSP_MCR1_ADDR 0x01900018u #define _MCBSP_MCR_XPBBLK_MASK 0x01800000u #define _MCBSP_MCR_XPBBLK_SHIFT 0x00000017u #define MCBSP_MCR_XPBBLK_SF1 0x00000000u #define MCBSP_MCR_XPBBLK_SF3 0x00000001u #define MCBSP_MCR_XPBBLK_SF5 0x00000002u #define MCBSP_MCR_XPBBLK_SF7 0x00000003u #define _MCBSP_MCR_XPABLK_MASK 0x00600000u #define _MCBSP_MCR_XPABLK_SHIFT 0x00000015u #define MCBSP_MCR_XPABLK_SF0 0x00000000u #define MCBSP_MCR_XPABLK_SF2 0x00000001u #define MCBSP_MCR_XPABLK_SF4 0x00000002u #define MCBSP_MCR_XPABLK_SF6 0x00000003u #define _MCBSP_MCR_XCBLK_MASK 0x001C0000u #define _MCBSP_MCR_XCBLK_SHIFT 0x00000012u #define MCBSP_MCR_XCBLK_SF0 0x00000000u #define MCBSP_MCR_XCBLK_SF1 0x00000001u #define MCBSP_MCR_XCBLK_SF2 0x00000002u #define MCBSP_MCR_XCBLK_SF3 0x00000003u #define MCBSP_MCR_XCBLK_SF4 0x00000004u #define MCBSP_MCR_XCBLK_SF5 0x00000005u #define MCBSP_MCR_XCBLK_SF6 0x00000006u #define MCBSP_MCR_XCBLK_SF7 0x00000007u #define _MCBSP_MCR_XMCM_MASK 0x00030000u #define _MCBSP_MCR_XMCM_SHIFT 0x00000010u #define MCBSP_MCR_XMCM_ENNOMASK 0x00000000u #define MCBSP_MCR_XMCM_DISXP 0x00000001u #define MCBSP_MCR_XMCM_ENMASK 0x00000002u #define MCBSP_MCR_XMCM_DISRP 0x00000003u #define _MCBSP_MCR_RPBBLK_MASK 0x00000180u #define _MCBSP_MCR_RPBBLK_SHIFT 0x00000007u #define MCBSP_MCR_RPBBLK_SF1 0x00000000u #define MCBSP_MCR_RPBBLK_SF3 0x00000001u #define MCBSP_MCR_RPBBLK_SF5 0x00000002u #define MCBSP_MCR_RPBBLK_SF7 0x00000003u #define _MCBSP_MCR_RPABLK_MASK 0x00000060u #define _MCBSP_MCR_RPABLK_SHIFT 0x00000005u #define MCBSP_MCR_RPABLK_SF0 0x00000000u #define MCBSP_MCR_RPABLK_SF2 0x00000001u #define MCBSP_MCR_RPABLK_SF4 0x00000002u #define MCBSP_MCR_RPABLK_SF6 0x00000003u #define _MCBSP_MCR_RCBLK_MASK 0x0000001Cu #define _MCBSP_MCR_RCBLK_SHIFT 0x00000002u #define MCBSP_MCR_RCBLK_SF0 0x00000000u #define MCBSP_MCR_RCBLK_SF1 0x00000001u #define MCBSP_MCR_RCBLK_SF2 0x00000002u #define MCBSP_MCR_RCBLK_SF3 0x00000003u #define MCBSP_MCR_RCBLK_SF4 0x00000004u #define MCBSP_MCR_RCBLK_SF5 0x00000005u #define MCBSP_MCR_RCBLK_SF6 0x00000006u #define MCBSP_MCR_RCBLK_SF7 0x00000007u #define _MCBSP_MCR_RMCM_MASK 0x00000001u #define _MCBSP_MCR_RMCM_SHIFT 0x00000000u #define MCBSP_MCR_RMCM_CHENABLE 0x00000000u #define MCBSP_MCR_RMCM_ELDISABLE 0x00000001u /******************************************************************************\ * _____________________ * | | * | R C E R | * |___________________| * * RCER0 - serial port 0 receive channel enable register * RCER1 - serial port 1 receive channel enable register * RCER2 - serial port 2 receive channel enable register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) RCEB * (rw) RCEA * \******************************************************************************/ #define _MCBSP_RCER_OFFSET 7 #define _MCBSP_RCER0_ADDR 0x018C001Cu #define _MCBSP_RCER1_ADDR 0x0190001Cu #define _MCBSP_RCER_RCEB_MASK 0xFFFF0000u #define _MCBSP_RCER_RCEB_SHIFT 0x00000010u #define _MCBSP_RCER_RCEA_MASK 0x0000FFFFu #define _MCBSP_RCER_RCEA_SHIFT 0x00000000u /******************************************************************************\ * _____________________ * | | * | X C E R | * |___________________| * * XCER0 - serial port 0 transmit channel enable register * XCER1 - serial port 1 transmit channel enable register * XCER2 - serial port 2 transmit channel enable register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) XCEB * (rw) XCEA * \******************************************************************************/ #define _MCBSP_XCER_OFFSET 8 #define _MCBSP_XCER0_ADDR 0x018C0020u #define _MCBSP_XCER1_ADDR 0x01900020u #define _MCBSP_XCER_XCEB_MASK 0xFFFF0000u #define _MCBSP_XCER_XCEB_SHIFT 0x00000010u #define _MCBSP_XCER_XCEA_MASK 0x0000FFFFu #define _MCBSP_XCER_XCEA_SHIFT 0x00000000u /******************************************************************************\ * _____________________ * | | * | P C R | * |___________________| * * PCR0 - serial port 0 pin control register * PCR1 - serial port 1 pin control register * PCR2 - serial port 2 pin control register (1) * * (1) only supported on devices with three serial ports * * FIELDS (msb -> lsb) * (rw) XIOEN * (rw) RIOEN * (rw) FSXM * (rw) FSRM * (rw) CLKXM * (rw) CLKRM * (rw) CLKSSTAT * (rw) DXSTAT * (r) DRSTAT * (rw) FSXP * (rw) FSRP * (rw) CLKXP * (rw) CLKRP * \******************************************************************************/ #define _MCBSP_PCR_OFFSET 9 #define _MCBSP_PCR0_ADDR 0x018C0024u #define _MCBSP_PCR1_ADDR 0x01900024u #define _MCBSP_PCR_XIOEN_MASK 0x00002000u #define _MCBSP_PCR_XIOEN_SHIFT 0x0000000Du #define MCBSP_PCR_XIOEN_SP 0x00000000u #define MCBSP_PCR_XIOEN_GPIO 0x00000001u #define _MCBSP_PCR_RIOEN_MASK 0x00001000u #define _MCBSP_PCR_RIOEN_SHIFT 0x0000000Cu #define MCBSP_PCR_RIOEN_SP 0x00000000u #define MCBSP_PCR_RIOEN_GPIO 0x00000001u #define _MCBSP_PCR_FSXM_MASK 0x00000800u #define _MCBSP_PCR_FSXM_SHIFT 0x0000000Bu #define MCBSP_PCR_FSXM_EXTERNAL 0x00000000u #define MCBSP_PCR_FSXM_INTERNAL 0x00000001u #define _MCBSP_PCR_FSRM_MASK 0x00000400u #define _MCBSP_PCR_FSRM_SHIFT 0x0000000Au #define MCBSP_PCR_FSRM_EXTERNAL 0x00000000u #define MCBSP_PCR_FSRM_INTERNAL 0x00000001u #define _MCBSP_PCR_CLKXM_MASK 0x00000200u #define _MCBSP_PCR_CLKXM_SHIFT 0x00000009u #define MCBSP_PCR_CLKXM_INPUT 0x00000000u #define MCBSP_PCR_CLKXM_OUTPUT 0x00000001u #define _MCBSP_PCR_CLKRM_MASK 0x00000100u #define _MCBSP_PCR_CLKRM_SHIFT 0x00000008u #define MCBSP_PCR_CLKRM_INPUT 0x00000000u #define MCBSP_PCR_CLKRM_OUTPUT 0x00000001u #define _MCBSP_PCR_CLKSSTAT_MASK 0x00000040u #define _MCBSP_PCR_CLKSSTAT_SHIFT 0x00000006u #define MCBSP_PCR_CLKSSTAT_0 0x00000000u #define MCBSP_PCR_CLKSSTAT_1 0x00000001u #define _MCBSP_PCR_DXSTAT_MASK 0x00000020u #define _MCBSP_PCR_DXSTAT_SHIFT 0x00000005u #define MCBSP_PCR_DXSTAT_0 0x00000000u #define MCBSP_PCR_DXSTAT_1 0x00000001u #define _MCBSP_PCR_DRSTAT_MASK 0x00000010u #define _MCBSP_PCR_DRSTAT_SHIFT 0x00000004u #define MCBSP_PCR_DRSTAT_0 0x00000000u #define MCBSP_PCR_DRSTAT_1 0x00000001u #define _MCBSP_PCR_FSXP_MASK 0x00000008u #define _MCBSP_PCR_FSXP_SHIFT 0x00000003u #define MCBSP_PCR_FSXP_ACTIVEHIGH 0x00000000u #define MCBSP_PCR_FSXP_ACTIVELOW 0x00000001u #define _MCBSP_PCR_FSRP_MASK 0x00000004u #define _MCBSP_PCR_FSRP_SHIFT 0x00000002u #define MCBSP_PCR_FSRP_ACTIVEHIGH 0x00000000u #define MCBSP_PCR_FSRP_ACTIVELOW 0x00000001u #define _MCBSP_PCR_CLKXP_MASK 0x00000002u #define _MCBSP_PCR_CLKXP_SHIFT 0x00000001u #define MCBSP_PCR_CLKXP_RISING 0x00000000u #define MCBSP_PCR_CLKXP_FALLING 0x00000001u #define _MCBSP_PCR_CLKRP_MASK 0x00000001u #define _MCBSP_PCR_CLKRP_SHIFT 0x00000000u #define MCBSP_PCR_CLKRP_FALLING 0x00000000u #define MCBSP_PCR_CLKRP_RISING 0x00000001u /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ union _McBSP_SPCR { volatile unsigned int Register; struct __McBSP_SPCR { unsigned int _RRST : 1; /*--- 0 ---*/ unsigned int RRDY : 1; /*--- 1 ---*/ unsigned int RFULL : 1; /*--- 2 ---*/ unsigned int RSYNCERR : 1; /*--- 3 ---*/ unsigned int RINTM : 2; /*--- 4,5 ---*/ unsigned int Reserved0 : 1; /*--- 6 ---*/ unsigned int DXENA : 1; /*--- 7 ---*/ unsigned int Reserved1 : 3; /*--- 8,9,10 ---*/ unsigned int CLKSTP : 2; /*--- 11,12 ---*/ unsigned int RJUST : 2; /*--- 13,14---*/ unsigned int DLB : 1; /*--- 15 ---*/ unsigned int _XRST : 1; /*--- 16 ---*/ unsigned int XRDY : 1; /*--- 17 ---*/ unsigned int _XEMPTY : 1; /*--- 18 ---*/ unsigned int XSYNCERR : 1; /*--- 19 ---*/ unsigned int XINTM : 2; /*--- 20,21 ---*/ unsigned int _GRST : 1; /*--- 22 ---*/ unsigned int _FRST : 1; /*--- 23 ---*/ unsigned int SOFT : 1; /*--- 24 ---*/ unsigned int FREE : 1; /*--- 25 ---*/ unsigned int Reserved2 : 6; /*--- 26,27,28,29,30,31 ---*/ } Bits; }; union _McBSP_PCR { volatile unsigned int Register; struct __McBSP_PCR { /*--- PIN Control ---*/ unsigned int CLKRP : 1; /*--- 0 ---*/ unsigned int CLKXP : 1; /*--- 1 ---*/ unsigned int FSRP : 1; /*--- 2 ---*/ unsigned int FSXP : 1; /*--- 3 ---*/ unsigned int DR_STAT : 1; /*--- 4 ---*/ unsigned int DX_STAT : 1; /*--- 5 ---*/ unsigned int CLKS_STAT : 1; /*--- 6 ---*/ unsigned int Reserved0 : 1; /*--- 7 ---*/ unsigned int CLKRM : 1; /*--- 8 ---*/ unsigned int CLKXM : 1; /*--- 9 ---*/ unsigned int FSRM : 1; /*--- 10 ---*/ unsigned int FSXM : 1; /*--- 11 ---*/ unsigned int RIOEN : 1; /*--- 12 ---*/ unsigned int XIOEN : 1; /*--- 13 ---*/ unsigned int Reserved1 : 18; /*--- 14-31 ---*/ } Bits; }; /*-------------------------------------------------------------------------------------*\ enum _XRWDLEN { Len_8Bit = MCBSP_RCR_RWDLEN1_8BIT, Len_12Bit = MCBSP_RCR_RWDLEN1_12BIT, Len_16Bit = MCBSP_RCR_RWDLEN1_16BIT, Len_20Bit = MCBSP_RCR_RWDLEN1_20BIT, Len_24Bit = MCBSP_RCR_RWDLEN1_24BIT, Len_32Bit = MCBSP_RCR_RWDLEN1_32BIT }; \*-------------------------------------------------------------------------------------*/ union _McBSP_RCR { volatile unsigned int Register; struct __McBSP_RCR { unsigned int Reserved0 : 4; unsigned int RWDREVRS : 1; unsigned int RWDLEN1 : 3; unsigned int RFRLEN1 : 7; unsigned int Reserved1 : 1; /*--- 15 --*/ unsigned int RDATDLY : 2; unsigned int RFIG : 1; unsigned int RCOMPAND : 2; unsigned int RWDLEN2 : 3; unsigned int RFRLEN2 : 7; unsigned int RPHASE : 1; } Bits; }; union _McBSP_XCR { volatile unsigned int Register; struct __McBSP_XCR { unsigned int Reserved0 : 4; /*--- 0,1,2,3 ---*/ unsigned int XWDREVRS : 1; /*--- 4 ---*/ unsigned int XWDLEN1 : 3; /*--- 5- 7 ---*/ unsigned int XFRLEN1 : 7; /*--- 8-14 ---*/ unsigned int Reserved1 : 1; /*--- 15 --*/ unsigned int XDATDLY : 2; /*--- 16-17 ---*/ unsigned int XFIG : 1; /*--- 18 ---*/ unsigned int XCOMPAND : 2; /*--- 19-20 ---*/ unsigned int XWDLEN2 : 3; /*--- 21-23 ---*/ unsigned int XFRLEN2 : 7; /*--- 24-30 ---*/ unsigned int XPHASE : 1; /*--- 31 ---*/ } Bits; }; union _McBSP_MCR { volatile unsigned int Register; struct __McBSP_MCR { unsigned int RMCM : 1; /*--- 0 ---*/ unsigned int RCBLK : 3; /*--- 2,3,4 ---*/ unsigned int RPABLK : 2; /*--- 5,6 ---*/ unsigned int RPBBLK : 2; /*--- 7,8 ---*/ unsigned int RMCME : 1; /*--- 9 ---*/ unsigned int Reserved0 : 6; /*--- 10,11,12,13,14,15 ---*/ unsigned int XMCM : 2; /*--- 16,17 ---*/ unsigned int XCBLK : 3; /*--- 18,19,20 ---*/ unsigned int XPABLK : 2; /*--- 21,22 ---*/ unsigned int XPBBLK : 2; /*--- 23,24 ---*/ unsigned int XMCME : 1; /*--- 25 ---*/ unsigned int Reserved1 : 6; /*--- 26-31 ---*/ } Bits; }; union _McBSP_SRGR { volatile unsigned int Register; struct __McBSP_SRGR { unsigned int CLKGDV_MASK : 8; /*--- 0-7 ---*/ unsigned int FWID_MASK : 8; /*--- 8-15 ---*/ unsigned int FPER_MASK : 12; /*--- 16-27 ---*/ unsigned int FSGM_MASK : 1; /*--- 28 ---*/ unsigned int CLKSM_MASK : 1; /*--- 29 ---*/ unsigned int CLKSP_MASK : 1; /*--- 30 ---*/ unsigned int GSYNC_MASK : 1; /*--- 31 ---*/ } Bits; }; struct _McBSP { volatile unsigned int MCBSP_DRR_ADDR; /*--- 0x018C0000u ---*/ volatile unsigned int MCBSP_DXR_ADDR; /*--- 0x018C0004u ---*/ union _McBSP_SPCR MCBSP_SPCR_ADDR; /*--- 0x018C0008u ---*/ union _McBSP_RCR MCBSP_RCR_ADDR; /*--- 0x018C000Cu ---*/ union _McBSP_XCR MCBSP_XCR_ADDR; /*--- 0x01840010u ---*/ union _McBSP_SRGR MCBSP_SRGR_ADDR; /*--- 0x018C0014u ---*/ union _McBSP_MCR MCBSP_MCR_ADDR; /*--- 0x018C0018u ---*/ volatile unsigned int MCBSP_RCER_ADDR; /*--- 0x018C001Cu ---*/ volatile unsigned int MCBSP_XCER_ADDR; /*--- 0x018C0020u ---*/ union _McBSP_PCR MCBSP_PCR_ADDR; /*--- 0x018C0024u ---*/ }; extern struct _McBSP * const McBSP[2]; #endif /*--- #ifndef _mcbsp_h_ ---*/