/****************************************************************************** Copyright (c) 2004, Infineon Technologies. All rights reserved. No Warranty Because the program is licensed free of charge, there is no warranty for the program, to the extent permitted by applicable law. Except when otherwise stated in writing the copyright holders and/or other parties provide the program "as is" without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The entire risk as to the quality and performance of the program is with you. should the program prove defective, you assume the cost of all necessary servicing, repair or correction. In no event unless required by applicable law or agreed to in writing will any copyright holder, or any other party who may modify and/or redistribute the program as permitted above, be liable to you for damages, including any general, special, incidental or consequential damages arising out of the use or inability to use the program (including but not limited to loss of data or data being rendered inaccurate or losses sustained by you or third parties or a failure of the program to operate with any other programs), even if such holder or other party has been advised of the possibility of such damages. ****************************************************************************** Module : ifx_swdrv.h Date : 2004-09-01 Description : JoeLin Remarks: *****************************************************************************/ #ifndef _ADM_6996_MODULE_H_ #define _ADM_6996_MODULE_H_ #include /* command codes */ #define ADM_SW_SMI_READ 0x02 #define ADM_SW_SMI_WRITE 0x01 #define ADM_SW_SMI_START 0x01 #define ADM_SW_EEPROM_WRITE 0x01 #define ADM_SW_EEPROM_WRITE_ENABLE 0x03 #define ADM_SW_EEPROM_WRITE_DISABLE 0x00 #define EEPROM_TYPE 8 /* for 93C66 */ /* bit masks */ #define ADM_SW_BIT_MASK_1 0x00000001 #define ADM_SW_BIT_MASK_2 0x00000002 #define ADM_SW_BIT_MASK_4 0x00000008 #define ADM_SW_BIT_MASK_10 0x00000200 #define ADM_SW_BIT_MASK_16 0x00008000 #define ADM_SW_BIT_MASK_32 0x80000000 /* delay timers */ #define ADM_SW_MDC_DOWN_DELAY 5 #define ADM_SW_MDC_UP_DELAY 5 #define ADM_SW_CS_DELAY 5 /* MDIO modes */ #define ADM_SW_MDIO_OUTPUT 0 #define ADM_SW_MDIO_INPUT 1 #define ADM_SW_MAX_PORT_NUM 5 #define ADM_SW_MAX_VLAN_NUM 15 /* registers */ #define ADM_SW_PORT0_CONF 0x1 #define ADM_SW_PORT1_CONF 0x3 #define ADM_SW_PORT2_CONF 0x5 #define ADM_SW_PORT3_CONF 0x7 #define ADM_SW_PORT4_CONF 0x8 #define ADM_SW_PORT5_CONF 0x9 #define ADM_SW_VLAN_MODE 0x11 #define ADM_SW_MAC_LOCK 0x12 #define ADM_SW_VLAN0_CONF 0x13 #define ADM_SW_PORT0_PVID 0x28 #define ADM_SW_PORT1_PVID 0x29 #define ADM_SW_PORT2_PVID 0x2a #define ADM_SW_PORT34_PVID 0x2b #define ADM_SW_PORT5_PVID 0x2c #define ADM_SW_PHY_RESET 0x2f #define ADM_SW_MISC_CONF 0x30 #define ADM_SW_BNDWDH_CTL0 0x31 #define ADM_SW_BNDWDH_CTL1 0x32 #define ADM_SW_BNDWDH_CTL_ENA 0x33 /* port modes */ #define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ #define ADM_SW_PORT_AN 0x2 /* auto negotiation */ #define ADM_SW_PORT_100M 0x4 /* 100M */ #define ADM_SW_PORT_FULL 0x8 /* full duplex */ #define ADM_SW_PORT_TAG 0x10 /* output tag on */ #define ADM_SW_PORT_DISABLE 0x20 /* disable port */ #define ADM_SW_PORT_TOS 0x40 /* TOS first */ #define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ #define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ #define ADM_SW_PORT_PVID_SHIFT 10 #define ADM_SW_PORT_PVID_BITS 4 /* VLAN */ #define ADM_SW_VLAN_PORT0 0x1 #define ADM_SW_VLAN_PORT1 0x2 #define ADM_SW_VLAN_PORT2 0x10 #define ADM_SW_VLAN_PORT3 0x40 #define ADM_SW_VLAN_PORT4 0x80 #define ADM_SW_VLAN_PORT5 0x100 /* GPIO 012 enabled, output mode */ #define GPIO_ENABLEBITS 0x000700f8 /* define AMAZON GPIO port to ADM6996 EEPROM interface MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ #define GPIO_MDIO 1 //P1.0 #define GPIO_MDC 2 //P1.1 #define GPIO_MDCS 4 //P1.2 //joelin #define GPIO_MDIO 0 //joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ //joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ #define MDIO_INPUT 0x00000001 #define MDIO_OUTPUT_EN 0x00010000 /* type definitions */ typedef unsigned char U8; typedef unsigned short U16; typedef unsigned int U32; typedef struct _REGRW_ { unsigned int addr; unsigned int value; unsigned int mode; }REGRW, *PREGRW; /* IOCTL keys */ #define KEY_IOCTL_ADM_REGRW 0x01 #define KEY_IOCTL_ADM_SW_REGRW 0x02 #define KEY_IOCTL_ADM_SW_PORTSTS 0x03 #define KEY_IOCTL_ADM_SW_INIT 0x04 #define KEY_IOCTL_MAX_KEY 0x05 /* IOCTL MAGIC */ #define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') /* IOCTL parameters */ #define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) #define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) #define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) #define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) #define REG_READ 0x0 #define REG_WRITE 0x1 void adm_init(void); unsigned int adm_read(unsigned int addr); int adm_write(unsigned int addr, unsigned int dat); void adm_update_cache(void); /*------------------------------------------------------------------------------------------*\ * Reset the VLAN settings of the switch * \*------------------------------------------------------------------------------------------*/ void adm_vlan_fbox_reset(void); /*------------------------------------------------------------------------------------------*\ * Configure VLAN on the switch * * * * Argument: config - Configuration structure * * * * Return: 0 - everything okay, negative value otherwise * \*------------------------------------------------------------------------------------------*/ int adm_vlan_fbox_config(struct avm_switch_struct *config); /*------------------------------------------------------------------------------------------*\ * Invalidate the given cache value * * * * Argument: addr - Address of the register whose cache should be invalidated, thus forcing * * refetching it the next time * \*------------------------------------------------------------------------------------------*/ void adm_invalidate_register_cache(unsigned int addr); #define ADM_DEVICE_ADDRESS 0x100 #define ADM_GET_SERIAL_REG(addr) adm_read((addr) + ADM_DEVICE_ADDRESS + 0x200) #define ADM_GET_EEPROM_REG(addr) adm_read((addr) + ADM_DEVICE_ADDRESS) /*--- #define ADM_PUT_EEPROM_REG(addr, dat) adm_write((addr) + 0x0, (dat)) ---*/ #define ADM_PUT_EEPROM_REG(addr, dat) adm_write((addr) + 0x80, (dat)) /*--- #define ADM_PUT_EEPROM_REG(addr, dat) adm_write((addr) + 0x100, (dat)) ---*/ /*--- #define ADM_PUT_EEPROM_REG(addr, dat) adm_write((addr) + 0x180, (dat)) ---*/ #endif /* _ADM_6996_MODULE_H_ */