/*--------------------------------------------------------------------------------------------------------------*\ \*--------------------------------------------------------------------------------------------------------------*/ #ifndef _hw_reset_h_ #define _hw_reset_h_ /*--------------------------------------------------------------------------------------------------------------*\ \*--------------------------------------------------------------------------------------------------------------*/ #define RESET_PRCR (*(volatile unsigned *)(RESET_BASE+0x0)) /* Reset Control bits */ #define UART0_RESET (1 << 0) #define UART1_RESET (1 << 1) #define IIC_RESET (1 << 2) #define TIMER0_RESET (1 << 3) #define TIMER1_RESET (1 << 4) #define RESERVED5_RESET (1 << 5) #define GPIO_RESET (1 << 6) #define ADSLSS_RESET (1 << 7) #define USB_RESET (1 << 8) #define SAR_RESET (1 << 9) #define RESERVED10_RESET (1 << 10) #define VDMAVT_RESET (1 << 11) #define FSER_RESET (1 << 12) #define RESERVED13_RESET (1 << 13) #define RESERVED14_RESET (1 << 14) #define RESERVED15_RESET (1 << 15) #define VLYNQ1_RESET (1 << 16) #define EMACA_RESET (1 << 17) #define DMA_RESET (1 << 18) #define BIST_RESET (1 << 19) #define VLYNQ0_RESET (1 << 20) #define EMACB_RESET (1 << 21) #define MDIO_RESET (1 << 22) #define ADSLSS_DSP_RESET (1 << 23) #define RESERVED24_RESET (1 << 24) #define RESERVED25_RESET (1 << 25) #define EMAC_PHY_RESET (1 << 26) #if !defined(NO_TYPES) union _hw_non_reset { volatile unsigned int Reg; struct __hw_non_reset { unsigned int uart0_unreset : 1; unsigned int uart1_unreset : 1; unsigned int iic_unreset : 1; unsigned int timer0_unreset : 1; unsigned int timer1_unreset : 1; unsigned int reserved5_unreset : 1; unsigned int gpio_unreset : 1; unsigned int adslss_unreset : 1; unsigned int usb_unreset : 1; unsigned int sar_unreset : 1; unsigned int reserved10_unreset : 1; unsigned int vdmavt_unreset : 1; unsigned int fser_unreset : 1; unsigned int reserved13_unreset : 1; unsigned int reserved14_unreset : 1; unsigned int reserved15_unreset : 1; unsigned int vlynq1_unreset : 1; unsigned int emaca_unreset : 1; unsigned int dma_unreset : 1; unsigned int bist_unreset : 1; unsigned int vlynq0_unreset : 1; unsigned int emacb_unreset : 1; unsigned int mdio_unreset : 1; unsigned int adslss_dsp_unreset : 1; unsigned int reserved24_unreset : 1; unsigned int reserved25_unreset : 1; unsigned int emac_phy_unreset : 1; unsigned int reserved1 : 5; } Bits; }; extern union _hw_non_reset * const RESET; #endif /*--- #if !defined(NO_TYPES) ---*/ /*--------------------------------------------------------------------------------------------------------------*\ \*--------------------------------------------------------------------------------------------------------------*/ #define RESET_SWRCR (*(volatile unsigned *)(RESET_BASE+0x4)) /*--------------------------------------------------------------------------------------------------------------*\ \*--------------------------------------------------------------------------------------------------------------*/ #define RESET_RSP (*(volatile unsigned *)(RESET_BASE+0x8)) #endif /*--- #ifndef _hw_reset_h_ ---*/