/*******************************************************************************
**+--------------------------------------------------------------------------+**
**|                            ****                                          |**
**|                            ****                                          |**
**|                            ******o***                                    |**
**|                      ********_///_****                                   |**
**|                      ***** /_//_/ ****                                   |**
**|                       ** ** (__/ ****                                    |**
**|                           *********                                      |**
**|                            ****                                          |**
**|                            ***                                           |**
**|                                                                          |**
**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
**|                        ALL RIGHTS RESERVED                               |**
**|                                                                          |**
**+--------------------------------------------------------------------------+**
*******************************************************************************/

/** \file   pal_cppi4Cfg.h
    \brief  PAL CPPI4 Configuration header file

    This file has the static (compile time) configuration parameters for the
    CPPI4 PAL driver.

    @author     Greg Guyotte
 */

#ifndef __PAL_CPPI4_CFG_H__
#define __PAL_CPPI4_CFG_H__

/* CPPI4 hardware specific */
#define CPPI4_RESET_WAIT                1     /**< Msecs to wait after reset op */
#define CPPI4_MAX_CHANNELS              18    /**< Max num of ch's for PAL */
#define CPPI4_MAX_SAR_CHANNEL           15    /**< Highest SAR channel */
#define CPPI4_MIN_MAC_CHANNEL           16    /**< Lowest MAC channel */
#define CPPI4_NUM_RX_POP_QUEUES         8     /**< Number of RX pop queues */
#define CPPI4_NUM_RX_PRI_LEVELS         4     /**< Number of RX pri levels for
             each pop queue */
#define CPPI4_NUM_TX_PRI_LEVELS         4     /**< Number of TX pri levels for
             SAR channel 0 only */
#define CPPI4_NUM_RX_PUSH_QUEUES        4     /**< Number of RX push queues */
#define CPPI4_NUM_TX_POP_QUEUES         4     /**< Number of TX pop (completion)
             queues */
#define CPPI4_NUM_TX_PUSH_QUEUES        23    /**< Number of TX push queues */


/**
   \brief Macros for Address conversions 
   \note: These need to be ported for a different platform other than MIPS 
 */
#ifdef CPPI4_PAL_MIPS_OPTIMIZED
#define PAL_CPPI4_VIRT_2_PHYS(addr)     (((Uint)(addr)) &~ 0xE0000000)
#define PAL_CPPI4_PHYS_2_VIRT(addr)     ((Ptr)(((Uint)(addr)) | 0x80000000))
#define PAL_CPPI4_VIRT_NOCACHE(addr)    ((Ptr)((PAL_CPPI4_VIRT_2_PHYS(addr)) | 0xA0000000))
#else /* Use PAL_sysXXX API's */
#define PAL_CPPI4_VIRT_2_PHYS(addr)     PAL_osMemVirt2Phy((Ptr)(addr))
#define PAL_CPPI4_PHYS_2_VIRT(addr)     PAL_osMemPhy2Virt((Ptr)(addr))
#define PAL_CPPI4_VIRT_NOCACHE(addr)    PAL_osMemVirt2VirtNoCache((Ptr)(addr))
#endif

#endif /* __PAL_CPPI4_CFG_H__ */