#ifndef _YAMUNA_H #define _YAMUNA_H /*---------------------------------------------------- * Yamuna's Module Base Addresses *--------------------------------------------------*/ #define AVALANCHE_DSLSS_PERIPHERAL_BASE (KSEG1_ADDR(0x01000000)) #define AVALANCHE_DSLSS_DMEM_BASE (KSEG1_ADDR(0x01C00000)) #define AVALANCHE_NWSS_SLAVE_BASE (KSEG1_ADDR(0x03000000)) #define AVALANCHE_USB20_OTG_SLAVE_BASE (KSEG1_ADDR(0x03400000)) #define AVALANCHE_VOICESS_BASE (KSEG1_ADDR(0x04000000)) #define AVALANCHE_TDM_BASE (KSEG1_ADDR(0x08604000)) #define AVALANCHE_EMIF_CONTROL_BASE (KSEG1_ADDR(0x08610800)) #define AVALANCHE_GPIO_BASE (KSEG1_ADDR(0x08610900)) #define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1_ADDR(0x08610A00)) #define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1_ADDR(0x08610B00)) #define AVALANCHE_TIMER0_BASE (KSEG1_ADDR(0x08610C00)) #define AVALANCHE_TIMER1_BASE (KSEG1_ADDR(0x08610D00)) #define AVALANCHE_UART0_REGS_BASE (KSEG1_ADDR(0x08610E00)) #define AVALANCHE_UART1_REGS_BASE (KSEG1_ADDR(0x08610F00)) #define AVALANCHE_SPI_BASE (KSEG1_ADDR(0x08611000)) #define AVALANCHE_UART0_DMA_REGS_BASE (KSEG1_ADDR(0x08611400)) #define AVALANCHE_RESET_CONTROL_BASE (KSEG1_ADDR(0x08611600)) #define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1_ADDR(0x08611800)) #define AVALANCHE_DCL_BASE (KSEG1_ADDR(0x08611A00)) #define AVALANCHE_MDIO_BASE (KSEG1_ADDR(0x08611E00)) #define AVALANCHE_INTC_BASE (KSEG1_ADDR(0x08612400)) #define AVALANCHE_PCI_CFG_BASE (KSEG1_ADDR(0x08614000)) #define AVALANCHE_MCSP_BASE (KSEG1_ADDR(0x08620000)) #define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1_ADDR(0x0C000000)) #define AVALANCHE_SDRAM_BASE 0x14000000UL #define AVALANCHE_LOW_CPMAC_BASE (KSEG1_ADDR(0x0304E000)) #define AVALANCHE_HIGH_CPMAC_BASE (KSEG1_ADDR(0x0304E800)) #define AVALANCHE_NWSS_QMGR_BASE (KSEG1_ADDR(0x03068000)) #define AVALANCHE_NWSS_DMA_BASE (KSEG1_ADDR(0x0300A000)) /*---------------------------------------------------- * Yamuna Interrupt Map (Primary Interrupts) *--------------------------------------------------*/ #define AVALANCHE_UNIFIED_SECONDARY_INT 0 #define AVALANCHE_EXT_INT_0 1 /* Reserved */ /* Reserved */ /* Reserved */ #define AVALANCHE_TIMER_0_INT 5 #define AVALANCHE_TIMER_1_INT 6 #define AVALANCHE_UART0_INT 7 #define AVALANCHE_UART1_INT 8 #define AVALANCHE_TDM_TX_DMA 9 #define AVALANCHE_TDM_RX_DMA 10 #define AVALANCHE_MCSP_TX_DMA 11 #define AVALANCHE_MCSP_RX_DMA 12 #define AVALANCHE_MCSP_TX 13 #define AVALANCHE_MCSP_RX 14 #define AVALANCHE_NWSS_TX0 15 #define AVALANCHE_NWSS_TX1 16 #define AVALANCHE_NWSS_TX2 17 #define AVALANCHE_NWSS_TX3 18 #define AVALANCHE_UART_TX_DMA 19 #define AVALANCHE_UART_RX_DMA 20 #define AVALANCHE_C55X_DSP0 21 #define AVALANCHE_C55X_DSP1 22 /* Reserved */ #define AVALANCHE_LOW_VLYNQ_INT 24 #define AVALANCHE_PCI 25 #define AVALANCHE_TDM_TX 26 #define AVALANCHE_TDM_RX 27 #define AVALANCHE_DSLSS_TO_MIPS 28 #define AVALANCHE_SPI 29 #define AVALANCHE_USB_DMA 30 #define AVALANCHE_USB 31 #define AVALANCHE_NWSS_RX0 32 #define AVALANCHE_NWSS_RX1 33 #define AVALANCHE_NWSS_RX2 34 #define AVALANCHE_NWSS_RX3 35 #define AVALANCHE_NWSS_RX4 36 #define AVALANCHE_NWSS_RX5 37 #define AVALANCHE_NWSS_RX6 38 #define AVALANCHE_NWSS_RX7 39 /*----------------------------------------------------------- * Yamuna Interrupt Map (Secondary Interrupts) *---------------------------------------------------------*/ /* Reserved 40 */ /* Reserved 41 */ /* Reserved 42 */ #define AVALANCHE_MAC0_STATUS 43 #define AVALANCHE_MDIO_LINK_INT0 44 #define AVALANCHE_MDIO_USER_INT0 45 #define AVALANCHE_C55X_ADDR_EXCEPTION 46 #define AVALANCHE_EMIF_INT 47 /* Reserved 48 */ /* Reserved 49 */ /* Reserved 50 */ /* Reserved 51 */ /* Reserved 52 */ /* Reserved 53 */ /* Reserved 54 */ /* Reserved 55 */ /* Reserved 56 */ /* Reserved 57 */ /* Reserved 58 */ /* Reserved 59 */ #define AVALANCHE_MAC1_STATUS 60 #define AVALANCHE_MDIO_LINK_INT1 61 #define AVALANCHE_MDIO_USER_INT1 62 /* Reserved 63 */ /* Reserved 64 */ /* Reserved 65 */ /* Reserved 66 */ /* Reserved 67 */ /* Reserved 68 */ /* Reserved 69 */ /* Reserved 70 */ /* Reserved 71 */ /*----------------------------------------------------------- * Yamuna's Reset Bits *---------------------------------------------------------*/ #define AVALANCHE_UART0_RESET_BIT 0 #define AVALANCHE_UART1_RESET_BIT 1 #define AVALANCHE_SPI_RESET_BIT 2 #define AVALANCHE_TIMER0_RESET_BIT 3 #define AVALANCHE_TIMER1_RESET_BIT 4 /* Reserved 5 */ #define AVALANCHE_GPIO_RESET_BIT 6 #define AVALANCHE_DSLSS_RESET_BIT 7 #define AVALANCHE_USB_RESET_BIT 8 #define AVALANCHE_NWSS_RESET_BIT 9 #define AVALANCHE_TDM_RESET_BIT 10 /* Reserved 11 */ /* Reserved 12 */ /* Reserved 13 */ /* Reserved 14 */ #define AVALANCHE_LOW_VLYNQ_RESET_BIT 15 #define AVALANCHE_PCI_RESET_BIT 16 /* Reserved 17 */ #define AVALANCHE_UART_DMA_RESET_BIT 18 /* Reserved 19 */ #define AVALANCHE_C55X_RESET_BIT 20 /* Reserved 21 */ #define AVALANCHE_MDIO_RESET_BIT 22 #define AVALANCHE_DSLSS_DSP_RESET_BIT 23 /* Reserved 24 */ /* Reserved 25 */ #define AVALANCHE_USBPHY_RESET_BIT 26 /* Reserved 27 */ /* Reserved 28 */ #define AVALANCHE_MCSP_RESET_BIT 29 #define AVALANCHE_PCI_RESET_OUTPUT_BIT 30 #define AVALANCHE_PCI_RESET_OUTPUT_BUFFER_ENABLE_BIT 31 /*----------------------------------------------------------- * Yamuna's Power Bits: TODO: Some of the modules here are not present on Yamuna, update when spec is updated. *---------------------------------------------------------*/ #define AVALANCHE_POWER_MODULE_ROMP 2 #define AVALANCHE_POWER_MODULE_MDIOP 3 #define AVALANCHE_POWER_MODULE_SPIP 4 #define AVALANCHE_POWER_MODULE_C55XP 5 #define AVALANCHE_POWER_MODULE_RAMP 6 #define AVALANCHE_POWER_MODULE_TIMER1P 7 #define AVALANCHE_POWER_MODULE_TIMER0P 8 #define AVALANCHE_POWER_MODULE_WDTIMERP 9 #define AVALANCHE_POWER_MODULE_GPIOP 10 #define AVALANCHE_POWER_MODULE_NWSSP 11 #define AVALANCHE_POWER_MODULE_MCBSPP 12 #define AVALANCHE_POWER_MODULE_UARTP 13 #define AVALANCHE_POWER_MODULE_USBP 14 #define AVALANCHE_POWER_MODULE_BISTP 15 #define AVALANCHE_POWER_MODULE_VLYNQ0P 16 #define AVALANCHE_POWER_MODULE_PCIP 17 #define AVALANCHE_POWER_MODULE_EMIFP 18 #define AVALANCHE_POWER_MODULE_TDMP 19 #define AVALANCHE_POWER_MODULE_DSLSSP 20 #define AVALANCHE_POWER_MODULE_DMAP 21 #define AVALANCHE_POWER_MODULE_FILTERP 22 #define AVALANCHE_POWER_MODULE_PBISTP 23 /*--------------------------------------------------------------------------- * Yamuna board vectors *--------------------------------------------------------------------------*/ #define AVALANCHE_VECS (KSEG1_ADDR(AVALANCHE_SDRAM_BASE)) #define AVALANCHE_VECS_KSEG0 (KSEG0_ADDR(AVALANCHE_SDRAM_BASE)) /*----------------------------------------------------------------------------- * Yamuna's system register. *---------------------------------------------------------------------------*/ #define AVALANCHE_DCL_BOOTCR AVALANCHE_DCL_BASE #define AVALANCHE_DCL_MII1SELREG (AVALANCHE_DCL_BASE + 0x18) #define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8) #define AVALANCHE_RST_CTRL_PRCR AVALANCHE_RESET_CONTROL_BASE #define AVALANCHE_RST_CTRL_SWRCR (AVALANCHE_RESET_CONTROL_BASE + 0x4) #define AVALANCHE_RST_CTRL_RSR (AVALANCHE_RESET_CONTROL_BASE + 0x8) #define AVALANCHE_POWER_CTRL_PDCR (KSEG1_ADDR(0x08610A00)) #define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1_ADDR(0x08610A0C)) #define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14) #define AVALANCHE_GPIO_DIN_R1 (AVALANCHE_GPIO_BASE + 0x0) #define AVALANCHE_GPIO_DIN_R2 (AVALANCHE_GPIO_BASE + 0x40) #define AVALANCHE_GPIO_DOUT_R1 (AVALANCHE_GPIO_BASE + 0x04) #define AVALANCHE_GPIO_DOUT_R2 (AVALANCHE_GPIO_BASE + 0x44) #define AVALANCHE_GPIO_DIR_R1 (AVALANCHE_GPIO_BASE + 0x08) #define AVALANCHE_GPIO_DIR_R2 (AVALANCHE_GPIO_BASE + 0x48) #define AVALANCHE_GPIO_ENBL_R1 (AVALANCHE_GPIO_BASE + 0x0c) #define AVALANCHE_GPIO_ENBL_R2 (AVALANCHE_GPIO_BASE + 0x4c) /* * Yamon Prom print address. * Kept same as Titan and Apex. */ #define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1_ADDR(0x10000500)) #define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ #define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34) #define AVALANCHE_BASE_BAUD (3686400 / 16) #define AVALANCHE_GPIO_PIN_COUNT 44 #define AVALANCHE_GPIO_OFF_MAP {0x00000000} #include "yamuna_boards.h" #define AVALANCHE_MIPS_FREQ_DEFAULT 36000000 #define AVALANCHE_SBUS_FREQ_DEFAULT 12000000 #define AVALANCHE_PBUS_FREQ_DEFAULT 12000000 /* * Source: http://www.dal.asp.ti.com/dsl/projects/ip-mod/module-ids.htm * * NOTE: Minor rev number ignored */ #define AVALANCHE_MDIO_HW_MODULE_REV 0x000070100 #define AVALANCHE_USB20_OTG_HW_MODULE_REV 0x000140100 #define AVALANCHE_PCI_HW_MODULE_REV 0x000160100 /* These module IDs are created by fixing the MSB as 1 * Bit 31:0 bits30-16: ModuleID * bits15-0: Reserved for now. * * In future can be used as * Bits 15-8: Major rev number, * Bits 7-0: Minor rev number * */ #define AVALANCHE_SPI_HW_MODULE_REV 0x80010000 #define AVALANCHE_TDM_HW_MODULE_REV 0x80020000 #define AVALANCHE_NWSS_HW_MODULE_REV 0x80030000 #define AVALANCHE_CPMAC_HW_MODULE_REV 0x00500102 #endif /*_YAMUNA_H */