/******************************************************************************* **+--------------------------------------------------------------------------+** **| **** |** **| **** |** **| ******o*** |** **| ********_///_**** |** **| ***** /_//_/ **** |** **| ** ** (__/ **** |** **| ********* |** **| **** |** **| *** |** **| |** **| Copyright (c) 1998-2005 Texas Instruments Incorporated |** **| ALL RIGHTS RESERVED |** **| |** **+--------------------------------------------------------------------------+** *******************************************************************************/ #ifndef _YAMUNA_CLK_CNTL_H_ #define _YAMUNA_CLK_CNTL_H_ /************************************************************************** * Clock Control *****************************************************************************/ #define CLK_MHZ(x) ( (x) * 1000000 ) /* The order of ENUMs here should not be altered since * the register addresses are derived from the order */ typedef enum PAL_SYS_CLKC_ID_tag { CLKC_VBUS=0, /* Need to check the order of these clocks from the yamuna board specification */ CLKC_MIPS, CLKC_TDM, CLKC_VLYNQ, CLKC_PCI, CLKC_DSLSS, CLKC_C55, CLKC_EPHY, CLKC_SYS, CLKC_NUM, /* Not a real clock just to get the number of clocks */ } PAL_SYS_CLKC_ID_T; /** * This stucture is populated and passed on to the pal_sys_clkc_init function */ typedef struct PAL_SYS_Tnetd84xxInit_tag { UINT32 refclk; } PAL_SYS_Tnetd84xxInit; #endif