/**************************************************************************************** * ddc_init_close.c * Linux atm module implementation. * * 2007 (c) Texas Instruments Inc. * * 7/7/2006 AV Removed some un-used LED functions. * 8/15/2006 MK CQ10843: Fixed F4/F5 OAM ping test issue by setting oamLbTimeout to * 5000 when the environment variable oam_lb_timeout is not set. * 9/21/2006 EP CQ10932: Generated Doxygen-compliant DDC API. * 9/22/2006 AV Merging in the changes due to the new SAR firmware, and PDSP memory * map. * 9/26/2006 AV Making changes in the ddc_atm_init to pass in the Rx and Tx Queues to * use for the OAM channel. Enabling the OAM channel opening. Enabling * the Rx channel close. * 10/04/2006 AV Making sure that all the buffers (data, Eoc and OAM) are the exact * same size, as they share the same hardware buffer pool in UR8. * 10/06/2006 AV Adding the loopback as a functionality on the code. * 10/25/2006 AV Removing the free of the Sar Device structure as that is taken care of * by DDC_cpsarDeleteInstance(). * 10/31/2006 EP Enabled environment variables. * 12/01/2006 CPH/MK Corrected sar_freq for UR8 to 120Mhz (to fix QoS). * Set chInfo.Priority to 3(UBR priority) for OAM channel. * 1/29/2007 CZ CQ11294: fix Unloading DSL driver module * 02/14/2007 EP Added channel open configuration macro. * Added CPPI error handling config. ****************************************************************************************/ #include "ddc_ti_dsl.h" /* replace the DDA_prom_getenv */ #include "dda_input.h" //#include "ddc_dsl_callback.h" #ifdef AR7_SAR #define AAL5_PARM "id=aal5, base = 0x03000000, offset = 0, int_line=15, ch0=[RxBufSize=1522; RxNumBuffers = 32; RxServiceMax = 50; TxServiceMax=50; TxNumBuffers=32; CpcsUU=0x5aa5; TxVc_CellRate=0x3000; TxVc_AtmHeader=0x00000640]" #define SAR_PARM "id=sar,base = 0x03000000, reset_bit = 9, offset = 0; UniNni = 0, PdspEnable = 1" #define RESET_PARM "id=ResetControl, base=0xA8611600" #define CH0_PARM "RxBufSize=1522, RxNumBuffers = 32, RxServiceMax = 50, TxServiceMax=50, TxNumBuffers=32, CpcsUU=0x5aa5, TxVc_CellRate=0x3000, TxVc_AtmHeader=0x00000640" #endif /* gloabals */ unsigned int oamFarLBCount[4]; DDC_sar_stat sarStat; int oamLbTimeout; /* end of gloabals */ /* Local Variables */ #ifdef AR7_SAR static char *pAal5, *pSar, *pReset; static char parm_data[1024]; static char aal5Data[1024]; static char sarData[1024]; static char resetData[256]; #endif static char EOCVendorID[8] = { 0xb5, 0x00, 0x54, 0x53, 0x54, 0x43, 0x00, 0x00 }; /* internal APIs */ static int DDC_sar_setup_oam_channel(DDC_DslPriv *priv); static int DDC_sar_init(DDC_DslPriv *priv); static int DDC_dsl_init(DDC_DslPriv *priv); static int DDC_dsl_set_dsl(DDC_DslPriv *priv); #ifdef AR7_SAR static void DDC_sar_init_dev_parm(void); static int DDC_sar_init_module(OS_FUNCTIONS *os_funcs); static int DDC_sar_find_device(int unit, const char *find_name, void *device_info); static int DDC_sar_get_device_parm_uint(void *dev_info, const char *param, unsigned int *value); static int DDC_sar_get_device_parm_value(void *dev_info, const char *param, void *value); static void DDC_sar_isr_unregister(OS_DEVICE *os_dev, int interrupt_num); static void DDC_sar_teardown_complete(OS_DEVICE *OsDev, int ch, int Dir); #endif #ifndef YAMUNA static int DDC_atm_autoDetectDspBoost (void); #endif static void DDC_dsl_exit(DDC_DslPriv *priv); static void DDC_sar_exit(DDC_DslPriv *priv); /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * Function: int DDC_atm_init(struct atm_dev *dev) * * Description: Device Initialization * *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ int DDC_atm_init (DDC_DslPriv **privP, void *dev, unsigned int OamTxQ, unsigned int OamRxQ) { #ifndef YAMUNA unsigned int chip_id; #endif extern unsigned int _dsl_Feature_0; extern unsigned int _dsl_Feature_1; extern unsigned int _dsl_Feature_0_defined; extern unsigned int _dsl_Feature_1_defined; extern unsigned int _dsl_PhyControl_0; //CQ10280 extern unsigned int _dsl_PhyControl_1; extern unsigned int _dsl_PhyControl_0_defined; extern unsigned int _dsl_PhyControl_1_defined; DDC_DslPriv *priv; dgprintf (4, "DDC_atm_init()\n"); //priv = (Tn7AtmPrivate *) dev->dev_data; priv = DDA_malloc (sizeof(DDC_DslPriv)); if(!priv) { DDA_printf("%s: Cannot allocate memory \n",__FUNCTION__); return -DDC_DSL_ENODEV; } DDA_memset(priv, 0, sizeof(DDC_DslPriv)); #ifndef YAMUNA chip_id = DSLHAL_REG32 (REG_CVR) & 0xFFFF; switch (chip_id & 0xFFFF) { case CHIP_AR7: /* Sangam */ DDA_printf ("Sangam detected\n"); priv->dsl_int = ATM_DSL_INT_SANGAM; priv->def_sar_inter_pace = SANGAM_DEFAULT_IPACEMAX_VAL; /* MR 2344 */ priv->sar_freq = 50000000; /* 200Mhz/4 */ break; case CHIP_AR7O_212: /* Ohio212 */ case CHIP_AR7O_250_212: /* Ohio250 */ priv->dsl_int = ATM_DSL_INT_OHIO; priv->def_sar_inter_pace = OHIO_DEFAULT_IPACEMAX_VAL; /* MR 2344 */ priv->sar_freq = 53000000; /* 212Mhz/4 */ break; default: return -DDC_DSL_ENODEV; /* Unknown chip */ }; if (DDC_atm_autoDetectDspBoost ()) { if(!dslhal_api_boostDspFrequency ()) { /* Boosted the SAR frequency as the boost was successful. */ priv->sar_freq = 62500000; /* 250Mhz/4 */ } } #else priv->dsl_int = ATM_DSL_INT_YAMUNA; priv->def_sar_inter_pace = YAMUNA_DEFAULT_IPACEMAX_VAL; /* MR 2344 */ //priv->def_sar_inter_pace = 0; /* zero for now. */ priv->sar_freq = 120000000; /* 360Mhz/3 */ priv->OamCh_txQ = OamTxQ; priv->OamCh_rxQ = OamRxQ; #endif if (DDC_sar_init (priv) != 0) { DDA_printf ("Failed to init SAR.\n"); return -DDC_DSL_ENODEV; } // Inter-Op DSL phy Control // Note the setting of _dsl_Feature_0 and _dsl_Feature_1 must before // dslhal_api_dslStartup (in DDC_dsl_init()). //if ((ptr = DDA_prom_getenv ("DSL_FEATURE_CNTL_0")) != NULL) if(DDA_get_value_from_offset(DSL_FEATURE_CNTL_0, &_dsl_Feature_0)) { _dsl_Feature_0_defined = 1; } if(DDA_get_value_from_offset(DSL_FEATURE_CNTL_1, &_dsl_Feature_1)) { _dsl_Feature_1_defined = 1; } //CQ10280 // DSL phy Feature Control // Note the setting of _dsl_PhyControl_0 and _dsl_PhyControl_1 must before // dslhal_api_dslStartup (in DDC_dsl_init()). //if ((ptr = DDA_prom_getenv ("DSL_PHY_CNTL_0")) != NULL) if(DDA_get_value_from_offset(DSL_PHY_CNTL_0, &_dsl_PhyControl_0)) { _dsl_PhyControl_0_defined = 1; } if(DDA_get_value_from_offset(DSL_PHY_CNTL_1, &_dsl_PhyControl_1)) { _dsl_PhyControl_1_defined = 1; } if (DDC_dsl_init (priv) < 0) { DDA_printf ("Failed to init DSL.\n"); return -DDC_DSL_ENODEV; } // read config for turbo dsl if(DDA_get_value_from_offset(TurboDSL, &priv->bTurboDsl)) { DDA_printf("Using user input TurboDSL %d \n", priv->bTurboDsl); } else { priv->bTurboDsl = 1; } /* CPPI error handling */ if (DDA_get_value_from_offset(CppiErrProc, &priv->bCppiErrProc)) { DDA_printf("Using user input CPPI Err Handling: %d \n", priv->bCppiErrProc); } else { priv->bCppiErrProc = 1; } // @Added to make Rx buffer number & Service max configurable through // environment variable. if(DDA_get_value_from_offset(SarRxBuf, &priv->sarRxBuf)) { DDA_printf("Using user input for the number of Rx Buffers %d \n", priv->sarRxBuf); } else { priv->sarRxBuf = RX_BUFFER_NUM; } if(DDA_get_value_from_offset(SarRxMax, &priv->sarRxMax)) { DDA_printf("Using user input for the number of Rx Interrupts %d \n", priv->sarRxMax); } else { priv->sarRxMax = RX_SERVICE_MAX; } if(DDA_get_value_from_offset(SarTxBuf, &priv->sarTxBuf)) { DDA_printf("Using user input for the number of Tx Buffers %d \n", priv->sarTxBuf); } else { priv->sarTxBuf = TX_BUFFER_NUM; } if(DDA_get_value_from_offset(SarTxMax, &priv->sarTxMax)) { DDA_printf("Using user input for the number of Tx Interrupts %d \n", priv->sarTxMax); } else { priv->sarTxMax = TX_SERVICE_MAX; } //Now that all has been initialized. *privP = priv; priv->dev =dev; //AV_DBG DDA_printf("%s: Done priv = %p\n", __FUNCTION__, priv); return 0; } /** * \brief DDC_dsl_init * * This function initializes DSL interface * * @param priv Pointer to DSL driver private data * @return 0: Success * -1: Failure */ static int DDC_dsl_init(DDC_DslPriv *priv) { int retVal = 0; int sarlb = 0; /* Check to see if the DSL really needs to be initialized. */ if((DDA_get_value_from_offset(SarLB, &sarlb))) { DDA_printf("Using Dummy DSL PHY \n"); priv->lConnected = 1; } else { /* * start dsl */ if((retVal = dslhal_api_dslStartup(&priv->pIhw)) !=0 ) { DDA_printf("DSL start failed. Error Code (%d) and priv->pIhw is %p \n", retVal, priv->pIhw); return -1; } #ifndef YAMUNA // set dsl into overlay page reload mode priv->pIhw->bAutoRetrain = 1; #endif /* * For the changes for training modes using bit fields. Defaults are for * backward compatibility. */ if(DDA_get_value_from_offset(DSL_BIT_TMODE, &priv->pIhw->AppData.useBitField)) { DDA_printf("%s : env var DSL_BIT_TMODE is set\n", __FUNCTION__); } /* set default training properties */ DDC_dsl_set_dsl(priv); priv->pIhw->pOsContext = priv; //start_kthread(DDC_dsl_reload_overlay, &overlay_thread); priv->pIhw->AppData.usTxPower = 0; priv->pIhw->AppData.dsTxPower = 0; } //AV_DBG DDA_printf("%s: Done \n", __FUNCTION__); // DDC_dsl_clear_eoc_setup(); //cph clearEoc debug return 0; } /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static void DDC_sar_teardown_complete(OS_DEVICE *OsDev, int ch, int Dir) { //AV: just for debugging. DDA_printf("%s called for channel %d\n", __FUNCTION__, ch); return; } #endif /************************************************************ NEED FN HEADER ************************************************************/ unsigned int DDC_dsl_set_modulation(DDC_DslPriv *priv, void* data, int flag) { /* *INDENT-OFF* */ struct { char *mode_name; unsigned int mode_num; } mode_table[]={ {"T1413", OLD_TRAINING_VAL_T1413}, {"GDMT", OLD_TRAINING_VAL_GDMT}, {"GLITE", GLITE_MODE}, {"MMODE", OLD_TRAINING_VAL_MMODE}, {"NMODE", NO_MODE}, {"AD2MOD", ADSL2_MODE}, {"AD2DEL", ADSL2_DELT}, {"A2PMOD", ADSL2_PLUS}, {"A2PDEL", ADSL2_PLUS_DELT} }; /* *INDENT-ON* */ int retval = TRUE; int train_mode = -1; int size; char *cp = (char *)data; int i; dgprintf(4,"DDC_dsl_set_modulation\n"); if (priv->pIhw->AppData.useBitField) { mode_table[0].mode_num = NEW_TRAINING_VAL_T1413; mode_table[1].mode_num = NEW_TRAINING_VAL_GDMT; mode_table[3].mode_num = NEW_TRAINING_VAL_MMODE; } for (i = 0; i < NUM_ELEMS (mode_table); i++) { if (!DDA_strcmp (data, mode_table[i].mode_name)) { train_mode = mode_table[i].mode_num; break; } } if (train_mode==-1) { /* * Since we don't want to compare the nul terminator */ size = DDA_strlen("tmode"); if(!DDA_strncmp(cp, "tmode", size)) { cp += size; /* * Read the specified mode, which has to be a hex value */ if((*cp == '0') && ((*(cp + 1) == 'x') || (*(cp + 1) == 'X'))) { train_mode = DDA_atoh(cp + 2); } else { train_mode = DDA_atoh(cp); } } else { /* * CQ9605: The new default command format for changing the modulation. */ if((*cp == '0') && ((*(cp + 1) == 'x') || (*(cp + 1) == 'X'))) { train_mode = DDA_atoh(cp + 2); } else if(!flag) { /* * For backward compatibility for modulation */ train_mode = DDA_atoi(cp); } } } if(train_mode >= 0) { DDA_printf("%s : Setting mode to %#x\n", __FUNCTION__, train_mode); retval = dslhal_api_setTrainingMode(priv->pIhw, train_mode); } return retval; } /************************************************************ NEED FN HEADER ************************************************************/ static int DDC_dsl_set_dsl(DDC_DslPriv *priv) { char *ptr = NULL; int value; int i; char tmp[4]; unsigned int bitswap; // OAM Feature Configuration dslhal_api_setOamFeature(priv->pIhw, 0x0000000C); /* Do only if we are in the new Base PSP 7.4.*/ #if ((PSP_VERSION_MAJOR == 7) && (PSP_VERSION_MINOR <= 4)) /* Check to see if we are operating in the new bit mode. */ //ptr = DDA_prom_getenv("DSL_BIT_TMODE"); if (priv->pIhw->AppData.useBitField) { /* If we are see if this is the first time the user has upgraded. */ if(!DDA_get_value_from_offset(DSL_UPG_DONE, &value)) { /* If it is the first time the user is upgrading, then make sure that we clear the modulation environment variable, as this could potentially not have the same meaning in the new mode. */ prom_unsetenv("modulation"); prom_setenv("DSL_UPG_DONE", "1"); } } #endif // modulation if(DDA_get_value_from_offset(modulation, &ptr)) { DDC_dsl_set_modulation(priv, ptr, FALSE); } // Fine Gains if(DDA_get_value_from_offset(fine_gain_control, &value)) { dslhal_api_setFineGainCtrl(priv->pIhw, (unsigned)value); } if(DDA_get_value_from_offset(fine_gain_control, &value)) { /* This expects the input to be in hex...so user has to make sure that they enter 0x... */ if (value) { dslhal_api_setFineGainValue(priv->pIhw, (unsigned)value); } } // margin retrain if(DDA_get_value_from_offset(enable_margin_retrain, &value)) { if(value == 1) { dslhal_api_setMarginMonitorFlags(priv->pIhw, 0, 1); priv->bMarginRetrainEnable = 1; //DDA_printf("enable showtime margin monitor.\n"); if(DDA_get_value_from_offset(margin_threshold, &value)) { //DDA_printf("Set margin threshold to %d x 0.5 db\n",value); if(value >= 0) { dslhal_api_setMarginThreshold(priv->pIhw, value); priv->bMarginRetrainEnable = 0; } } } } // rate adapt if(DDA_get_value_from_offset(enable_rate_adapt, &value)) { dslhal_api_setRateAdaptFlag(priv->pIhw, value); } // trellis if(DDA_get_value_from_offset(trellis, &value)) { dslhal_api_setTrellisFlag(priv->pIhw, value); priv->pIhw->AppData.trellis = value; //DDA_printf("trellis=%d\n"); } // bitswap if(DDA_get_value_from_offset(bitswap, &bitswap)) { dslhal_api_usBitSwap(priv->pIhw, 0, bitswap); dslhal_api_dsBitSwap(priv->pIhw, 0, bitswap); } // maximum bits per carrier if(DDA_get_value_from_offset(maximum_bits_per_carrier, &value)) { dslhal_api_setMaxBitsPerCarrierUpstream(priv->pIhw, value); } // maximum interleave depth if(DDA_get_value_from_offset(maximum_interleave_depth, &value)) { dslhal_api_setMaxInterleaverDepth(priv->pIhw, value); } // inner and outer pairs if(DDA_get_value_from_offset(pair_selection, &value)) { dslhal_api_selectInnerOuterPair(priv->pIhw, value); } //Dying Gasp Polarity if(DDA_get_value_from_offset(dgas_polarity, &value)) { dslhal_api_configureDgaspLpr(priv->pIhw, 1, 1); dslhal_api_configureDgaspLpr(priv->pIhw, 0, value); } //los_alarm if(DDA_get_value_from_offset(los_alarm, &value)) { dslhal_api_disableLosAlarm(priv->pIhw, value); } //EOC Vendor ID. ptr = NULL; if(DDA_get_value_from_offset(eoc_vendor_id, &ptr)) { if(ptr) { for(i=0;i<8;i++) { tmp[0]=ptr[i*2]; tmp[1]=ptr[i*2+1]; tmp[2]=0; EOCVendorID[i] = DDA_atoh(tmp); //DDA_printf("tmp=%s--", tmp); //DDA_printf("ID[%d]=0x%02x ", i, (unsigned char)EOCVendorID[i]); } if (priv->pIhw->netService == 2) // annex b { // DDA_printf("EOCVendorID=%02x %02x %02x %02x %02x %02x %02x %02x\n", // EOCVendorID[0], EOCVendorID[1], EOCVendorID[2], EOCVendorID[3], // EOCVendorID[4], EOCVendorID[5], EOCVendorID[6], EOCVendorID[7]); dslhal_api_setEocVendorId(priv->pIhw, EOCVendorID); } } } //eoc_vendor_revision ptr = NULL; if(DDA_get_value_from_offset(eoc_vendor_revision, &ptr)) { //DDA_printf("eoc rev=%d\n", DDA_atoi(ptr)); dslhal_api_setEocRevisionNumber(priv->pIhw, ptr); } //EOC Vendor Serial Number ptr = NULL; if(DDA_get_value_from_offset(eoc_vendor_serialnum, &ptr)) { if(ptr) { dslhal_api_setEocSerialNumber(priv->pIhw, ptr); } } // CQ10037 Added invntry_vernum environment variable to be able to set version number in ADSL2, ADSL2+ modes. ptr = NULL; if(DDA_get_value_from_offset(invntry_vernum, &ptr)) { if(ptr) { dslhal_api_setEocRevisionNumber(priv->pIhw, ptr); } } return 0; } /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * Function: static int DDC_atm_autoDetectDspBoost(void) * * Description: Detect whether Dsp frequency should be boosted or not * * Input: none * Output: none * Return: * * 0 -- do not boost * 1 -- Boost * *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ #ifndef YAMUNA static int DDC_atm_autoDetectDspBoost (void) { unsigned int dspfreq; unsigned int reg_cvr; unsigned int reg_DIDR1; unsigned int reg_DIDR2; // unsigned int reg_codec_CTRL2; unsigned int PG_num; unsigned int chip_id; unsigned int timecode; unsigned int TrimRegVal; int boostDsp = 0; int dsp_noboost = 0; DDA_get_value_from_offset(dsp_noboost, &dsp_noboost); if (DDA_get_value_from_offset(dsp_freq, &dspfreq)) { if (dspfreq == 250) { boostDsp = 1; } } else if (!dsp_noboost) /* make sure dsp_noboost flag was not set * before boost */ { /* * auto detect whether boost dsp clock or not */ reg_cvr = DSLHAL_REG32 (REG_CVR); PG_num = (reg_cvr >> 16) & 0xFF; reg_DIDR1 = DSLHAL_REG32 (REG_DIDR1); reg_DIDR2 = DSLHAL_REG32 (REG_DIDR2); chip_id = reg_cvr & 0xFFFF; switch (chip_id) { case CHIP_AR7: /* 7300, 7300A or 7300C */ // DDA_printf("Sangam detected\n"); if (!(reg_DIDR2 & BIT23)) { /* 7300 or 7300A */ if ((PG_num != 0x57) && (PG_num >= 0x23)) { /* * Rev 2.3 or larger but not 5.7, can boost */ boostDsp = 1; DDC_atm_set_can_support_adsl2 (TRUE); } else { /* * timecode gereatre than 4208000 can boost */ timecode = ((reg_DIDR2 & 0x1FFF) << 10) | ((reg_DIDR1 & 0xFFC00000) >> 22); dgprintf (4, "timecode=%d\n", timecode); if (timecode > 4208000) boostDsp = 1; } DDC_atm_set_can_support_adsl2 (TRUE); } else { DDA_printf ("7300C detected\n"); /* else 7300C: don't boost */ DDC_atm_set_can_support_adsl2 (FALSE); } break; case CHIP_AR7O_212: /* Ohio212: don't boost */ DDA_printf ("Ohio212 detected\n"); DDC_atm_set_can_support_adsl2 (FALSE); break; case CHIP_AR7O_250_212: /* Ohio250 or Ohio212(new) */ /* * Check Buck Trim bit see if it's Ohio250 or Ohio 212 */ DSLHAL_REG32 (REG_PRCR) &= ~PRCR_DSP; /* put DSP in reset */ DSLHAL_REG32 (REG_PRCR) |= (PRCR_ADSLSS); /* reset ADSLSS */ DSLHAL_REG32 (REG_ADSLSS_PRCR) |= ADSLSS_PRCR_DSL_SPA; /* reset * ADSLSS * DSL_SPA */ DDA_mdelay (10); /* Sanjay : Delay the read from the register * as sometimes this causes incorrect value * to be read from the register */ TrimRegVal = (DSLHAL_REG32 (REG_BUCKTRIM_READ) >> 8) & 0x07; if (TrimRegVal == 0x07) { DDA_printf ("Ohio250(7200/7100A2) detected\n"); boostDsp = 1; DDC_atm_set_can_support_adsl2 (TRUE); } else { if (TrimRegVal==0x06) { boostDsp = 1; DDA_printf ("Ohio250(7100A1) detected\n"); } else DDA_printf ("Ohio212(7100Trim=%d) detected\n", TrimRegVal); DDC_atm_set_can_support_adsl2 (FALSE); } break; default: dgprintf (4, "Unknown chip id, cvr=%08x\n", reg_cvr); DDC_atm_set_can_support_adsl2 (FALSE); break; } /* switch */ } if (boostDsp) dgprintf (4, "set dspfreq 250Mhz\n"); return (boostDsp); } #endif //CT CQ10076 - Added function to get chipset Id /************************************************************ NEED FN HEADER ************************************************************/ static int DDC_sar_init(DDC_DslPriv *priv) { #ifdef AR7_SAR int retCode; int hal_funcs_size; HAL_FUNCTIONS *pHalFunc; HAL_DEVICE *pHalDev; OS_FUNCTIONS *pOsFunc; int oamMod; int lbTimeout; dgprintf(4, "DDC_sar_init\n"); pOsFunc = (OS_FUNCTIONS *)DDA_malloc(sizeof(OS_FUNCTIONS)); priv->pSarOsFunc = (void *)pOsFunc; /* init boot parms */ DDC_sar_init_dev_parm(); /* init sar os call back functions */ retCode = DDC_sar_init_module(pOsFunc); if (retCode != 0) /* error */ { DDA_printf("Failed to init SAR OS Functions\n"); return (1); } //AV_DDM DDA_critical_on(); /* Init sar hal */ //AV_DDM: Changing OS_DEVICE to DDC pointer. retCode = cpaal5InitModule(&pHalDev, (OS_DEVICE*) priv, &pHalFunc, pOsFunc, sizeof(OS_FUNCTIONS), &hal_funcs_size, 0); if (retCode != 0) /* error */ { DDA_printf("Failed to init SAR HAL\n"); return (1); } /* sanity check */ if (pHalDev == NULL || pHalFunc == NULL || hal_funcs_size != sizeof(HAL_FUNCTIONS) ) { DDA_printf("Invalid SAR hal and/or functions.\n"); return (1); } /* remeber HAL pointers */ priv->pSarHalDev = (void *)pHalDev; priv->pSarHalFunc = (void *)pHalFunc; /* Probe for the Device to get hardware info from driver */ retCode = pHalFunc->Probe(pHalDev); if (retCode !=0) { DDA_printf("SAR hal probing error.\n"); return (1); } /* init sar hal */ retCode = pHalFunc->Init(pHalDev); if (retCode != 0) /* error */ { DDA_printf("pHalFunc->Init failed. err code =%d\n", retCode); return (1); } /* open hal module */ retCode = pHalFunc->Open(pHalDev); if (retCode != 0) /* error */ { DDA_printf("pHalFunc->open failed, err code: %d\n",retCode ); return (1); } /* init sar for firmware oam */ oamMod = 1; pHalFunc->Control(pHalDev,"OamMode", "Set", &oamMod); /* read in oam lb timeout value */ if (DDA_get_value_from_offset(oam_lb_timeout, &lbTimeout)) { if(lbTimeout) { oamLbTimeout = lbTimeout; pHalFunc->Control(pHalDev,"OamLbTimeout", "Set", &lbTimeout); } } else { oamLbTimeout = 5000; } oamFarLBCount[0]=0; oamFarLBCount[1]=0; oamFarLBCount[2]=0; oamFarLBCount[3]=0; DDA_memset(&sarStat, 0 , sizeof(sarStat)); /* setup channel 15 for oam operation */ DDC_sar_setup_oam_channel(priv); //AV_DDM DDA_critical_off(); #endif /* AR7_SAR */ #ifdef UR8_SAR int retCode; static int ddcInitStatus = 0; DDC_CpsarDevice *SarDev = NULL; int sarlb = 0; if((ddcInitStatus != 2) && (!priv->SarDev)) { /* Create DDC Instance */ retCode = DDC_cpsarCreateInstance(0, /* Instance Id */ priv, /* DDC Handle */ //&CpsarDDACbInterface, /* Pointer to DDA Callback function table */ &SarDev, /* Address of pointer to DDC Handle */ NULL); /* Param not used */ if (retCode != CPSAR_SUCCESS) { DDA_printf("\nERROR:%s: Error %08X from DDC_cpsarCreateInstance()", __FUNCTION__, retCode); return -1; } /* Initialize DDC Instance by passing initial configuration structure */ DDA_get_value_from_offset(SarLB, &sarlb); retCode = DDC_cpsarInit(SarDev, sarlb); if (retCode != CPSAR_SUCCESS) { DDA_printf("\nERROR:%s: Error %08X from DDC_cpsarInit()", __FUNCTION__, retCode); DDA_free(SarDev); return -2; } ddcInitStatus = 2; /* Instance initialized */ //AV_SM : Since all the initializations have been done. priv->SarDev = SarDev; /* Open the OAM channel. */ DDC_sar_setup_oam_channel(priv); } else { DDA_printf("%s: SAR is already initialized. \n", __FUNCTION__); } #endif /* UR8_SAR */ dgprintf(4, "DDC_sar_init done"); return 0; } /************************************************************ NEED FN HEADER ************************************************************/ #define USE_PDSP_054 //CQ10273 static int DDC_sar_setup_oam_channel(DDC_DslPriv *priv) { #ifdef AR7_SAR CHANNEL_INFO chInfo; HAL_FUNCTIONS *pHalFunc; HAL_DEVICE *pHalDev; int chan=RESERVED_OAM_CHANNEL; //15; int auto_pvc = 0; //AV_26 //unsigned int oam2host_ch; //char oam_str[20]; dgprintf(4, "DDC_sar_setup_oam_channel\n"); pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc; pHalDev = (HAL_DEVICE *)priv->pSarHalDev; //CQ10273 DDA_get_value_from_offset(autopvc_enable, &auto_pvc); DDA_memset(&chInfo, 0xff, sizeof(chInfo)); /* channel specific */ chInfo.Channel = RESERVED_OAM_CHANNEL; //15; hardcoded for last channel chInfo.Direction = 0; chInfo.Vci = 30; /* just need below 32 */ chInfo.Vpi = 0; chInfo.TxVc_QosType = 2; /*default */ chInfo.PktType = PACKET_TYPE_TRANS; //PACKET_TYPE_OAM; To correct Data Cell to Host Issues! 10/07/05 chInfo.TxServiceMax = 2; chInfo.RxServiceMax = 2; chInfo.TxNumQueues = 1; chInfo.TxNumBuffers = 4; chInfo.RxNumBuffers = 4; chInfo.RxBufSize = 256; if( auto_pvc == 0) { chInfo.RxVc_OamToHost = 0; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamToHost = 0; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.FwdUnkVc = 0; } else { chInfo.RxVc_OamToHost = 1; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamToHost = 1; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVc_OamCh = RESERVED_OAM_CHANNEL;//jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamCh = RESERVED_OAM_CHANNEL;//jz: CQ#9861, Set the unmatched oam ping to the host flags if(auto_pvc<=2) chInfo.FwdUnkVc = 1; else //3 or more chInfo.FwdUnkVc = 0; // was 1; test fix for not forwarding data cells!enable forwarding of unknown vc //DDA_printf("DBG----: autopvc_enable=%d(1: autoPVC ok, 2: unK=1 and 54chg, 3: unK=0 Greg's suggestion) chInfo.FwdUnkVc set to %d.\n", auto_pvc, chInfo.FwdUnkVc); } //chInfo.FwdUnkVc = 1; //priginal was 1 chInfo.TxVc_AtmHeader = DDC_sar_atm_header((int)chInfo.Vpi, chInfo.Vci); chInfo.RxVc_AtmHeader = DDC_sar_atm_header((int)chInfo.Vpi, chInfo.Vci); chInfo.TxVp_AtmHeader = DDC_sar_atm_header((int)chInfo.Vpi, 0); chInfo.RxVp_AtmHeader = DDC_sar_atm_header((int)chInfo.Vpi, 0); dgprintf(4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader); if(pHalFunc->ChannelSetup(pHalDev, &chInfo, NULL)) { DDA_printf("failed to setup channel =%d.\n", chan); return -1; } #endif /* AR7_SAR */ #ifdef UR8_SAR CpsarChInfo chInfo; DDC_CpsarDevice *SarDev = priv->SarDev; int chan = RESERVED_OAM_CHANNEL; //15; int auto_pvc = 0; int vpi = 0; int vci = 30; /* just need below 32 */ int Qnum = CH_CONFIG(priv->OamCh_rxQ, priv->OamCh_txQ, priv->bCppiErrProc); dgprintf(4, "DDC_sar_setup_oam_channel\n"); //CQ10273 DDA_get_value_from_offset(autopvc_enable, &auto_pvc); DDA_memset(&chInfo, 0, sizeof(chInfo)); /* channel specific */ chInfo.chNum = RESERVED_OAM_CHANNEL; //15; hardcoded for last channel chInfo.chDir = DDC_NET_CH_DIR_BIDIRECTIONAL; chInfo.TxVc_QosType = 2; chInfo.Priority = 3; //UBR /*default */ chInfo.PktType = PKT_TYPE_TRANS; //PACKET_TYPE_OAM; To correct Data Cell to Host Issues! 10/07/05 //AV_SM : TODO add these following to the list. chInfo.TxServiceMax = 2; chInfo.RxServiceMax = 2; //chInfo.TxNumQueues = 1; chInfo.TxNumBuffers = 4; chInfo.RxNumBuffers = 4; //chInfo.RxBufSize = 256; chInfo.RxBufSize = RX_BUFFER_SIZE; //All channels using the same queue have to use the same size. chInfo.numTxBD = 4; chInfo.chState = 0; if( auto_pvc == 0) { chInfo.RxVc_OamToHost = 0; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamToHost = 0; //jz: CQ#9861, Set the unmatched oam ping to the host flags //chInfo.FwdUnkVc = 0; } else { chInfo.RxVc_OamToHost = 1; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamToHost = 1; //jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVc_OamCh = RESERVED_OAM_CHANNEL;//jz: CQ#9861, Set the unmatched oam ping to the host flags chInfo.RxVp_OamCh = RESERVED_OAM_CHANNEL;//jz: CQ#9861, Set the unmatched oam ping to the host flags //AV_SM #if 0 if(auto_pvc<=2) chInfo.FwdUnkVc = 1; else //3 or more chInfo.FwdUnkVc = 0; // was 1; test fix for not forwarding data cells!enable forwarding of unknown vc #endif //DDA_printf("DBG----: autopvc_enable=%d(1: autoPVC ok, 2: unK=1 and 54chg, 3: unK=0 Greg's suggestion) chInfo.FwdUnkVc set to %d.\n", auto_pvc, chInfo.FwdUnkVc); } //chInfo.TxVc_AtmHeader = DDC_sar_atm_header((int)vpi, vci); chInfo.AtmHeader = DDC_sar_atm_header((int)vpi, vci); //chInfo.RxVc_AtmHeader = DDC_sar_atm_header((int)vpi, vci); //chInfo.TxVp_AtmHeader = DDC_sar_atm_header((int)vpi, 0); //chInfo.RxVp_AtmHeader = DDC_sar_atm_header((int)vpi, 0); //dgprintf(4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader); /* Open the Sar channel. */ chInfo.chDir = DDC_NET_CH_DIR_TX; if(DDC_cpsarChOpen(SarDev, &chInfo, Qnum)) { DDA_printf("failed to setup OAM channel =%d.\n", chan); return -1; } chInfo.chDir = DDC_NET_CH_DIR_RX; if(DDC_cpsarChOpen(SarDev, &chInfo, Qnum)) { DDA_printf("failed to setup OAM channel =%d.\n", chan); return -1; } #endif // claiming the channel priv->lut[chan].vpi = 0; priv->lut[chan].vci = 30; priv->lut[chan].chanid = chan; priv->lut[chan].inuse = 1; return 0; } /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static void DDC_sar_init_dev_parm(void) { //AV_26 #if 0 int i; /* aal5 */ //DDA_strcpy(aal5Parm.id, "aal5"); aal5Parm.base = 0x03000000; aal5Parm.offset = 0; aal5Parm.int_line=15; aal5Parm.chan[0].RxBufSize=1600; aal5Parm.chan[0].RxNumBuffers = 32; aal5Parm.chan[0].RxServiceMax = 50; aal5Parm.chan[0].TxServiceMax=50; aal5Parm.chan[0].TxNumBuffers=32; aal5Parm.chan[0].CpcsUU=0x5aa5; aal5Parm.chan[0].TxVc_CellRate=0x3000; aal5Parm.chan[0].TxVc_AtmHeader=0x00000640; for(i=1;i<8;i++) { DDA_memcpy(&aal5Parm.chan[i], &aal5Parm.chan[0], sizeof(aal5Parm.chan[0])); } /* sar */ //DDA_strcpy(sarParm.id, "sar"); sarParm.base = 0x03000000; sarParm.reset_bit = 9; sarParm.offset = 0; sarParm.UniNni = 0; #endif pAal5 = aal5Data; pSar = sarData; pReset = resetData; DDA_strcpy(pAal5, AAL5_PARM); DDA_strcpy(pSar, SAR_PARM); DDA_strcpy(pReset, RESET_PARM); } #endif /* AR7_SAR */ /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static int DDC_sar_init_module(OS_FUNCTIONS *os_funcs) { dgprintf(4, "DDC_sar_init_module\n"); if( os_funcs == 0 ) { return(-1); } os_funcs->Control = DDC_sar_control; os_funcs->CriticalOn = DDA_critical_on; os_funcs->CriticalOff = DDA_critical_off; os_funcs->DataCacheHitInvalidate = DDC_atm_data_invalidate; os_funcs->DataCacheHitWriteback = DDC_atm_data_writeback; os_funcs->DeviceFindInfo = DDC_sar_find_device; os_funcs->DeviceFindParmUint = DDC_sar_get_device_parm_uint; os_funcs->DeviceFindParmValue = DDC_sar_get_device_parm_value; os_funcs->Free = DDA_free; os_funcs->FreeRxBuffer = DDA_free_buffer; os_funcs->FreeDev = DDA_free_dev; os_funcs->FreeDmaXfer = DDA_free_dma_transfer; os_funcs->IsrRegister = DDC_atm_sarhal_isr_register; os_funcs->IsrUnRegister = DDC_sar_isr_unregister; os_funcs->Malloc = DDA_malloc; os_funcs->MallocRxBuffer = DDA_malloc_rxbuffer; os_funcs->MallocDev = DDA_malloc_dev; os_funcs->MallocDmaXfer = DDA_malloc_dma_transfer; os_funcs->Memset = DDA_memset; os_funcs->Printf = DDA_printf; os_funcs->Receive = DDC_sar_receive; //AV_SM : One layer of translation. //os_funcs->SendComplete = DDA_send_complete; os_funcs->SendComplete = DDC_send_complete; os_funcs->Strcmpi = DDA_strcmp; os_funcs->Sprintf = DDA_sprintf; os_funcs->Strlen = DDA_strlen; os_funcs->Strstr = DDA_strstr; os_funcs->Strtoul = DDA_strtoul; os_funcs->TeardownComplete = DDC_sar_teardown_complete; return(0); } #endif /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static int DDC_sar_find_device(int unit, const char *find_name, void *device_info) { int ret_val = 0; char **ptr; ptr = (char **)device_info; dgprintf(3,"DDC_sar_find_device\n"); if(DDA_strcmp(find_name, "aal5")==0) { *ptr = pAal5; } else if(DDA_strcmp(find_name, "sar")==0) { dgprintf(3, "pSar=%s\n", pSar); *ptr = pSar; } else if(DDA_strcmp(find_name, "reset")==0) { dgprintf(3, "pReset=%s\n", pReset); *ptr = pReset; } device_info = NULL; return(ret_val); } #endif /* AR7_SAR */ /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static int DDC_sar_get_device_parm_uint(void *dev_info, const char *param, unsigned int *value) { char *dev_str; char *pMatch; int i=0, j=0; char val_str[64]; unsigned int val; int base = 10; dgprintf(6, "DDC_sar_get_device_parm_uint()\n"); dev_str = (char *)dev_info; dgprintf(3, "parm=%s\n", param); pMatch = DDA_strstr(dev_str, param); if(pMatch) { //get "=" position while(pMatch[i] != '=') { i++; } i++; // get rid of spaces while(pMatch[i]== ' ') { i++; } //get rid of 0x if(pMatch[i]== '0') { if(DDA_toupper(pMatch[i+1]) == 'X') //if(pMatch[i+1] == 'x' || pMatch[i+1] == 'X') { i+=2; base = 16; } } // get next delineator while(pMatch[i] != ',' && pMatch[i] != 0x0) { val_str[j]=pMatch[i]; j++; i++; } val_str[j]=0; val = DDA_strtoul(val_str, (char **)NULL, base); dgprintf(4, "val =%d\n", val); *value = val; return 0; } dgprintf(3, "match not found.\n"); if(DDA_strcmp(dev_str, "debug")==0) { dgprintf(6,"debug..\n"); *value = 6; return 0; } return (1); } #endif /* AR7_SAR */ /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static int DDC_sar_get_device_parm_value(void *dev_info, const char *param, void *value) { char *dev_str; char *pMatch; int i=0, j=0; char *pVal; dgprintf(3, "DDC_sar_get_device_parm_value().\n"); pVal = (char *) parm_data; dev_str = (char *)dev_info; dgprintf(3, "dev_info: \n%s\n", dev_str); dgprintf(3, "param=%s\n", param); if(DDA_strcmp(param, "Ch0")==0) { *(char **)value = CH0_PARM; dgprintf(3, "value =%s\n", *(char **)value); return 0; } pMatch = DDA_strstr(dev_str, param); if(pMatch) { //get "=" position while(pMatch[i] != '=') { i++; } i++; // get rid of spaces while(pMatch[i]== ' ') { i++; } if(pMatch[i] != '[') //"[" { // get next delineator while(pMatch[i] != ',' && pMatch[i] != 0x0) { pVal[j] = pMatch[i]; j++; i++; } pVal[j]=0; *(char **)value = pVal; return 0; } else { i++; //skip "[" while(pMatch[i] != ']') { if(pMatch[i] == ';') //";" pVal[j] = ','; else pVal[j] = pMatch[i]; j++; i++; } pVal[j] = 0; *(char **)value = pVal; return 0; } } return (1); } #endif /* AR7_SAR */ /************************************************************ NEED FN HEADER ************************************************************/ //AV_DDM Not needed any more. #if AR7_SAR static inline void DDC_sar_sarhal_isr_register(OS_DEVICE *os_dev, int(*hal_isr)(HAL_DEVICE *, int *), int interrupt_num) { DDC_atm_sarhal_isr_register(os_dev, hal_isr, interrupt_num); } #endif /************************************************************ NEED FN HEADER ************************************************************/ #ifdef AR7_SAR static void DDC_sar_isr_unregister(OS_DEVICE *os_dev, int interrupt_num) { /* TODO */ } #endif /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * Function: void DDC_atm_get_chipsetId(char *pVerId) * * Description: Detect whether Dsp frequency should be boosted or not * * Input: char * buffer to populate with chipset ID string * max 31 characters * Output: none * Return: none * *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ void DDC_atm_get_chipsetId (char *pVerId) { #ifndef YAMUNA unsigned int reg_DIDR2; unsigned int chip_id; unsigned int TrimRegVal; /* * get chipset hw info */ chip_id = (DSLHAL_REG32 (REG_CVR)) & 0xFFFF; reg_DIDR2 = DSLHAL_REG32 (REG_DIDR2); switch (chip_id) { case CHIP_AR7: /* 7300, 7300A or 7300C */ if (!(reg_DIDR2 & BIT23)) DDA_sprintf(pVerId, "7300/7300A"); else DDA_sprintf(pVerId, "7300C"); break; case CHIP_AR7O_212: /* Ohio212 */ DDA_sprintf(pVerId, "Ohio212"); break; case CHIP_AR7O_250_212: /* Ohio250 or Ohio212(new) */ /* * Check Buck Trim bit see if it's Ohio250 or Ohio 212 */ TrimRegVal = (DSLHAL_REG32 (REG_BUCKTRIM_READ) >> 8) & 0x07; if (TrimRegVal == 0x07) { DDA_sprintf(pVerId, "Ohio250(7200/7100A2)"); } else { if (TrimRegVal==0x06) DDA_sprintf(pVerId, "Ohio250(7100A1)"); else DDA_sprintf(pVerId, "Ohio212(7100Trim=%01d)", TrimRegVal); } break; default: DDA_sprintf(pVerId, "Unknown"); break; } /* switch */ #else DDA_sprintf(pVerId, "UR8"); #endif return; } /************************************************************ NEED FN HEADER ************************************************************/ //AV:Temporary hack #ifndef pRX_CPPI_COMP_PTR #define pRX_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8048)) #define RX_CPPI_COMP_PTR(base) (*pRX_CPPI_COMP_PTR(base)) #define TEARDOWN_VAL 0xfffffffc #define pTXH_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8040)) #define TXH_CPPI_COMP_PTR(base) (*pTXH_CPPI_COMP_PTR(base)) #define pTXL_CPPI_COMP_PTR(base) ((volatile bit32u *)(base+0x8044)) #define TXL_CPPI_COMP_PTR(base) (*pTXL_CPPI_COMP_PTR(base)) #endif #ifdef AR7_SAR int DDC_sar_deactivate_vc(DDC_DslPriv *priv, int chan) { unsigned int mode; HAL_FUNCTIONS *pHalFunc; HAL_DEVICE *pHalDev; int rc; dgprintf(4, "DDC_sar_deactivate_vc\n"); //DDA_printf("DDC_sar_deactivate_vc entered\n"); pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc; pHalDev = (HAL_DEVICE *)priv->pSarHalDev; //AV: testing for disabling interrupts. //mode = 0xf; //tear down everything, wait for return; mode = (0xf & ~0x8); //tear down everything, don't wait for return; //AV_DDM DDA_critical_on(); rc = pHalFunc->ChannelTeardown(pHalDev, chan, mode); #if 0 //AV:Wait for the interrupt to happen. while (((*(pRX_CPPI_COMP_PTR( pHalDev->dev_base )+( chan *64))) & TEARDOWN_VAL) != TEARDOWN_VAL) { RxTeardownInt(HalDev->dev_base, chan); //Assuming that both are set at the same time TxTeardownInt(HalDev->dev_base, chan, 0); TxTeardownInt(HalDev->dev_base, chan, 1); } #endif //AV_DDM DDA_critical_off(); DDA_printf("ChannelTeardown returned rc = %d\n", rc); //return rc; return 0; } #endif #ifdef UR8_SAR int DDC_sar_deactivate_vc(DDC_DslPriv *priv, int chan) { int rc_tx, rc_rx; dgprintf(4, "DDC_sar_deactivate_vc\n"); //AV_DDM //DDA_critical_on(); DDA_printf("%s: calling rx close \n", __FUNCTION__); rc_rx = DDC_cpsarChClose(priv->SarDev, chan, DDC_NET_CH_DIR_RX, NULL); DDA_printf("%s: calling tx close \n", __FUNCTION__); rc_tx = DDC_cpsarChClose(priv->SarDev, chan, DDC_NET_CH_DIR_TX, NULL); //AV_DDM //DDA_critical_off(); DDA_printf("%s: rc_rx = %#x rc_tx = %#x \n", __FUNCTION__, rc_rx, rc_tx); //return rc; return 0; } #endif /************************************************************ NEED FN HEADER ************************************************************/ int DDC_sar_activate_vc (DDC_atm_activate_vc_parm_t * DDC_atm_activate_vc_parm_p) { #ifdef AR7_SAR CHANNEL_INFO chInfo; HAL_FUNCTIONS *pHalFunc; HAL_DEVICE *pHalDev; int rc; dgprintf (4, "DDC_sar_activate_vc\n"); pHalFunc = (HAL_FUNCTIONS *) DDC_atm_activate_vc_parm_p->priv->pSarHalFunc; pHalDev = (HAL_DEVICE *) DDC_atm_activate_vc_parm_p->priv->pSarHalDev; DDA_memset (&chInfo, 0xff, sizeof (chInfo)); /* * channel specific */ chInfo.Channel = DDC_atm_activate_vc_parm_p->chan; chInfo.Direction = 0; chInfo.Vci = DDC_atm_activate_vc_parm_p->vci; chInfo.Vpi = DDC_atm_activate_vc_parm_p->vpi; chInfo.TxVc_QosType = DDC_atm_activate_vc_parm_p->qos; chInfo.Priority = DDC_atm_activate_vc_parm_p->priority; /* * SR 1-4426141: The mask is now being defaulted for all QoS modes. This * fixes the cell spacing violation at low rates. */ chInfo.DaMask = 1; chInfo.TxVc_Mbs = DDC_atm_activate_vc_parm_p->mbs; /* use pcr as MBS */ /* Added Check for params */ if((DDC_atm_activate_vc_parm_p->scr == 0) || (DDC_atm_activate_vc_parm_p->pcr == 0)) { if(DDC_atm_activate_vc_parm_p->qos == 2) { dgprintf (1, "%s: scr or pcr = 0.\n", __FUNCTION__); DDC_atm_activate_vc_parm_p->scr = 1; DDC_atm_activate_vc_parm_p->pcr = 1; } else { DDA_printf("s: Failed incorrect param. Got pcr = %d and scr = %d \n", __FUNCTION__, DDC_atm_activate_vc_parm_p->scr, DDC_atm_activate_vc_parm_p->pcr); return -1; } } chInfo.TxVc_CellRate = DDC_atm_activate_vc_parm_p->priv->sar_freq / (DDC_atm_activate_vc_parm_p->scr); chInfo.TxVc_Pcr = DDC_atm_activate_vc_parm_p->priv->sar_freq / (DDC_atm_activate_vc_parm_p->pcr); /* * default */ chInfo.PktType = PACKET_TYPE_AAL5; /* @change to make it configurable 05/15/2004 */ chInfo.TxServiceMax = DDC_atm_activate_vc_parm_p->priv->sarTxMax; /* @change to make it configurable 05/15/2004 */ chInfo.RxServiceMax = DDC_atm_activate_vc_parm_p->priv->sarRxMax; chInfo.TxNumQueues = TX_QUEUE_NUM; if (DDC_atm_activate_vc_parm_p->vpi == REMOTE_MGMT_VPI && DDC_atm_activate_vc_parm_p->vci == REMOTE_MGMT_VCI) { chInfo.TxNumBuffers = 4; chInfo.RxNumBuffers = 4; chInfo.RxBufSize = MAX_CLEAR_EOC_BUF_SIZE; } else { /* @change to make it configurable 05/15/2004 */ chInfo.TxNumBuffers = DDC_atm_activate_vc_parm_p->priv->sarTxBuf; /* @change to make it configurable 05/15/2004 */ chInfo.RxNumBuffers = DDC_atm_activate_vc_parm_p->priv->sarRxBuf; chInfo.RxBufSize = RX_BUFFER_SIZE; } chInfo.RxVc_OamToHost = 0; chInfo.RxVp_OamToHost = 0; /* Cleaned up two unnecessary function calls. */ chInfo.TxVc_AtmHeader = DDC_sar_atm_header (DDC_atm_activate_vc_parm_p->vpi, DDC_atm_activate_vc_parm_p->vci); chInfo.RxVc_AtmHeader = chInfo.TxVc_AtmHeader; chInfo.TxVp_AtmHeader = DDC_sar_atm_header (DDC_atm_activate_vc_parm_p->vpi, 0); chInfo.RxVp_AtmHeader = chInfo.TxVp_AtmHeader; chInfo.CpcsUU = 0; dgprintf (4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader); rc = pHalFunc->ChannelSetup(pHalDev, &chInfo, DDC_atm_activate_vc_parm_p->priv->lut[DDC_atm_activate_vc_parm_p->chan].vcc); if (rc) { DDA_printf ("failed to setup channel =%d with return code %d \n", DDC_atm_activate_vc_parm_p->chan, rc); return -1; } #endif /* AR7_SAR */ #ifdef UR8_SAR CpsarChInfo chInfo; DDC_CpsarDevice *SarDev = DDC_atm_activate_vc_parm_p->priv->SarDev; int rc; int Qnum = CH_CONFIG( DDC_atm_activate_vc_parm_p->rq_num, DDC_atm_activate_vc_parm_p->tq_num, DDC_atm_activate_vc_parm_p->priv->bCppiErrProc); dgprintf (4, "DDC_sar_activate_vc\n"); DDA_memset (&chInfo, 0, sizeof (chInfo)); /* * channel specific */ chInfo.chNum = DDC_atm_activate_vc_parm_p->chan; chInfo.chDir = DDC_NET_CH_DIR_BIDIRECTIONAL; chInfo.TxVc_QosType = DDC_atm_activate_vc_parm_p->qos; chInfo.Priority = DDC_atm_activate_vc_parm_p->priority; chInfo.chState = 0; /* * SR 1-4426141: The mask is now being defaulted for all QoS modes. This * fixes the cell spacing violation at low rates. */ chInfo.DaMask = 1; chInfo.TxVc_Mbs = DDC_atm_activate_vc_parm_p->mbs; /* use pcr as MBS */ /* Added Check for params */ if((DDC_atm_activate_vc_parm_p->scr == 0) || (DDC_atm_activate_vc_parm_p->pcr == 0)) { if(DDC_atm_activate_vc_parm_p->qos == 2) { dgprintf (1, "%s: scr or pcr = 0.\n", __FUNCTION__); DDC_atm_activate_vc_parm_p->scr = 1; DDC_atm_activate_vc_parm_p->pcr = 1; } else { DDA_printf("s: Failed incorrect param. Got pcr = %d and scr = %d \n", __FUNCTION__, DDC_atm_activate_vc_parm_p->scr, DDC_atm_activate_vc_parm_p->pcr); return -1; } } chInfo.TxVc_CellRate = DDC_atm_activate_vc_parm_p->priv->sar_freq / (DDC_atm_activate_vc_parm_p->scr); chInfo.TxVc_Pcr = DDC_atm_activate_vc_parm_p->priv->sar_freq / (DDC_atm_activate_vc_parm_p->pcr); /* * default */ chInfo.PktType = PKT_TYPE_AAL5; /* @change to make it configurable 05/15/2004 */ chInfo.TxServiceMax = DDC_atm_activate_vc_parm_p->priv->sarTxMax; /* @change to make it configurable 05/15/2004 */ chInfo.RxServiceMax = DDC_atm_activate_vc_parm_p->priv->sarRxMax; //chInfo.TxNumQueues = TX_QUEUE_NUM; chInfo.numTxBD = DDC_atm_activate_vc_parm_p->priv->sarTxBuf; if (DDC_atm_activate_vc_parm_p->vpi == REMOTE_MGMT_VPI && DDC_atm_activate_vc_parm_p->vci == REMOTE_MGMT_VCI) { chInfo.TxNumBuffers = 4; chInfo.RxNumBuffers = 4; //chInfo.RxBufSize = MAX_CLEAR_EOC_BUF_SIZE; chInfo.RxBufSize = RX_BUFFER_SIZE; //In UR8 All the buffers in the same pool have to use the //same buffer size. } else { /* @change to make it configurable 05/15/2004 */ chInfo.TxNumBuffers = DDC_atm_activate_vc_parm_p->priv->sarTxBuf; /* @change to make it configurable 05/15/2004 */ chInfo.RxNumBuffers = DDC_atm_activate_vc_parm_p->priv->sarRxBuf; chInfo.RxBufSize = RX_BUFFER_SIZE; } chInfo.RxVc_OamToHost = 0; chInfo.RxVp_OamToHost = 0; /* Cleaned up two unnecessary function calls. */ chInfo.AtmHeader = DDC_sar_atm_header (DDC_atm_activate_vc_parm_p->vpi, DDC_atm_activate_vc_parm_p->vci); chInfo.CpcsUU = 0; //dgprintf (4, "TxVc_AtmHeader=0x%x\n", chInfo.TxVc_AtmHeader); chInfo.chDir = DDC_NET_CH_DIR_RX; rc = DDC_cpsarChOpen(SarDev, &chInfo, Qnum); if (rc) { DDA_printf ("failed to setup RX channel =%d with return code %d \n", DDC_atm_activate_vc_parm_p->chan, rc); return -1; } chInfo.chDir = DDC_NET_CH_DIR_TX; rc = DDC_cpsarChOpen(SarDev, &chInfo, Qnum); if (rc) { DDA_printf ("failed to setup TX channel =%d with return code %d \n", DDC_atm_activate_vc_parm_p->chan, rc); return -1; } #endif /* UR8_SAR */ return 0; } /************************************************************ NEED FN HEADER ************************************************************/ static void DDC_sar_exit(DDC_DslPriv *priv) { #ifdef AR7_SAR HAL_FUNCTIONS *pHalFunc; HAL_DEVICE *pHalDev; dgprintf(4, "DDC_sar_exit()\n"); pHalFunc = (HAL_FUNCTIONS *)priv->pSarHalFunc; pHalDev = (HAL_DEVICE *)priv->pSarHalDev; DDC_sar_deactivate_vc(priv, RESERVED_OAM_CHANNEL);//15); de-activate oam channel pHalFunc->Close(pHalDev, 2); pHalFunc->Shutdown(pHalDev); DDA_free(priv->pSarOsFunc); #endif /* AR7_SAR */ #ifdef UR8_SAR DDC_CpsarDevice *SarDev = priv->SarDev; dgprintf(4, "DDC_sar_exit()\n"); //CZ disable PDSP SarDev->regs->Control = 0; DDC_sar_deactivate_vc(priv, RESERVED_OAM_CHANNEL);//15); de-activate oam channel DDC_cpsarDeleteInstance (SarDev, NULL); //AV_don't need to do this anymore. //DDA_free(priv->SarDev); #endif /* UR8_SAR */ } /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * Function: int avsar_exit(void) * * Description: Avalanche SAR exit function * *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ static void DDC_dsl_exit (DDC_DslPriv * priv) { //priv->bshutdown = 1; //stop_kthread(&overlay_thread); DDC_dsl_clear_eoc_close(priv); dslhal_api_dslShutdown(priv->pIhw); } /**************************************************** Need Fn Header. ****************************************************/ int DDC_dsl_Close(DDC_DslPriv **priv) { DDC_DslPriv *cpriv = *priv; cpriv->lConnected = 0; DDC_dsl_exit(cpriv); DDC_sar_exit(cpriv); DDA_free(cpriv); return 0; }