/** * \file ddc_ti_dsl.h * * \author Copyright (C) 2001-2007 Texas Instruments Incorporated. * * \brief This file contains DSL Driver Core (DDC) layer internal definitions. * * \date 14Feb07 EP Added change history, cleanup. * Added channel open configuration macro. */ #ifndef _DDC_INTERNAL_H_ #define _DDC_INTERNAL_H_ #include "ddc_dsl_api.h" #include "dsl_hal_api.h" #include "dsl_hal_support.h" #include "dsl_hal_csl.h" #include "ddc_dsl_callback.h" #define _SIZE_T_ #ifndef size_t #define size_t unsigned int #endif #ifdef AR7_SAR #define _CPHAL_AAL5 #define _CPHAL_SAR #define _CPHAL_HAL typedef void OS_PRIVATE; typedef void OS_DEVICE; typedef void OS_SENDINFO; typedef void OS_RECEIVEINFO; typedef void OS_SETUP; #include "cpswhal_cpsar.h" #endif /* AR7_SAR */ /*** atm ***/ #define TX_SERVICE_MAX 32 #define RX_SERVICE_MAX 32 #define TX_BUFFER_NUM 64 #define RX_BUFFER_NUM 64 #define TX_QUEUE_NUM 2 #define RX_BUFFER_SIZE 1582 #define STOP_EMPTY_BUFF 2 #define START_EMPTY_BUFF 3 #define OFFSETOF(s,m) (size_t)(unsigned long)&(((s *)0)->m) #define MAX_PVC_TABLE_ENTRY 16 // CZ. moved the below line to ddc_dsl_api.h //#define RESERVED_OAM_CHANNEL 15 /*** DSL ***/ /* For the changes for trainning modes using bit fields. Defaults are for backward compatibility. */ #define OLD_TRAINING_VAL_GDMT 3 #define OLD_TRAINING_VAL_T1413 2 #define OLD_TRAINING_VAL_MMODE 1 #define NEW_TRAINING_VAL_GDMT 2 #define NEW_TRAINING_VAL_T1413 128 #define NEW_TRAINING_VAL_MMODE 255 #ifndef TRUE #define TRUE 1 #endif #ifndef FALSE #define FALSE 0 #endif #define MAX_CLEAR_EOC_BUF_SIZE 600 #define host2dspAddrMapping(a) (((int)a)&~0xe0000000) /** \brief Chip-dependent interrupt source number */ #define ATM_DSL_INT_SANGAM 39 /** for Sangam */ #define ATM_DSL_INT_OHIO 23 /** for Ohio */ #define ATM_DSL_INT_YAMUNA 28 /** for Yamuna */ #define SANGAM_DEFAULT_IPACEMAX_VAL 3 #define OHIO_DEFAULT_IPACEMAX_VAL 4 #define YAMUNA_DEFAULT_IPACEMAX_VAL 6 #define ANNEX_M_2PLUS_PACEMAX_VAL 6 /* PDSP OAM General Purpose Registers (@todo: These need to be used in the HAL!) */ #define SAR_PDSP_HOST_OAM_CONFIG_REG_ADDR 0xa3000020 #define SAR_PDSP_OAM_CORR_REG_ADDR 0xa3000024 #define SAR_PDSP_OAM_LB_RESULT_REG_ADDR 0xa3000028 #define SAR_PDSP_OAM_F5LB_COUNT_REG_ADDR 0xa300002c #define SAR_PDSP_OAM_F4LB_COUNT_REG_ADDR 0xa3000030 /* *INDENT-OFF* */ /* Old values for backward compatibility. To be removed for UR8 */ #define NO_MODE 0 #define MULTI_MODE 1 #define T1413_MODE 2 #define GDMT_MODE 3 #define GLITE_MODE 4 #define ADSL2_MODE 8 #define ADSL2_DELT 9 #define ADSL2_PLUS 0x10 #define ADSL2_PLUS_DELT 0x11 #define READSL_MODE 0x20 #define READSL_PLUS_DELT 0x21 #define ADSL2_ANNEX_I 0x100 //Not supported yet #define ADSL2_ANNEX_J 0x200 //Not supported yet #define ADSL2_ANNEX_M 0x400 #define ADSL2_PLUS_ANNEX_I 0x800 //Not supported yet #define ADSL2_PLUS_ANNEX_J 0x1000 //Not supported yet #define ADSL2_PLUS_ANNEX_M 0x2000 /* *INDENT-ON* */ #define DDC_DSL_ADSL2_MASKS (ADSL2_MODE | ADSL2_ANNEX_I | ADSL2_ANNEX_J | ADSL2_ANNEX_M) #define DDC_DSL_ADSL2PLUS_MASKS (ADSL2_PLUS | ADSL2_PLUS_ANNEX_I | ADSL2_PLUS_ANNEX_J | ADSL2_PLUS_ANNEX_M) /*** Data structures ***/ #ifdef AR7_SAR typedef enum { PACKET_TYPE_AAL5, PACKET_TYPE_NULL, PACKET_TYPE_OAM, PACKET_TYPE_TRANS, PACKET_TYPE_AAL2 }PACKET_TYPE; #endif /* AR7_SAR */ #ifdef UR8_SAR #define PKT_TYPE_AAL5 0 #define PKT_TYPE_NULL 1 #define PKT_TYPE_OAM 2 #define PKT_TYPE_TRANS 3 #define PKT_TYPE_EFM 4 #define PKT_TYPE_ETH 7 #define PKT_TYPE_GEN 6 #endif /* UR8_SAR */ /** * \brief DSL SAR statistics */ typedef struct _sar_stat { unsigned int txErrors; /**< TBD */ unsigned int rxErrors; /**< TBD */ unsigned int rxPktCnt; /**< TBD */ unsigned int txPktCnt; /**< TBD */ unsigned int rxBytes; /**< TBD */ unsigned int txBytes; /**< TBD */ } sar_stat_t; typedef enum { OAM_PING_FAILED, OAM_PING_SUCCESS, OAM_PING_PENDING, OAM_PING_NOT_STARTED, OAM_PING_PENDING_RECVD //Add internal state for the unmatched oam ping result } OAM_PING; extern DDC_sar_stat sarStat; extern int oamLbTimeout; #define RX_Q_SHIFT 0 #define TX_Q_SHIFT 8 #define ERR_PROC_SHIFT 16 #define CH_CONFIG(r, t, e) (((r)<<0) | ((t)<<8) | (((e)?1:0)<<16)) /*** Prototype ***/ /* Proc API functions */ int DDC_atm_proc_version (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_atm_proc_channels (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_sar_proc_sar_stat (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_sar_proc_oam_ping (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_sar_proc_pvc_table (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_snr0 (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_snr1 (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_snr2 (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_eoc (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_bit_allocation(char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_train_mode_export(char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_SNRpsds (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_QLNpsds (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_modem (char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_stats (char* buf, int count,int *eof, DDC_DslPriv *priv); #ifdef ADV_DIAG_STATS //CQ10275 int DDC_dsl_proc_adv_stats1(char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_adv_stats2(char* buf, int count,int *eof, DDC_DslPriv *priv); int DDC_dsl_proc_adv_stats3(char* buf, int count,int *eof, DDC_DslPriv *priv); #endif #endif /*_DDC_INTERNAL_H_*/