#ifndef __DEV_HOST_INTERFACE_H__ #define __DEV_HOST_INTERFACE_H__ 1 /******************************************************************************* * FILE PURPOSE: Public header file for the Host-to-DSP interface ******************************************************************************** * * TEXAS INSTRUMENTS PROPRIETARY INFORMATION * * (C) Copyright Texas Instruments Inc. 2002. All rights reserved. * * Property of Texas Instruments Incorporated * * Restricted Rights - Use, duplication, or disclosure is subject to * restrictions set forth in TI's program license agreement and * associated documentation * * * FILE NAME: dev_host_interface.h * * DESCRIPTION: * This header file defines the variables and parameters used between the * host processor and the DSP. This file is included in both the DSP * software and the host software. * * RULES FOR MODIFICATION AND USE OF THIS FILE: * * --The main pointer to the struct of pointers will always be at the same fixed * location (0x80000000). * * --Each pointer element in the struct of pointers (indicated by the main pointer) * will always point to a struct only. * * --Any new structures added to the host interface in subsequent versions must * each have a corresponding new pointer element added to the END of the struct * of pointers. Other than this, there will never be any moving or rearranging * of the pointer elements in the struct of pointers. * * --Any new elements added to existing structures will be added at the END of the * structure. Other than this, there will never be any moving or rearranging * of structure elements. * * --A new structure will never be added as a new element in an old structure. * New structures must be added separately with a new entry in the struct of * pointers, as noted above. * * --Also, the sizes of existing arrays within old structures will never be changed. * * --The modem code in the DSP will never reference the struct of pointers in order * to avoid aliasing issues in the DSP code. The modem code will only use the * specific structures directly. * * --The host processor never accesses the DSP side of the ATM-TC hardware directly. * The DSP interfaces directly to the ATM-TC hardware and relays information to * the host processor through the host interface. * * --The host processor can track the modem's transition through important states * by accessing the Modem State Bit Field in the host interface. Each bit in * the bit field represents an important state to track in the modem. As the * modem transitions through each important state, the corresponding bit will * change from a zero to a one. Each bit in the bit field will only be reset to * zero if the modem retrains. If new states need to be tracked and are added * in subsequent versions of the host interface, a corresponding bit will be * added at the END of the bit field to ensure backwards compatibility. The * Modem State Bit Field is reset if the modem retrains or falls out of Showtime. * * --An interrupt will be sent to the host processor when a change occurs in the * Modem State Bit Field. There is an interrupt masking register which can mask * specific interrupts corresponding to the bits of the Modem State Bit Field. * This allows the host to keep an interrupt from being generated for those * states that are masked. * * HISTORY: * * 11/20/02 J. Bergsagel Written from the previous host interface file * 11/27/02 J. Bergsagel Added comments for mailbox control struct and * fixed a couple items for overlay page stuff. * Also, added temporary elements for SWTC code. * 12/04/02 J. Bergsagel Added extra dummy byte to DEV_HOST_eocVarDef_t * for proper word alignment. * 12/12/02 J. Bergsagel Changed initial states in the modem state bit field * and added more instructions for adding more states. * 12/16/02 J. Bergsagel Changed name "hostVersion_p" to "hostIntfcVersion_p". * Removed dspAturState from DEV_HOST_modemStateBitField_t. * Reorganized several struct elements to clean up the * host interface. * 12/27/02 Sameer V Added missing channel 0 statistics for TC. Added * ocd error information. * 12/27/02 Sameer V Added overlayState to OlayDP_Parms to indicate whether * overlays are being executed in current state. * 01/06/03 J. Bergsagel Added maxAllowedMargin and minRequiredMargin to * DEV_HOST_msg_t. * Renamed TC chan 1 items to be chan 0 items to start out. * 01/17/03 Sameer V Moved delineationState to atmStats structure. * 01/21/03 Barnett Implemented Ax7 UNIT-MODULE modular software framework. * 01/22/03 J. Bergsagel Added warning comments for certain struct typedefs. * 01/23/03 C. Perez-N. Removed old AX5-only diags. command/response entries in the * HOST and DSP ennumerations, and added the AX7 new ones * Added pointer entries in the DEV_HOST_dspOamSharedInterface_t * structure pointing to the analog diags. input/output/options * structures. * 01/29/03 Sameer V Removed TC_IDLE in enum for delineation state. Hardware * only reports TC_HUNT, TC_PRESYNC and TC_SYNC. * 03/07/03 Sameer/Jonathan Put SWTC token around structs and elements only used by SWTC * 03/12/03 Mannering Add CO profile data structures * 03/18/03 J. Bergsagel Removed the obsolete DSP_CHECK_TC response message. * 03/24/03 J. Bergsagel Added DEV_HOST_hostInterruptMask_t for masking DSP interrupt sources * 03/28/03 C. Perez-N Changed the C-style comments and made them C++ sytle instead. * Replaced the occurrences of "SINT32 *" pointer declarations with * "PSINT32" * 03/28/03 Mannering Update CO profile data structures * 04/04/03 S. Yim Add host I/F hooks for switchable hybrid and RJ11 * inner/outer pair selection * 04/11/03 J. Bergsagel Changed modem state bit field struct types to enums instead and used * a single integer variable for each "bitfield". * Changed bit field for host interrupt masks to an integer value also. * 04/14/03 J. Bergsagel Changed name of table pointer "meanSquareTblDstrm_p" to "marginTblDstrm_p". * 04/03/03 Umesh Iyer CMsg1 and RMsg1 use the same storage as CMSGPCB and RMSGPCB. * The string lengths for these have been adjusted to hold the longest * message in each case. The PCB messages from ADSL2 are longer. * 04/21/03 Sameeer V Added new host mailbox message for shutting down the DSLSS peripherals. * 04/23/03 J. Bergsagel Fixed comments for overlay mailbox messages and for losErrors. * 04/28/03 Mannering Added skip phase op flag to CO profile data structure * 05/05/03 Mannering Review Comments - Removed "#if CO_PROFILE" from around structure * definitions and define the number of profiles (DEV_HOST_LIST_ENTRIES) * 05/13/03 J. Bergsagel Added new elements to DEV_HOST_phyPerf_t for host control of hybrid. * 05/15/03 J. Bergsagel Added "farEndLosErrors" and "farEndRdiErrors" to DEV_HOST_modemStatsDef_t. * 05/16/03 Mannering Updated CO profile structure to support updated bit allocation and * interopability. * 05/20/03 Sameer V Added DSP message to inicate DYING GASP. * 05/22/03 J. Bergsagel Added a new struct typedef "DEV_HOST_hostInterruptSource_t". * Added "atucGhsRevisionNum" to "DEV_HOST_dspWrNegoParaDef_t". * Moved the following struct typedef's here to the public host interface: * DEV_HOST_dspBitSwapDef_t * DEV_HOST_atmDsBert_t * 05/28/03 A. Redfern Changed pointer type and location for margin reporting. * 05/28/03 Mannering Moved CO profile defines to dev_host_interface_pvt.h * 05/28/03 J. Bergsagel Moved subStateIndex and STM BERT controls into new struct "DEV_HOST_modemEnvPublic_t" * 05/29/03 J. Bergsagel Added elements to "DEV_HOST_modemEnvPublic_t" for host control of DSLSS LED's. * 06/10/03 Umesh Iyer Modified trainMode check to be compliant with the new host i/f mods. * 06/05/03 J. Bergsagel Added enum that will eventually replace the bitfield: DEV_HOST_diagAnlgOptionsVar_t. * Added new element "currentHybridNumUsed" in the DEV_HOST_phyPerf_t typedef * Added new host control flags for LPR signal detection on GPIO[0]. * 06/06/03 A. Redfern Removed fine gain scale from the CO profile and added max downstream power cutback. * Changed "test1" in CO profile struct to "phyEcDelayAdjustment". * 06/26/03 J. Bergsagel Added genericStructure typedef and two pointer elements of this type in the big table. * 07/03/03 Jack Huang Renamed test2 to bSwapThresholdUpdate * 07/07/03 Mallesh Changed phySigTxPowerCutback_f flag to a variable phySigTxGainReductionAt0kft which indicates the * amount of gain reduction in linear scale. * 07/15/03 Sameer V Changed DEV_HOST_diagAnlgOptionsVar_t to be an enum instead of a bit field. Host code * does not support setting bit fields. * 07/22/03 Jack Huang Added bitswap control flag in host i/f for API calls * 08/06/03 Sameer V Added missingToneDs_p to the DEV_HOST_oamWrNegoParaDef_t to enable host to switch off * DS tones on specified bins * 08/21/03 Jack Huang Added pcbEnabled flag in the DEV_HOST_modemEnvPublic_t structure * Added g.hs buffer definitions to DEV_HOST_dspOamSharedInterface_t * Added DEV_HOST_consBufDef_t to the DEV_HOST_dspOamSharedInterface_t structure * 08/26/03 J. Bergsagel Fixed name of "missingToneDs_p" to be "missingToneDsAddr" instead (since it is * not really used as a pointer). * 09/11/03 Mallesh Added a flag "usPilotInT1413ModeInMedley" to determine the need to send Upstream Pilot * in medley in T1.413 mode. * 09/12/03 J. Bergsagel Changed "test3" to "phyBitaFastPathExcessFineGainBump" in CO profile struct. * Changed "test4" to "phyBitaSkipGapAdjustment" in CO profile struct. * 09/23/03 J. Bergsagel Changed "T1413vendorRevisionNumber" to "vendorRevisionNumber" in DEV_HOST_msg_t. * Added ADSL2 and ADSL2 diag. states to the modem state bit field. * 10/01/03 J. Bergsagel Changed define of "MULTI_MODE" to be 255 to indicate that all possible bits * in the 8-bit bit field are turned on for any current and future training modes. * 10/09/03 M. Turkboylari Added DSP_TRAINING_MSGS and adsl2DeltMsgs_p, which is a pointer to a pointer, * in order to pass the ADSL2 training and DELT messages to the host side. This is for ACT. * 10/20/03 Mallesh Added a GHS state enumerator for cleardown * 10/20/03 Xiaohui Li Add definition for READSL2_MODE and READSL2_DELT * 11/07/03 J. Bergsagel Removed all code for when SWTC==1, which therefore allows removal of include of * "env_def_defines.h". We shouldn't have any compile tokens used in this file. * (the SWTC token is always off in any Ax7 code). * 11/14/03 J. Bergsagel Also removed READSL2_ENABLE token (no more compile tokens to be used in this .h file). * 12/12/03 Sameer/Ram Added DEV_HOST_EOCAOC_INTERRUPT_MASK to enable host to disable response code for AOC/EOC * mailbox messages * 12/09/03 Jack Huang Changed G.hs txbuf size from 60 to 64 to fit the max segment size * 12/15/03 Mallesh Changed vendor ID type defenition from SINT16 to UINT16 * 12/23/03 Sameer V Added ability to turn off constellation display reporting to host using oamFeature bit field. * 12/24/03 Sameer V Changed comment for Constellation Display Current Address to Host Write instead of DSP Write. * 12/26/03 Sameer/Ram Added DEV_HOST_GHSMSG_INTERRUPT_MASK to enable host to disable response code for GHS Messages * 02/03/04 Mannering Added token OHIO_SUPPORT * 02/24/04 Mannering Fixed comments on devCodecTxDf2aDen and devCodecTxDf2bDen. * 03/08/04 Mallesh Increased the number of overlay pages to 7. * 04/01/04 Sameer Increased the number of overlay pages to 8. * 04/12/04 Sameer Moved TXDF2B filter coeffs to SDRAM memory. Added mechanism to DMA data back to data memory * based on the pointer allocated by the host processor. * 04/15/04 Umesh Iyer Added support for including 2 additional overlay pages for training. * 04/20/04 U G Jani Reused dummy2 for EOC selfTestResults results in DEV_HOST_eocVarDef_t typedef. * 05/14/04 Mallesh Added structures for ADSL2 bitswaps * 06/11/04 Brian Z. & C. Added structures for clear EOC HDLC host Rx and Tx buffers * 07/09/04 Jack Huang Added MSE settle time control in CO profile * 07/22/04 SV/MH/SM Added variable to indicate rcvMode. * 08/09/04 Jack Huang Added following control variables in CO profile a) thresholf for ratio of max/min MSE and * b) threshold of max MSE power. * 08/25/04 Sameer V Added flag to indicate whether DSP runs at 200 v/s 250 Mhz. * 08/26/04 Brian Z/S.Yim Added DEV_HOST_diagAnlgOutputVar_t.rcvMode for Matlab offline data process * 10/06/04 Sameer V Added structure for feature control * 03/17/05 T. Leyrer Replaced reserved1 with maxbits_ds in structure DEV_HOST_msg_t. maxbits_ds is set to the * minimum between host and CO setting and used for bit allocation and bitswap. * 12/28/04 DW CQ 9356: Modified definitions of phy feature control and enable bits. * Added interop control and enable bits. Added bit mask definitions. * 02/09/05 YH CQ9459: add interop control and enable bits for SHORT_LOOP_US_ERR_REDUCTION. * this is for fixing interop issue at CANTV * 02/23/05 YH added interop bit for QWEST_ALCATEL_US_LOW_RATE_FIX * added interop bit for T1413_LONG_LOOP_ACTIVATION added interop bit for QWEST_ALCATEL_US_LOW_RATE_FIX added interop bit for ASB_ETSIB_HIGH_BER_FIX added interop bit for BELL_CANADA_DOUBLE_BRIDGE_TAP_FIX added interop bit for BELGACOM_DS_FIX added interop bit for CINCINNATI_BELL_FIX added interop bit for FRANCE_TELECOM_FIX * 03/31/05 Ragu Pappu added interop bit for QWEST_US_1M_RATE_FIX * 05/20/05 Kapil Added fields corresponding to AnnexB and AnnexM. * Added two extra elements in DEV_HOST_dspWrNegoParaDef_t * structure and one extra element in DEV_HOST_oamWrNegoParaDef_t * structure. CQ9600. * 05/20/05 Venkat R CQ9600: Added bit field definitions for DEV_HOST_dspWrNegoParaDef_t * psd_mask_qualifier field * 06/14/05 Peter Hou Added MULTI_MODE8 for backward compatibility * Added ADSL2_MASKS & ADSL2PLUS_MASKS * 07/06/05 Peter Hou Added ENABLE_BELGACOM_ANXB_FAST_TRAINING as IOP Bit12 * 07/11/05 Kapil CQ9600: Cleaned up usage of READSL as per new definitions of * trainMode. * 07/21/05 Kapil CQ9600: Increase MAX_CMSGPCB2_LENGTH to ensure proper word alignment * and also to take care of DELT. * 07/21/05 Venkat R CQ9600: Expanded some array sizes in DEV_HOST_olrDspRxDef_t to support * 64 upstream bins. * 05/03/05 Hanyu Liu CQ9500: added interop control and disable bits for SAFEMODE_FOR_G992_3_5 * 05/16/05 Madhu Hegde CQ 9620. Added interop bit for ADI_UPSTREAM_RATES_FIX. * When this bit is enabled, the quantization noise added to * R-MEDLEY is reduced to get higher US data rates. * 07/13/05 C. Urrutia Added interop bit for ENABLE_OHIO_HYBRID4_REWIRE. * When this bit is enabled hybrid 4 becomes part of the tx path * 07/12/05 Shanti K CQ9528 : Modified data structure DEV_HOST_modemEnvPublic_t * 07/18/05 C. Urrutia CQ9787 : Added interop bit for WESTELL_RFI_OPTION * 08/31/05 Peter Hou CQ9613 : Remove/recycle bit12, ENABLE_OHIO_HYBRID4_REWIRE, * changed to ENABLE_NOKIA_D50_GDMT_RETRAIN_FIX * 10/31/05 Ram CQ10012: Added interop bit for REPORT_AVG_MARGIN; reused Bit14 * Deleted unused bit for Belgacom Fast AnnexB training. * 11/03/05 Manjula K CQ10037:Added Inventory command support for ADSL2/2+ * 10/25/05 Ragu Pappu CQ10004. Added API control bit to disable extended* * framing support. * 1/4/06 Peter Hou CQ5885, fixed ADSL2\2+ clearEoc CNXT IoP, added DISABLE_CNXT_CLREOC_PATCH. * 01/18/06 Hanyu Liu CQ10173: Added API bit17, ENABLE_TELEFONICA_FIXED_MARGIN * 11/08/05 Peter Hou Add DEV_HOST_BIS_MGMTCount_t in DEV_HOST_dspOamSharedInterface_t * 01/27/06 Raghu M CQ10045 Added API bit support for INP maximization * 01/25/06 Madhu H CQ10198: Added API bit to extend Annex B US to bin 28 * and delay minimization. * 01/18/06 E Yin CQ10222: Add API control bit to disable extended INP paramter in Ghs. * 02/08/06 Wal/Ley/Peter CQ10242: Added Cli2Linux buffer interface for CLI * redirection to Linux * 02/09/06 Kapil Gulati CQ10222: The API control bits for extended framing and INP>2 were * not compliant with our traditional way of defining these bits. * Hence fixed that issue. * 02/14/06 Kapil Gulati CQ10222: During SQI testing it was found that LS FS+ DSLAM does not * handle INP>2 G.hs message correctly. Hence it was decided to disable * this feature by default. * 03/29/06 E. Peng Added Band Plan definition for VDSL. * 04/21/06 E Yin CQ10483: Add bit define for VDSL2 mode. This is only temp. we still * need to close loop with Earl. * 07/03/06 Mike Locke CQ10770: Extended DEV_HOST_errorStats_t to reflect recommendation requirements * * 06/26/06 Geeta CQ10769: Modified DEV_HOST_coData_t. Added rxfilt_t and txfilt_t. * Added #define TXDF1_COEFFLEN * 08/25/06 Brian Lai CQ100780: Include new overlay definitions from ctrl_olay_swif.h * 10/31/06 Dragan L CQ10809: Include phy_hyb.h and modify the size of hybrid cost array * 10/12/06 Brian Lai CQ11058: Removed overlay reference from dev_host_interface * 10/31/06 E. Peng Fixed Host Interface alignment to be compatible with previous builds. * 11/07/06 E. Peng Removed include file and fixed alignment. * 11/16/06 EYin Add ch1 support for dual channel in BIS_MGMT_CountersDef_t; // UR8_MERGE_START API-Bits PeterHou * 04/03/06 PeterHou/KapilG CQ10375: Added ENABLE_PHY_INP_DSCRC_IMPROVEMENT API bit * PeterHou/HanyuL CQ10385: Added ENABLE_DETECT_MORE_COMB1TONES API bit * PeterHou/TimB CQ10351: Added ENABLE_PHY_SRA_SUPPORT API bit // UR8_MERGE_END API-Bits PeterHou // UR8_MERGE_START CQ10448 Ram * 04/04/06 Ram CQ10448: Combined two reserved byte fields into one SINT16 in atur_msg * structure as attNdrBits field to compute DS Max Attainable NDR * Removed trailing comma from IOP and PHY Feature Bit Structures // UR8_MERGE_END CQ10448 Ram //UR8_MERGE_START_END CQ10758 Tim * 07/11/06 Tim Bornemisza CQ10758: Updated DEV_HOST_olrDspRxDef_t structure for US SRA // UR8_MERGE_START_END CQ10774 Ram * UR8_MERGE_START CQ11194 HZ * 12/05/06 Hao Zhou CQ11194: Modify the estimation of attainable DS data rate. * Add a variable 'raOVRate' in the structure 'DSPWrNegoPara' in this file. * UR8_MERGE_END CQ11194 HZ * UR8_MERGE_START CQ10978 Jack Zhang * 10/4/06 JZ CQ10978: Request for the DSL Power Management Status Report * UR8_MERGE_END CQ10978* * UR8_MERGE_START CQ10979 Jack Zhang * 10/4/06 JZ CQ10979: Request for TR-069 Support for RP7.1 * UR8_MERGE_END CQ10979* * UR8_MERGE_START CQ10880 Jack Zhang * 8/30/06 JZ CQ10880: Add DSL HAL API for sending mailbox message for L3 * UR8_MERGE_END CQ10880* * 01/17/06 Venkat R CQ11354: Merged dsMargin changed in eocvar to SINT16 * Fix Alignment of annex_selected * 01/23/07 Brian Lai CQ11344: Ported cabinet mode from AR7 * (C) Copyright Texas Instruments Inc. 2002. All rights reserved. *******************************************************************************/ #include "dev_host_verdef.h" // DW 12/28/04 Bit mask definitions, intended for general use #define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004 #define BIT3 0x00000008 #define BIT4 0x00000010 #define BIT5 0x00000020 #define BIT6 0x00000040 #define BIT7 0x00000080 #define BIT8 0x00000100 #define BIT9 0x00000200 #define BIT10 0x00000400 #define BIT11 0x00000800 #define BIT12 0x00001000 #define BIT13 0x00002000 #define BIT14 0x00004000 #define BIT15 0x00008000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 // --------------------------------------------------------------------------------- // Address of the pointer to the DEV_HOST_dspOamSharedInterface_s struct of pointers // This is where it all starts. // --------------------------------------------------------------------------------- #define DEV_HOST_DSP_OAM_POINTER_LOCATION 0x80000000 // The define "MAX_NUM_UPBINS" is used in "DEV_HOST_diagAnlgInputVar_t" below. // This value can never be changed (for host intf. backwards compatibility) #define MAX_NUM_UPBINS 64 // ----------------------------------------------- // Begin common enumerations between DSP and host. // ----------------------------------------------- // These Host-to-DSP commands are organized into two groups: // immediate state change commands and status affecting commands. // Do not add or remove commands except at the bottom since the DSP assumes this sequence. enum { HOST_ACTREQ, // Send R-ACKREQ and monitor for C-ACKx HOST_QUIET, // Sit quietly doing nothing for about 60 seconds, DEFAULT STATE; R_IDLE HOST_XMITBITSWAP, // Perform upstream bitswap - FOR INTERNAL USE ONLY HOST_RCVBITSWAP, // Perform downstream bitswap - FOR INTERNAL USE ONLY HOST_RTDLPKT, // Send a remote download packet - FOR INTERNAL USE ONLY HOST_CHANGELED, // Read the LED settings and change accordingly HOST_IDLE, // Sit quiet HOST_REVERBTEST, // Generate REVERB for manufacturing test HOST_CAGCTEST, // Set coarse receive gain for manufacturing test HOST_DGASP, // send Dying Gasp messages through EOC channel HOST_GHSREQ, // G.hs - FOR INTERNAL USE ONLY HOST_GHSMSG, // G.hs - FOR INTERNAL USE ONLY HOST_GHS_SENDGALF, // G.hs - FOR INTERNAL USE ONLY HOST_GHSEXIT, // G.hs - FOR INTERNAL USE ONLY HOST_GHSMSG1, // G.hs - FOR INTERNAL USE ONLY HOST_HYBRID, // Enable/Disable automatic hybrid switch HOST_RJ11SELECT, // RJ11 inner/outer pair select HOST_DIGITAL_MEM, // Digital Diags: run external memory tests HOST_TXREVERB, // AFE Diags: TX path Reverb HOST_TXMEDLEY, // AFE Diags: TX path Medley HOST_RXNOISEPOWER, // AFE Diags: RX noise power HOST_ECPOWER, // AFE Diags: RX eco power HOST_ALL_ADIAG, // AFE Diags: all major analog diagnostic modes. Host is responsible to initiate each diagnostic sessions HOST_USER_ADIAG, // AFE Diags: Host fills in analog diagnostic input data structure as specified and requests DSP to perform measurements as specified HOST_QUIT_ADIAG, // AFE Diags: Host requests DSP to quit current diagnostic session. This is used for stopping the transmit REVERB/MEDLEY HOST_NO_CMD, // All others - G.hs - FOR INTERNAL USE ONLY HOST_DSLSS_SHUTDOWN, // Host initiated DSLSS shutdown message HOST_SET_GENERIC, // Set generic CO profile HOST_UNDO_GENERIC, // Set profile previous to Generic HOST_GHS_CLEARDOWN, // G.hs - FOR INTERNAL USE ONLY to start cleardown // * UR8_MERGE_START CQ10880 Jack Zhang HOST_L3_MSG // Send a message to DSP to switch to request CO for a transition to L3 mode // * UR8_MERGE_END CQ10880* }; // These DSP-to-Host responses are organized into two groups: // responses to commands and requests for OAM services. enum { DSP_IDLE, // R_IDLE state entered DSP_ACTMON, // R_ACTMON state entered DSP_TRAIN, // R_TRAIN state entered DSP_ACTIVE, // R_ACTIVE state entered DSP_XMITBITSWAP, // Upstream bitswap complete - FOR INTERNAL USE ONLY DSP_RCVBITSWAP, // Downstream bitswap complete - FOR INTERNAL USE ONLY DSP_RTDL, // R_RTDL state entered - FOR INTERNAL USE ONLY DSP_RRTDLPKT, // RTDL packet received - FOR INTERNAL USE ONLY DSP_XRTDLPKT, // RTDL packet transmitted - FOR INTERNAL USE ONLY DSP_ERROR, // Command rejected, wrong state for this command DSP_REVERBTEST, // Manufacturing REVERB test mode entered DSP_CAGCTEST, // Manufacturing receive gain test done DSP_OVERLAY_START, // Notify host that page overlay has started - overlay number indicated by "tag" DSP_OVERLAY_END, // Notify host that page overlay has ended - overlay number indicated by "tag" DSP_CRATES1, // CRATES1 message is valid and should be copied to host memory now DSP_SNR, // SNR calculations are ready and should be copied to host memory now DSP_GHSMSG, // G.hs - FOR INTERNAL USE ONLY DSP_RCVBITSWAP_TIMEOUT, // Acknowledge Message was not received within ~500 msec (26 Superframes). DSP_ATM_TC_SYNC, // Indicates true TC sync on both the upstream and downstream. Phy layer ready for data xfer. DSP_ATM_NO_TC_SYNC, // Indicates loss of sync on phy layer on either US or DS. DSP_HYBRID, // DSP completed hybrid switch DSP_RJ11SELECT, // DSP completed RJ11 inner/outer pair select DSP_INVALID_CMD, // Manufacturing (Digital and AFE) diags: CMD received not recognized DSP_TEST_PASSED, // Manufacturing diags: test passed DSP_TEST_FAILED, // Manufacturing diags: test failed DSP_TXREVERB, // Manufacturing AFE diags: Response to HOST_TXREVERB DSP_TXMEDLEY, // Manufacturing AFE diags: Response to HOST_TXMEDLEY DSP_RXNOISEPOWER, // Manufacturing AFE diags: Response to HOST_RXNOISEPOWER DSP_ECPOWER, // Manufacturing AFE diags: Response to HOST_ECPOWER DSP_ALL_ADIAG, // Manufacturing AFE diags: Response to HOST_ALL_ADIAG DSP_USER_ADIAG, // Manufacturing AFE diags: Response to HOST_USER_ADIAG DSP_QUIT_ADIAG, // Manufacturing AFE diags: Response to HOST_QUIT_ADIAG DSP_DGASP, // DSP Message to indicate dying gasp DSP_EOC, // DSP Message to indicate that DSP sent an EOC message to CO DSP_TRAINING_MSGS, // DSP Message to indicate that host has to copy the training message specified in the tag field. DSP_CLEAR_EOC, // DSP Message to indicate that the Rx buffer is full and ready for host to reead DSP_LOF // DSP Message to indicate an LOF alarm is being set or cleared }; // Definitions used to indicate which modes are allowed by HAL. The datapump looks at // these to determine the contents of transmitted handshake messages and to figure out // what are the allowed modes in which the modem can potentially train up. // Note that at this time ANNEX I and J are not supported and these bits are // effectively ignored. #define NO_MODE 0x0000 #define DELT_ENABLE 0x0001 #define GDMT_ANNEX_A_OR_B 0x0002 #define GLITE_ANNEX_A_AND_B 0x0004 #define ADSL2_ANNEX_A_OR_B 0x0008 #define ADSL2PLUS_ANNEX_A_OR_B 0x0010 #define ADSL2_ANNEX_L 0x0020 #define T1413_ANSI 0x0080 #define ADSL2_ANNEX_I 0x0100 #define ADSL2_ANNEX_J 0x0200 #define ADSL2_ANNEX_M 0x0400 #define ADSL2PLUS_ANNEX_I 0x0800 #define ADSL2PLUS_ANNEX_J 0x1000 #define ADSL2PLUS_ANNEX_M 0x2000 #define VDSL2 0x8000 // temporary for VDSL2 #define ADSL2_ANNEX_A_OR_B_DELT (ADSL2_ANNEX_A_OR_B + DELT_ENABLE) #define ADSL2PLUS_ANNEX_A_OR_B_DELT (ADSL2PLUS_ANNEX_A_OR_B + DELT_ENABLE) #define ADSL2_ANNEX_L_DELT (ADSL2_ANNEX_L + DELT_ENABLE) #define MULTI_MODE 0xffff #define MULTI_MODE8 0xff // 8 bit Multi_Mode for backward compatibility #define ADSL2_MASKS (ADSL2_ANNEX_A_OR_B | ADSL2_ANNEX_I | ADSL2_ANNEX_J | ADSL2_ANNEX_L | ADSL2_ANNEX_M) #define ADSL2PLUS_MASKS (ADSL2PLUS_ANNEX_A_OR_B | ADSL2PLUS_ANNEX_I | ADSL2PLUS_ANNEX_J | ADSL2PLUS_ANNEX_M) // Defintions used to indicate the standard in which the modem trained up. // Values for trainMode field of DEV_HOST_dspWrNegoParaDef_t - please note this refers to standard // used. Please be careful while changing this. Changing the bit definitions of this byte can // BREAK backward compatibility with HAL and ATM drivers versions earlier than D4.1 // Typically the bit field definitions for this field should be the same as Least Significant Byte of // DEV_HOST_oamWrNegoParaDef_t.stdMode // Please note that MULTI_MODE as defined in stdMode field of DEV_HOST_oamWrNegoParaDef_t is not // required as this field refers to any one selected mode #define GDMT_MODE 0x02 #define GLITE_MODE 0x04 #define ADSL2_MODE 0x08 #define ADSL2PLUS_MODE 0x10 #define T1413_MODE 0x80 #define ADSL2_DELT (ADSL2_MODE + DELT_ENABLE) #define ADSL2PLUS_DELT (ADSL2PLUS_MODE + DELT_ENABLE) #define BIS_STDS_MASK (ADSL2_MODE | ADSL2PLUS_MODE | DELT_ENABLE) // Definitions used to indicate the Annex in which the modem trained up. // Values for annex_selected field of DEV_HOST_dspWrNegoParaDef_t enum { ANNEXA = 0x1, ANNEXB = 0x2, ANNEXC = 0x4, ANNEXI = 0x8, ANNEXJ = 0x10, ANNEXL = 0x20, ANNEXM = 0x40 }; // Definitions for psd_mask_qualifier field of DEV_HOST_dspWrNegoParaDef_t // Bit positions of the fields in DEV_HOST_dspWrNegoParaDef_t.psd_mask_qualifier #define OVERLAPPED_SPEC_TYPE_BITPOS 0 #define ANNEXL_TYPE_BITPOS 1 // Also called READSL #define ANNEXMJ_SUBMODE_MASK_BITPOS 2 #define ANNEXMJ_US_INBAND_PSD_SHAPE_BITPOS 6 // Bit position 7 reserved for Annex J or M related use #define ANNEXB_TONES1TO32_SUPP_BITPOS 8 // Overlapped/Non-overlapped Spectrum // 1 - DS/US Overlapped spectrum, 0 - Non overlapped spectrum #define OVERLAPPED_SPECTRUM_USED (0x0001< MAXBADSYNC ADSL frames UINT32 farEndLosErrors; // Number of reported LOS defects by the CO. UINT32 farEndRdiErrors; // Number of reported RDI defects by the CO. // UR8_MERGE_START CQ10979 Jack Zhang SINT32 dsACTPSD; // Downstream actual power spectral density. SINT32 usACTPSD; // Upstream actual power spectral density. SINT32 dsHLINSC; // Downstream linear representation scale. PUINT32 dsHLINps_p; // Downstream linear channel characteristics per subcarrier. // UR8_MERGE_END CQ10979* // UR8_MERGE_START CQ10978 Jack Zhang UINT8 pwrStatus; // DSL Power Management Status. UINT8 pad[3]; // pading to 32 bits. // UR8_MERGE_END CQ10978* } DEV_HOST_modemStatsDef_t; // TPS-TC related statistics // Note that tx and rx notation is relative to the DSL link, not the TPS-TC interface. // Never access a struct of this typedef directly. Always go through the DEV_HOST_atmStats_t struct. typedef struct { UINT32 goodCount; // Transmit Good Cell Count UINT32 idleCount; // Transmit Idle Cell Count UINT8 ncdFlag; // Far end No Cell Delineation indication UINT8 hecFlag; // Far end hec flag indication, ADSL1 only UINT8 intlvFlag; // 1 indicates this bearer is used for ADSL1 interleaved, else 0 UINT8 dummy; // Available for future use UINT32 hecErrors; // Num of far end HEC errored ADSL superframes, ADSL1 only } DEV_HOST_txAtmStats_t; // Never access a struct of this typedef directly. Always go through the DEV_HOST_atmStats_t struct. typedef struct { UINT32 goodCount; // Receive Good Cell Count UINT32 idleCount; // Receive Idle Cell Count UINT32 badHecCount; // Receive Bad Hec Cell Count UINT32 ovflwDropCount; // Receive Overflow Dropped Cell Count DEV_HOST_cellDelinState_t delineationState; // Indicates current delineation state UINT32 ocdErrors; // Out of Cell Delineation UINT32 lcdErrors; // Loss of Cell Delineation (within the same connection) UINT32 hecErrors; // Num of HEC errored ADSL superframes, valid for ADSL1 only UINT8 ocdFlag; // ocd flag for IB setting UINT8 ncdFlag; // No Cell Delineation UINT8 hecFlag; // hec flag for IB setting UINT8 lcdFlag; // Current lcd status for MPS-TC & OAM SINT8 consecOCD; // Count of consecutive OCD errors, + for errors, - for non-errors UINT8 intlvFlag; // 1 indicates this bearer is used for ADSL1 interleaved, else 0 UINT16 dummy; // Available for future use } DEV_HOST_rxAtmStats_t; typedef struct { // These pointers might be easier to handle if they were organized as an array DEV_HOST_txAtmStats_t *tx0_p; // Transmit ATM stats for TC channel 0 DEV_HOST_rxAtmStats_t *rx0_p; // Receive ATM stats for TC channel 0 DEV_HOST_txAtmStats_t *tx1_p; // Transmit ATM stats for TC channel 1 DEV_HOST_rxAtmStats_t *rx1_p; // Receive ATM stats for TC channel 1 } DEV_HOST_atmStats_t; // ---------------------- // Begin EOC definitions. // ---------------------- // The two values below can never change (for backwards compatibility of host intf.) #define DEV_HOST_EOCREG4LENGTH 32 #define DEV_HOST_EOCREG5LENGTH 32 typedef struct { UINT8 eocReg4[DEV_HOST_EOCREG4LENGTH]; // Host/Dsp Write, vendor specific EOC Register 4 UINT8 eocReg5[DEV_HOST_EOCREG5LENGTH]; // Host/Dsp Write, vendor specific EOC Register 5 UINT8 vendorId[8]; // Host write UINT8 revNumber[4]; // Host, ATU-R Revision Number UINT8 serialNumber[32]; // Host write UINT8 eocReg4Length; // Host Write, valid length for EOC register 4 UINT8 eocReg5Length; // Host Write, valid length for EOC register 5 UINT8 selfTestResults[2]; // EOC selftestResults place holder UINT32 eocModemStatusReg; // Dsp Write, status bits to host UINT8 lineAtten; // Dsp Write, line attenuation in 0.5 db step UINT8 bDummy; // To make sure that aturConfig was 16-bit aligned // UR8_MERGE_START CQ11228 HZ SINT16 dsMargin; // DSP Write, measured DS margin in 0.1 db precision UINT8 aturConfig[30]; // Dsp Write, also used by EOC for ATUR Configuration - needs to be 32-bit aligned UINT8 dummy2[2]; // Dummy to make revNumber_2p 32-bit aligned UINT8 revNumber_2p[16]; // CQ10037- Host, ATU-R Version Number, used only in ADSL2, ADSL2plus mode. } DEV_HOST_eocVarDef_t; typedef struct { UINT16 endEocThresh; // Host Write, end of Clear EOC stream threshold UINT16 dummy; // dummy value to fill gap UINT32 dropEocCount; // Dsp Write, counter of dropped Clear EOC bytes UINT16 eocRxLength; // Host/DSP write, number of valid Rx Clear EOC bytes UINT16 eocTxLength; // Host/DSP write, number of valid Tx Clear EOC bytes UINT8 eocRxBuf[64]; // Dsp Write, Buffer for receiving Rx Clear EOC bytes UINT8 eocTxBuf[64]; // Host Write, Buffer for writing Tx Clear EOC bytes } DEV_HOST_clearEocVarDef_t; // ----------------------------------- // Begin DSP/Host Mailbox Definitions. // ----------------------------------- // The 3 values below can never be decreased, only increased. // If you increase one of the values, you must add more to the // initializers in "dev_host_interface.c". #define DEV_HOST_HOSTQUEUE_LENGTH 8 #define DEV_HOST_DSPQUEUE_LENGTH 8 #define DEV_HOST_TEXTQUEUE_LENGTH 8 // Never access a struct of this typedef directly. Always go through the DEV_HOST_mailboxControl_t struct. typedef struct { UINT8 cmd; UINT8 tag; UINT8 param1; UINT8 param2; } DEV_HOST_dspHostMsg_t; // Never access a struct of this typedef directly. Always go through the DEV_HOST_mailboxControl_t struct. typedef struct { UINT32 msgPart1; UINT32 msgPart2; } DEV_HOST_textMsg_t; // The structure below has been ordered so that the Host need only write to // even byte locations to update the indices. // The Buffer pointers in the struct below each point to a different // struct array that has an array size of one of the matching Queue Length // values defined above (DEV_HOST_HOSTQUEUE_LENGTH, DEV_HOST_DSPQUEUE_LENGTH, // and DEV_HOST_TEXTQUEUE_LENGTH). typedef struct { UINT8 hostInInx; // Host write, DSP must never write except for init UINT8 bDummy0[3]; // dummy bytes for explicit 32-bit alignment UINT8 hostOutInx; // DSP write, Host must never write UINT8 bDummy1[3]; // dummy bytes for explicit 32-bit alignment UINT8 dspOutInx; // Host write, DSP must never write except for init UINT8 bDummy2[3]; // dummy bytes for explicit 32-bit alignment UINT8 dspInInx; // DSP write, Host must never write UINT8 bDummy3[3]; // dummy bytes for explicit 32-bit alignment UINT8 textInInx; // DSP write, Host must never write UINT8 bDummy4[3]; // dummy bytes for explicit 32-bit alignment UINT8 textOutInx; // Host write, DSP must never write except for init UINT8 bDummy5[3]; // dummy bytes for explicit 32-bit alignment DEV_HOST_dspHostMsg_t *hostMsgBuf_p; // pointer to Host Mailbox Buffer (Host writes the buffer) DEV_HOST_dspHostMsg_t *dspMsgBuf_p; // pointer to DSP Mailbox Buffer (DSP writes the buffer) DEV_HOST_textMsg_t *textMsgBuf_p; // pointer to Text Mailbox Buffer (DSP writes the buffer) } DEV_HOST_mailboxControl_t; //----------------------------------------- // Physical layer performance parameter //----------------------------------------- typedef struct { SINT32 hybridCost[30/*PHY_HYB_OPTIONS*/];// Cost functions for hybrids (0: none, 1-4 hybrid options) UINT8 bestHybrid; // Index of best hybrid UINT8 bDummy0[3]; // dummy bytes for explicit 32-bit alignment UINT32 bestHybRejection; // rejection_dB = 10 * log10(rejection / 256) SINT32 usAvgGain; // upstream average gain in 20log10 (Q8) SINT32 dsAvgGain; // downstream average gain in 20log10 (Q8) UINT8 disableDspHybridSelect_f; // Allows host to disable the automatic hybrid selection by the DSP UINT8 hostSelectHybridNum; // DSP will use this hybrid number only if DSP Select is disabled (values: 1-4) UINT8 currentHybridNumUsed; // DSP indicates to the host the current hybrid number in use UINT8 reserved1; // reserved for future use } DEV_HOST_phyPerf_t; /*********************************************************** * The 3 structures below are used only for analog * diagnostic functions originally defined in diag.h * Moved here by Carlos A. Perez under J. Bergsagel request ***********************************************************/ /****************************************************************************/ /* Options for the Analog Diagnostic user input data structure */ /* (MUST be word aligned) */ /****************************************************************************/ typedef enum { ZERO_DIAG_OPT = 0, // dummy value for zero place-holder NOISE_ONLY = 0x1, // diagnostic in noise only mode (on=1, off=0), disregard diagMode 0-4 EXTERNAL_CO = 0x2, // operates against external CO (external=1, internal=0) DIAG_AGC = 0x4, // agc selects gains control (agc=1, manual=0) CROSSTALK_TEQ = 0x8, // crosstalk selects teq (crosstalk=1, manual=0) LEAKY_TEQ = 0x10, // use leaky teq (on=1, off=0) AUX_AMPS = 0x20, // auxamps (on=1, off=0) BW_SELECT = 0x40, // change rxhpf/txlpf fc (modify=1, default=0) DIAG_HYB_SELECT = 0x80, // change hybrid (modify=1, default=0) POWER_DOWN_CDC = 0x100, // power down codec (power down=1, no power down=0) ISDN_OP_MODE = 0x200, // operation mode (pots=0, isdn=1) BYPASS_RXAF2 = 0x400, // Bypass except RXAF2 (on=1, off = 0) TX_TEST_CONT = 0x800, // Continuous tx test (on=1, off=0) TX_SCALE_MTT = 0x1000 // Scale tx signal for Mtt test (on=1, off=0) } DEV_HOST_diagAnlgOptionsVar_t; /****************************************************************************/ /* Analog Diagnostic user input data structure (MUST be word align) */ /****************************************************************************/ typedef struct { DEV_HOST_diagAnlgOptionsVar_t diagOption; // Other diagnostic optional settings UINT8 diagMode; // Performance diagnostic mode UINT8 txMode; // transmit mode UINT8 rxMode; // receive mode UINT8 teqSp; // Select teq starting pt UINT8 txDf1; // see dev_codec_filters.c and UINT8 txDf2a; // dev_codec.h for filter coefficients UINT8 txDf2b; UINT8 rxDf4; UINT16 codingGain256Log2; // 256*Log2(coding gain) UINT16 noiseMargin256Log2; // 256*Log2(noise margin) UINT16 rxPga1; // PGA1 UINT16 rxPga2; // PGA2 UINT16 rxPga3; // PGA3 UINT16 anlgEq; // AEQ settings (dB/MHz) SINT8 pilotBin; // Select pilot subchannel SINT8 txSwGain; // manual set for bridge tap loop SINT8 tdw1Len; // TDW1 length - 0,2,4,8,16 SINT8 tdw2Len; // TDW2 length - 0,2,4,8,16 UINT8 teqEcMode; // TEQ/EC mode UINT8 hybrid; UINT8 txAttn; // Codec Tx attenuation UINT8 txGain; // Codec Tx gain (Sangam only) SINT16 txPda; //Codec Tx Digital gain/attn UINT8 txTone[MAX_NUM_UPBINS]; // Turning tones on/off // Still govern by lastbin UINT16 rsvd; //for 32 bits alignment }DEV_HOST_diagAnlgInputVar_t; /****************************************************************************/ /* Analog diagnostic output data structure */ /****************************************************************************/ typedef struct { PSINT32 rxSnr_p[2]; // Pointer to estimated snr PSINT32 rxSubChannelCapacity_p[2]; // Pointer to estimated subchan capacity PSINT32 rxSignalPower_p[2]; // Pointer to estimated signal power PSINT32 rxNoisePower_p[2]; // Pointer to estimated noise power PSINT32 rxAvg_p; // Pointer to average of rcvd signal SINT32 chanCapacity[2] ; // Channel total capacity SINT32 dataRate[2]; // Modem data rate (SNR) SINT32 avgNoiseFloor; // Average noise floor SINT16 snrGap256Log2; // 256*Log2(snr gap) SINT16 rxPga1; // PGA1 SINT16 rxPga2; // PGA2 SINT16 rxPga3; // PGA3 SINT16 anlgEq; // AEQ settings (dB/MHz) SINT8 rcvMode; // CPE rcv mode for Matlab data processing SINT8 rsvd; }DEV_HOST_diagAnlgOutputVar_t; // Bit field structure that allows the host to mask off interrupt sources for possible DSP-to-Host interrupts. // Each bit represents a possible source of interrupts in the DSP code that might cause a DSP-to-Host // interrupt to occur. // This mask structure is not intended to show how interrupt sources in the DSP code correspond to the actual // DSP-to-Host interrupts. There could be multiple ways to cause an interrupt in the DSP code, but they all // eventually tie into one of the three possible DSP-to-Host interrupts. // The host should write a "1" to an individual bit when it wants to mask possible interrupts from that source. // enum that represents individual bits in maskBitField1 typedef enum { ZERO_MASK1 = 0, // dummy value for zero place-holder DSP_MSG_BUF = 0x1, // mask interrupts due to DSP-to-Host message mailbox updates STATE_BIT_FIELD = 0x2, // mask interrupts due to changes in the modem state bit fields DSP_HEARTBEAT = 0x4 // mask interrupts for the DSP hearbeat } DEV_HOST_intMask1_t; // this enum should only have 32 values in it (maximum). // Add more "mask bit fields" at the end of this struct if you need more mask values typedef struct { DEV_HOST_intMask1_t maskBitField1; } DEV_HOST_hostInterruptMask_t; // this struct should only have 32 bits in it. // Bit field structure that allows the host to determine the source(s) of DSP-to-Host interrupts in case // several of the interrupt sources get combined onto a single DSP-to-Host interrupt. // DSP will set each bit to a "1"as an interrupt occurs. // Host has the reponsibility to clear each bit to a "0" after it has determined the source(s) of interrupts. // Each source bit field in this struct will use the same enum typedef that matches the corresponding mask // bit field in "DEV_HOST_hostInterruptMask_t" typedef struct { DEV_HOST_intMask1_t sourceBitField1; } DEV_HOST_hostInterruptSource_t; // -------------------------- // Begin bitswap definitions. // -------------------------- // bitSwapSCnt contains the superframe to perform bit swap // The entries must be ordered so that the first group only contains bit change commands // The other entries may contain power adjustment instructions and must be // written with something. NOP (0) is an available instruction. typedef struct { PUINT8 fineGains_p; // pointer to bng string, needed to check fine gains for powerswap UINT8 bitSwapNewIndices[6]; // Bin before bitSwapBin to process UINT8 bitSwapCmd[6]; // Bitswap command for bitSwapBin UINT8 bitSwapBin[6]; // bin to modify UINT8 bitSwapSCnt; // Superframe count on which to perform bitswap UINT8 bitSwapEnabled; // bitSwapEnabled } DEV_HOST_dspBitSwapDef_t; // ------------------------------------------- // Begin OLR DSP Rx definitions for ADSL2 and ADSL2 plus. // ------------------------------------------- // OLR (On-line reconfig) contains the variables and arrays to perform US bitswap // DRR and SRA variables can be added in this struct later // All fields are DSP write/read with OVHD level2 Rx buffer. typedef struct { UINT8 bitSwapEnabled; // Enable bitswap UINT8 Index; // index to parse msg UINT8 ctrl_field; // OLR msg control field UINT8 MsgType; // OLR msg type UINT8 NakReason; // Negtive Ack and reason UINT8 send_msg_action; // Transmit/re-transmit msg flag UINT8 resp_msg_action; // Negative resp msg value UINT8 ss_invert_phase; // Sending response of inverted phase for sync symbol UINT16 Nf; // number of subcarriers to be modified //UR8_MERGE_START CQ10758 Tim UINT16 Lp; // CQ10758: the new total number of bits from SRA UINT8 Bp; // CQ10758: the new Bp from an SRA or DRR UINT8 dummy; //UR8_MERGE_END CQ10758 Tim UINT16 msg_i; // Msg index to store bit swap msg UINT8 binnum[MAX_NUM_UPBINS]; // Subcarrier numbers OLR_BSWP_MAX_LEN for US UINT16 gainnbits[MAX_NUM_UPBINS]; // 12-bit gains and 4-bit bits for the subcarrier } DEV_HOST_olrDspRxDef_t; // struct def for parsing US req bitswap msg // ------------------------------------------- // Begin OLR DSP Tx definitions. // ------------------------------------------- // OLR (On-line reconfig) contains the variables to perform DS bitswap // DRR and SRA variables can be added in this struct later // All fields are DSP write/read with OVHD level2 Tx buffer. typedef struct { UINT8 bitSwapEnabled; // Enable Bitswap Flag UINT8 ctrl_field; // OLR msg control field UINT8 MsgType; // OLR msg type UINT8 waitforresp; // wait for response flag UINT8 resend_count; // retransmit counter to limit resend UINT8 prev_ss_phase; // Previously detected sync symbol phase UINT16 prev_txmsg_len; // Previous Tx msg length for resending SINT16 timeoutcnt; // wait for response timeout count } DEV_HOST_olrDspTxDef_t; // struct def for generating DS bitswap req // --------------------------- // Begin ATM BERT definitions. // --------------------------- // Structure used for ATM Idle Cells based bit error rate computation. typedef struct { UINT8 atmBertFlag; // Feature enable/disable flag (Host write) UINT8 dummy1; UINT8 dummy[2]; // Dummy bytes for 32-bit alignment UINT32 bitCountLow; // Low part of 64-bit BERT bit count (DSP write) UINT32 bitCountHigh; // High part of 64-bit BERT bit count (DSP write) UINT32 bitErrorCountLow; // Low part of 64-bit BERT bit count (DSP write) UINT32 bitErrorCountHigh;// High part of 64-bit BERT bit count (DSP write) } DEV_HOST_atmDsBert_t; // ------------------------------------ // Misc. modem environment definitions. // ------------------------------------ typedef struct { SINT16 subStateIndex; // Index that signifies datapump substate. (DSP write) UINT8 externalBert; // Turn on/off external BERT interface. 0 = OFF; 1 = ON. (Host write) UINT8 usBertPattern; // BERT pattern for US TX data. 0 = 2^15-1; 1 = 2^23-1. (Host write) UINT8 overrideDslLinkLed_f; // Overrides DSP operation of the DSL_LINK LED. (Host write) // 0 = DSP is in control; 1 = Host is in control. UINT8 dslLinkLedState_f; // DSL_LINK LED state when override flag has been set. (Host write) // DSL_LINK LED will be updated with this value once per frame. // LED is active-low: 0 = ON, 1 = OFF. UINT8 overrideDslActLed_f; // Overrides DSP operation of the DSL_ACT LED. (Host write) // 0 = DSP is in control; 1 = Host is in control. UINT8 dslActLedState_f; // DSL_ACT LED state when override flag has been set. (Host write) // DSL_ACT LED will be updated with this value once per frame. // LED is active-low: 0 = ON, 1 = OFF. UINT8 dGaspLprIndicator_f; // How LPR signal (GPIO[0]) is to be interpreted. (Host write) // 0 = LPR is active-low; 1 = LPR is active-high. UINT8 overrideDspLprGasp_f; // Overrides DSP detection of LPR signal to send out DGASP. (Host write) // 0 = DSP detects LPR; 1 = Host detects LPR and sends "HOST_DGASP" to DSP. UINT8 pcbEnabled; // DS power cut back UINT8 maxAvgFineGainCtrl_f; // If maxAvgFineGainCtrl_f == 0, then the datapump controls the maximum average fine gain value. // If maxAvgFineGainCtrl_f == 1, then the host controls the maximum average fine gain value. UINT32 reasonForDrop; // This field will tell the host what might be the reason for a dropped connection. SINT16 maxAverageFineGain; // When maxAvgFineGainCtrl_f == 1, the value in maxAverageFineGain is the maximum average fine gain level in 256log2 units. // UR8_MERGE_START_END CQ10415_CABMODE HL UINT8 CO_cabinet_mode_enabled; // 0 = Default // 1 = (Mode is G.992.5 mode) && (CO is Infineon) && (Cabinet mode with DS start tone # >= 100) UINT8 enable_cnxt_ovhd_patch_f; } DEV_HOST_modemEnvPublic_t; // ----------------------------- // Generic structure definition. // ----------------------------- typedef struct { PSINT8 parameter1_p; PSINT16 parameter2_p; PSINT32 parameter3_p; PUINT8 parameter4_p; PUINT16 parameter5_p; PUINT32 parameter6_p; } DEV_HOST_genericStructure_t; // ------------------------------ // Begin G.hs buffer definitions. // ------------------------------ typedef struct { UINT8 txBuf[64]; // G.hs xmt buffer } DEV_HOST_ghsDspTxBufDef_t; typedef struct { UINT8 rxBuf[80]; // G.hs rcv buffer } DEV_HOST_ghsDspRxBufDef_t; // ----------------------------------------- // Begin Constellation Display definitions. // ----------------------------------------- typedef struct { UINT32 consDispStartAddr; // Host write UINT32 consDispCurrentAddr; // Host write UINT32 consDispBufLen; // Constellation Buffer Length UINT32 consDispBin; // Host write, DS band only } DEV_HOST_consBufDef_t; typedef struct { PSINT16 buffer1_p; //DSP write PSINT16 buffer2_p; //DSP write } DEV_HOST_snrBuffer_t; // --------------------------------------------------------------------------------- // Typedef to be used for the clear EOC HDLC frame exchange between host and DSP, // used in ovhd_eoc.c // --------------------------------------------------------------------------------- #define OVHD_clearEOC_hostBufSize 600 // overhead clear EOC HDLC host buffer size #define OVHD_clearEOC_hostBuffers 4 // number of overhead clear EOC HDLC host buffers in Rx or Tx typedef struct { UINT32 len; // packet length UINT8 data[OVHD_clearEOC_hostBufSize]; // data field } clearEocBufDesc_t; typedef struct { UINT32 clearEocEnabled; // 0 -- disabled; 1 -- enabled. clearEocBufDesc_t *pTxBufDesc[OVHD_clearEOC_hostBuffers]; // Tx buffer desc pointer array clearEocBufDesc_t *pRxBufDesc[OVHD_clearEOC_hostBuffers]; // Rx buffer desc pointer array UINT32 txRdIndex; // DSP read UINT32 txWrIndex; // Host write UINT32 rxRdIndex; // Host read UINT32 rxWrIndex; // DSP write } DEV_HOST_clearEocParm_t; typedef struct { UINT32 phyFeature; // Feature bits UINT32 phyControl; // Control bits } DEV_HOST_phyFeatureConfiguration_t; typedef struct { DEV_HOST_phyFeatureConfiguration_t * phyFeatureList0_p; // Pointer to Feature List 0 DEV_HOST_phyFeatureConfiguration_t * phyFeatureList1_p; // Pointer to Feature List 1 DEV_HOST_phyFeatureConfiguration_t * phyInteropList0_p; // Pointer to Interop feature list 0 DEV_HOST_phyFeatureConfiguration_t * phyInteropList1_p; // Pointer to Interop feature list 1 } DEV_HOST_phyControlStructure_t; //Management counters (moved from ovhd_bis_mgmt.h) //WARNING! //The order of this structure is critical as it mirrors the ADSL2 //management overhead message and we take advantage of this as part of an //optimization in ovvhd_bis_mgmt.c. Do not change the order or remove //anything and if you need to make an addition, it must be an integer //and it must be added to the end typedef struct { //PMD and PMS-TC counters UINT32 fec_errors_Lpa; //fec anomalies for latency path a UINT32 fec_errors_Lpb; //fec anomalies for latency path b UINT32 crc_errors_Lpa; //crc anomalies for latency path a UINT32 crc_errors_Lpb; //crc anomalies for latency path b UINT32 fec_errored_seconds; //FEC errored seconds counter UINT32 errored_seconds; //errored seconds counter UINT32 severly_errored_seconds; //severly errored seconds counter UINT32 los_errored_seconds; //los errored seconds counter UINT32 unavailable_seconds; //unavailable errored seconds counter //TPS-TC counters //for channel 0 UINT32 hec_errors_Ch0; //HEC anomalies counters UINT32 total_cells_thro_HEC_Ch0; //counter of total cells passed through HEC function UINT32 total_cells_to_ATM_Ch0; //counter of total cells passed to the upper ATM function UINT32 bit_errors_idle_cells_Ch0; //counter of total bit errors detected in ATM idle cells payload //for channel 1 UINT32 hec_errors_Ch1; //HEC anomalies counters UINT32 total_cells_thro_HEC_Ch1; //counter of total cells passed through HEC function UINT32 total_cells_to_ATM_Ch1; //counter of total cells passed to the upper ATM function UINT32 bit_errors_idle_cells_Ch1; //counter of total bit errors detected in ATM idle cells payload }BIS_MGMT_CountersDef_t; typedef struct { BIS_MGMT_CountersDef_t *bis_Mgmt_Count_US_p; BIS_MGMT_CountersDef_t *bis_Mgmt_Count_DS_p; } DEV_HOST_MGMTCount_t; typedef struct //(CQ10242) { UINT8 redirect; // set by NSP UINT8 ack; // set by datapump to acknowledge redirect UINT16 buffsize; // size of debug buffer in chars PUINT8 buffaddr; // address of debug buffer (an array of char) } DEV_HOST_Cli2lctl_t; /*EP Addition Start*/ #define MAX_BAND 5 typedef struct { short numTone; /*total number of tones defined in the band plan*/ short numBand; /*total number of band pairs defined in the band plan*/ struct { short start_tone; /*starting tone number*/ short end_tone; /*ending tone number*/ } bandPair[MAX_BAND]; } BandPlanSingle_t; typedef struct { BandPlanSingle_t *txBandPlan; /* transmit */ BandPlanSingle_t *rxBandPlan; /* receive */ } BandPlan_t; typedef struct { BandPlan_t *ptrBandPlan; /*pointer to the band plan list*/ UINT8 currentIndex; /*offset to ptrBandPlan, band plan used*/ UINT8 customIndex; /*offset to ptrBandPlan, band plan customized*/ UINT8 reserved1; UINT8 reserved2; } DEV_HOST_BandPlan_t; /*EP Addition Stop*/ // -------------------------------------------------------------------------------------- // Typedef to be used for the DEV_HOST_dspOamSharedInterface_s struct of pointers // (this is used in dev_host_interface.c). // NOTE: This struct of pointers is NEVER to be referenced anywhere else in the DSP code. // IMPORTANT: Only pointers to other structs go into this struct !! // -------------------------------------------------------------------------------------- typedef struct { DEV_HOST_hostIntfcVersionDef_t *hostIntfcVersion_p; DEV_HOST_dspVersionDef_t *datapumpVersion_p; DEV_HOST_modemStateBitField_t *modemStateBitField_p; DEV_HOST_dspWrNegoParaDef_t *dspWriteNegoParams_p; DEV_HOST_oamWrNegoParaDef_t *oamWriteNegoParams_p; DEV_HOST_raMsgsDef_t *raMsgs_p; DEV_HOST_dspWrSuperFrameCntDef_t *dspWriteSuperFrameCnt_p; DEV_HOST_msg_t *atucMsg_p; DEV_HOST_msg_t *aturMsg_p; DEV_HOST_dspWrSharedTables_t *dspWrSharedTables_p; void *unused1; // overlay DEV_HOST_eocVarDef_t *eocVar_p; DEV_HOST_clearEocVarDef_t *clearEocVar_p; DEV_HOST_modemStatsDef_t *modemStats_p; DEV_HOST_atmStats_t *atmStats_p; DEV_HOST_mailboxControl_t *dspHostMailboxControl_p; DEV_HOST_phyPerf_t *phyPerf_p; DEV_HOST_diagAnlgInputVar_t *analogInputVar_p; DEV_HOST_diagAnlgOutputVar_t *analogOutputVar_p; DEV_HOST_hostInterruptMask_t *hostInterruptMask_p; void *unused2; // profileList_p; DEV_HOST_hostInterruptSource_t *hostInterruptSource_p; DEV_HOST_dspBitSwapDef_t *dspBitSwapDstrm_p; DEV_HOST_dspBitSwapDef_t *dspBitSwapUstrm_p; DEV_HOST_atmDsBert_t *atmDsBert_p; DEV_HOST_modemEnvPublic_t *modemEnvPublic_p; DEV_HOST_genericStructure_t *genericStructure1_p; DEV_HOST_genericStructure_t *genericStructure2_p; DEV_HOST_ghsDspTxBufDef_t *ghsDspTxBuf_p; DEV_HOST_ghsDspRxBufDef_t *ghsDspRxBuf_p; DEV_HOST_consBufDef_t *consDispVar_p; DEV_HOST_snrBuffer_t *snrBuffer_p; DEV_HOST_olrDspRxDef_t *olrDspRx_p; DEV_HOST_olrDspTxDef_t *olrDspTx_p; DEV_HOST_clearEocParm_t *pClrEOC_p; DEV_HOST_phyControlStructure_t *phyControl_p; DEV_HOST_MGMTCount_t *mgmt_Count_p; DEV_HOST_Cli2lctl_t *cli_p; //(CQ10242) } DEV_HOST_dspOamSharedInterface_t; // --------------------------------------------------------------------------------- // Typedef to be used for the pointer to the DEV_HOST_dspOamSharedInterface_s struct // of pointers (this is used in dev_host_interface.c). // --------------------------------------------------------------------------------- typedef DEV_HOST_dspOamSharedInterface_t *DEV_HOST_dspOamSharedInterfacePtr_t; #endif