/**
 *  \file   dsl_hal_csl.c
 *
 *  \author Copyright (C) 2001-2006 Texas Instruments Incorporated.
 *
 *  \brief  This file contains DSL HAL CSL source code for DSL device driver.
 *
 *  \date   18May06     0.00.00     EP      Created: Ported from AR7.
 *  \date   17Nov06     0.00.01     EP      Supported Big Endian on Yamuna.
 *  \date   16Feb07     0.00.02     EP      Always clear all DSL interrupt bits.
 *  \date   23Feb07     0.00.03     EP      CQ11512: Added resetting DSLSS peripherals.
 */


#include <dsl_hal_csl.h>


unsigned char triggerDsp250MHZ = 0;

#ifdef YAMUNA

void dslhal_csl_clearInterrupt()
{
  unsigned clrReg;

//bk
  unsigned srcReg;
  static unsigned intCnt = 0;
  
  intCnt++;
  
  srcReg = HOST_REG(DSP_INTR_CLR_REGISTER);
  //printk("[bk] %s: %p, intCnt = %d\n",__FUNCTION__,srcReg,intCnt);

  // if (intCnt > 2000 ) return; 
  
//end bk

  
  /* Clear out the DSLSS Interrupt Registers to acknowledge Interrupt */
  /* Always clear all interrupts, EP20070216 */
  clrReg = HOST_REG(DSP_INTR_CLR_REGISTER);
  clrReg |= MASK_INTR_ALL;
  HOST_REG(DSP_INTR_CLR_REGISTER) = clrReg;
}


static struct {
    unsigned int  initF;
    unsigned int  chip_id;
} CSL;

void dslhal_csl_init(void)
{
    CSL.chip_id = DSLHAL_REG32(REG_CVR) & 0xFFFF;
    CSL.initF = TRUE;
}


/**
 * \brief   Map DSP memory address to HOST memory space.
 *          HOST          DSP
 *          PMEM          N/A
 *          DMEM          MIPS2DMEM_OFFSET[31:22], addr[21:0]
 *          PERI          MIPS2PERI_OFFSET[31:23], addr[22:0]
 *
 *  @param  addrDsp DSP memory address.
 *  @return 0:      Invalid DSP address.
 *          other:  Host memory address.
 */
unsigned int dslhal_support_hostDspAddressTranslate( unsigned int addrDsp )
{
    unsigned int addrHost = DSLHAL_ERROR_ADDRESS_TRANSLATE;

    if (!CSL.initF)
    {
        dslhal_csl_init();
    }

    dgprintf(7, "dslhal_support_hostDspAddressTranslate: chip_id = %x\n", CSL.chip_id);

    switch (addrDsp & 0xF0000000)
    {
#ifdef DSP_RST_WORKAROUND  /*work-around*/
        case 0x00000000 :
#else
        case 0x00000000 :
            addrHost = 0x10000000 | (HOST_REG(REG_PM2EMIF) + (addrDsp & 0x003FFFFF));
            break;
#endif
        case 0x10000000 :
            addrHost = 0x10000000 | (HOST_REG(REG_DM2EMIF) + (addrDsp & 0x003FFFFF));
            break;
        case 0x80000000 :  /*MIPS2DMEM_OFFSET*/
            addrHost = 0x01C00000 | (addrDsp & 0x003FFFFF);
            break;
#if 0
        case 0x02000000 :  /*MIPS2PERI_OFFSET*/
            addrHost = 0x01000000 | (addrDsp & 0x007FFFFF);
            break;
#endif
        default:
            return 0;
            break;
    }
    addrHost = HOST_MEM_V2P(addrHost);

    dgprintf(7, "DSP(%08x)->HOST(%08x)\n", addrDsp, addrHost);

    return addrHost;
}


int  dslhal_support_unresetDslSubsystem(void)
{
  dgprintf(5,"Bring DSLSS out of Reset \n");

  DSLHAL_REG32(REG_PRCR) |= PRCR_ADSLSS;
  shim_osClockWait(DSLHAL_REG_DELAY);

  dgprintf(4," dslhal_support_unresetDslSubsystem done: 0x%0x\n", DSLHAL_REG32(REG_PRCR));
  return DSLHAL_ERROR_NO_ERRORS;
}


int  dslhal_support_resetDslSubsystem(void)
{
  dgprintf(4, "dslhal_support_resetDslSubsystem \n");

  if (DSLHAL_REG32(REG_PRCR) & PRCR_ADSLSS)
  {
    unsigned count;

    HOST_REG(DEV_DSPSS_PRCONT_ADDR) = 0;
    shim_osClockWait(DSLHAL_REG_DELAY);

    HOST_REG(DEV_MDMA0_CTL_ADDR)    = 0;
    shim_osClockWait(DSLHAL_REG_DELAY);
    HOST_REG(DEV_MDMA1_CTL_ADDR)    = 0;
    shim_osClockWait(DSLHAL_REG_DELAY);
    HOST_REG(DEV_MDMA2_CTL_ADDR)    = 0;
    shim_osClockWait(DSLHAL_REG_DELAY);
    HOST_REG(DEV_MDMA3_CTL_ADDR)    = 0;

    count = 1000;
    while (count--) {
        shim_osClockWait(720);
    }

    HOST_REG(DEV_PERIPH_PRCR_BASE) &= ~(DEV_PERIPH_PRCR_424M | DEV_PERIPH_PRCR_360M | DEV_PERIPH_PRCR_DI | DEV_PERIPH_PRCR_ATMTC);

    count = 1000;
    while (count--) {
        shim_osClockWait(720);
    }
  }

  DSLHAL_REG32(REG_PRCR) &= ~PRCR_ADSLSS;
  shim_osClockWait(DSLHAL_REG_DELAY);

  dgprintf(4, "dslhal_support_resetDslSubsystem Done: 0x%0x\n", DSLHAL_REG32(REG_PRCR));
  return DSLHAL_ERROR_NO_ERRORS;
}


int dslhal_support_unresetDsp(void)
{
  volatile unsigned int reg;

  dgprintf(5,"Bring DSP out of Reset \n");

  reg = DSLHAL_REG32(REG_PRCR);
  reg |= PRCR_DSP;
  DSLHAL_REG32(REG_PRCR) = reg;
  shim_osClockWait(DSLHAL_REG_DELAY);

  if (DSLHAL_REG32(REG_PRCR) != reg)
  {
    DSLHAL_REG32(REG_PRCR) = reg;
    shim_osClockWait(DSLHAL_REG_DELAY);
  }

  dgprintf(4, "dslhal_support_unresetDsp() done: 0x%0x\n", DSLHAL_REG32(REG_PRCR));
  return DSLHAL_ERROR_NO_ERRORS;
}


int dslhal_support_resetDsp(void)
{
  dgprintf(4, "dslhal_support_resetDsp \n");

  DSLHAL_REG32(REG_PRCR) &= ~PRCR_DSP;
  shim_osClockWait(DSLHAL_REG_DELAY);

  dgprintf(4, "dslhal_support_resetDsp Done: 0x%0x\n", DSLHAL_REG32(REG_PRCR));
  return DSLHAL_ERROR_NO_ERRORS;
}


unsigned dslhal_api_boostDspFrequency(void)
{
  return 0;
}

#else


#ifdef PRE_SILICON
/*********************************************/
/*   Base Addresses                          */
/*********************************************/
#define DEV_MDMA_BASE                 0x02000300

/*********************************************/
/*   MC DMA Control Registers in DSL         */
/*********************************************/

#define DEV_MDMA0_SRC_ADDR         (DEV_MDMA_BASE + 0x00000000)
#define DEV_MDMA0_DST_ADDR         (DEV_MDMA_BASE + 0x00000004)
#define DEV_MDMA0_CTL_ADDR         (DEV_MDMA_BASE + 0x00000008)
#define DEV_MDMA1_SRC_ADDR         (DEV_MDMA_BASE + 0x00000040)
#define DEV_MDMA1_DST_ADDR         (DEV_MDMA_BASE + 0x00000044)
#define DEV_MDMA1_CTL_ADDR         (DEV_MDMA_BASE + 0x00000048)
#define DEV_MDMA2_SRC_ADDR         (DEV_MDMA_BASE + 0x00000080)
#define DEV_MDMA2_DST_ADDR         (DEV_MDMA_BASE + 0x00000084)
#define DEV_MDMA2_CTL_ADDR         (DEV_MDMA_BASE + 0x00000088)
#define DEV_MDMA3_SRC_ADDR         (DEV_MDMA_BASE + 0x000000C0)
#define DEV_MDMA3_DST_ADDR         (DEV_MDMA_BASE + 0x000000C4)
#define DEV_MDMA3_CTL_ADDR         (DEV_MDMA_BASE + 0x000000C8)

#define DEV_MDMA0_SRC           (*((volatile UINT32 *) DEV_MDMA0_SRC_ADDR))
#define DEV_MDMA0_DST           (*((volatile UINT32 *) DEV_MDMA0_DST_ADDR))
#define DEV_MDMA0_CTL           (*((volatile UINT32 *) DEV_MDMA0_CTL_ADDR))
#define DEV_MDMA1_SRC           (*((volatile UINT32 *) DEV_MDMA1_SRC_ADDR))
#define DEV_MDMA1_DST           (*((volatile UINT32 *) DEV_MDMA1_DST_ADDR))
#define DEV_MDMA1_CTL           (*((volatile UINT32 *) DEV_MDMA1_CTL_ADDR))
#define DEV_MDMA2_SRC           (*((volatile UINT32 *) DEV_MDMA2_SRC_ADDR))
#define DEV_MDMA2_DST           (*((volatile UINT32 *) DEV_MDMA2_DST_ADDR))
#define DEV_MDMA2_CTL           (*((volatile UINT32 *) DEV_MDMA2_CTL_ADDR))
#define DEV_MDMA3_SRC           (*((volatile UINT32 *) DEV_MDMA3_SRC_ADDR))
#define DEV_MDMA3_DST           (*((volatile UINT32 *) DEV_MDMA3_DST_ADDR))
#define DEV_MDMA3_CTL           (*((volatile UINT32 *) DEV_MDMA3_CTL_ADDR))

/* MDMA control bits                     */

#define DEV_MDMA_START             0x80000000
#define DEV_MDMA_STOP              0x00000000
#define DEV_MDMA_STATUS            0x40000000
#define DEV_MDMA_DST_INC           0x00000000
#define DEV_MDMA_DST_FIX           0x02000000
#define DEV_MDMA_SRC_INC           0x00000000
#define DEV_MDMA_SRC_FIX           0x00800000
#define DEV_MDMA_BURST1            0x00000000
#define DEV_MDMA_BURST2            0x00100000
#define DEV_MDMA_BURST4            0x00200000

#define DEV_MDMA_LEN_SHF           2
#define DEV_MDMA_LEN_MASK          0x0000FFFF

#define DMA0   0
#define DMA1   1
#define DMA2   2
#define DMA3   3
#endif
#ifdef DMA
SINT32 getDmaStatus(UINT32 mask)
{
  if(!(IFR & mask))
  {
    return DSLHAL_ERROR_NO_ERRORS;
  }
  else
  {
    ICR = mask ;
    return 1 ;
  }
}

void programMdma(UINT32 dma, UINT32 source, UINT32 destination, UINT32 length, UINT32 wait)
{
  volatile UINT32 statusMask ;

  switch(dma)
  {
  case DMA0:
    {
      DEV_MDMA0_SRC = source ;
      DEV_MDMA0_DST = destination ;
      DEV_MDMA0_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
                       DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
      statusMask = 0x00000010 ;
    }
  break ;
  case DMA1:
    {
      DEV_MDMA1_SRC = source ;
      DEV_MDMA1_DST = destination ;
      DEV_MDMA1_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
                       DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
      statusMask = 0x00000020 ;
    }
  break ;
  case DMA2:
    {
      DEV_MDMA2_SRC = source ;
      DEV_MDMA2_DST = destination ;
      DEV_MDMA2_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
                       DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
      statusMask = 0x00000040 ;
    }
  break ;
  case DMA3:
    {
      DEV_MDMA3_SRC = source ;
      DEV_MDMA3_DST = destination ;
      DEV_MDMA3_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
                       DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
      statusMask = 0x00000080 ;
    }
  break ;

  }

  if(wait)
  {
    while(!(getDmaStatus(statusMask))) ;
  }

}
#endif


/* CQ 9802: Number of power down retries. */
#ifndef PWR_DN_RETRYS
#define PWR_DN_RETRYS   3
#endif


/******************************************************************************************
 * FUNCTION NAME:    dslhal_api_boostDspFrequency(void)
 *
 *******************************************************************************************
 * DESCRIPTION: This fuction will boost DSP frequency to 250MHz
 *
 * INPUT:  none
 *
 * RETURN: 0 SUCCESS
 *         1 FAILED
 *
 *****************************************************************************************/
unsigned int dslhal_api_boostDspFrequency(void)
{
  unsigned int rc;
  unsigned int chipId;
  unsigned int buck_trim_read;

  rc =dslhal_support_hostDspAddressTranslate((unsigned int)0x02040010);
  if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
  {
     dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
     return DSLHAL_ERROR_ADDRESS_TRANSLATE;
  }

  chipId= DSLHAL_REG32(REG_CVR) & 0xFFFF;
  switch (chipId)
  {
  case CHIP_AR7:  /* Sangam */
    dgprintf(4, "Sangam clock boost 250\n");
    /* Put ADSLSS in to reset */
    DSLHAL_REG32(REG_VSERCLKSELR) = 0x1;
    shim_osClockWait(64);
    dgprintf(4,"REG_VSERCLKSELR<-0x01\n");

    DSLHAL_REG32(REG_MIPS_PLLM) = 0x4;
    shim_osClockWait(64);
    dgprintf(4,"Enable Analog PLL \n");

    DSLHAL_REG32(REG_MIPS_PLLM) = 0x97fe;
    shim_osClockWait(64);

    triggerDsp250MHZ = 1;

    break;

  case CHIP_AR7O_250_212:  /* Ohio250/Ohio212(new) */
  // Could be 212 or 250,

    /* read buck trim bits and save for later use */
    DSLHAL_REG32(REG_PRCR) &= ~(PRCR_DSP|PRCR_SAR);
    shim_osClockWait(64);
    DSLHAL_REG32(REG_PRCR) |=  (PRCR_ADSLSS); /* reset ADSLSS */
    shim_osClockWait(64);
    DSLHAL_REG32(REG_ADSLSS_PRCR) |= ADSLSS_PRCR_DSL_SPA;   /* reset ADSLSS DSL_SPA */
    shim_osClockWait(256);

    // Now both 7100&7200 dsp run at 250Mhz.
    // TB - Mask out the byte of interest
    buck_trim_read= (DSLHAL_REG32(REG_BUCKTRIM_READ) >>8)&0xff;
    //
    // If buck trim is '111', then it's Ohio250, boot dsp clock to
    // 250Mhz, otherwise it's Ohio212, don't boost
    // 111 or 110 --> 250Mhz.
    if((buck_trim_read != 0xFF) && ((buck_trim_read==0x07) || (buck_trim_read==0x06)))
    {
      int retry_attmpts;
      volatile unsigned int *dsp_pmem_ptr = (volatile unsigned int *)DSP_PMEM_START_ADDR;
      int pattern = 0xABCDABCD;

      // boost dsp clock to 250Mhz
      dgprintf(4, "Ohio clock boost 250\n");

      triggerDsp250MHZ = 1;

      for(retry_attmpts = 0; retry_attmpts <= PWR_DN_RETRYS; retry_attmpts++)
      {
          /* Ensure that the peripherals in the ADSLSS are in reset */
          DSLHAL_REG32(REG_PRCR) &= ~(PRCR_DSP|PRCR_SAR|PRCR_ADSLSS_ONLY);
          shim_osClockWait(64);

          /* Disabling the system PLL dividers */
          DSLHAL_REG32(REG_SYSTEM_PLLCSR) &= ~PLLEN;
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_PLLCSR<-0x00\n");

          /* Disabling the MIPS PLL dividers */
          DSLHAL_REG32(REG_MIPS_PLLCSR) &= ~PLLEN;
          shim_osClockWait(640);
          dgprintf(4,"REG_MIPS_PLLCSR<-0x00\n");

          /* Disable (gate off) clock from MIPS PLL to ADSLSS */
          DSLHAL_REG32(REG_SYSTEM_POSTDIV2) = 0;
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_POSTDIV2<-0x00\n");

        /* AV:
              Added a check for this should be added for the code below for 1:1 mode
              to ensure that the MIPS PLL has been configured generate the 212MHz
              output for the PHY.
        */
          if(DSLHAL_REG32(REG_MIPS_PLLM) != OHIO_MIPS_PLLM_RATIO)
          {
              DSLHAL_REG32(REG_MIPS_PLLM) =  OHIO_MIPS_PLLM_RATIO;      // programming the multiplier.
              shim_osClockWait(64);
              dgprintf(4,"REG_MIPS_PLLM<-0x05\n");
          }

          /* CQ9802: Power down the peripherals in the ADSLSS */
          DSLHAL_REG32(REG_PDCR) |= (PDCR_SARP | PDCR_ADSLP | PDCR_ADSPP);
          shim_osClockWait(640);

          /* Enable the 250 mode */
          DSLHAL_REG32(REG_VSERCLKSELR) |= OHIO_250_MODE;
          shim_osClockWait(640);
          dgprintf(4,"REG_VSERCLKSELR<-0x100\n");

          /* CQ9802: Power up the peripherals in the ADSLSS */
          DSLHAL_REG32(REG_PDCR) &= ~(PDCR_SARP | PDCR_ADSLP | PDCR_ADSPP);
          shim_osClockWait(640);

          /* Re-enable the MIPS PLL */
          DSLHAL_REG32(REG_MIPS_PLLCSR) |= PLLEN;
          shim_osClockWait(640);
          dgprintf(4,"REG_MIPS_PLLCSR<-0x01\n");

          DSLHAL_REG32(REG_SYSTEM_PLLM) = OHIO_SYS_PLLM_RATIO ;  // programming the multiplier.
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_PLLM<-0x09\n");

          DSLHAL_REG32(REG_SYSTEM_POSTDIV2) = DIVEN | OHIO_SYS_POSTDIV2_RATIO;  // programming the post divider
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_POSTDIV2<-0x8000\n");

          DSLHAL_REG32(REG_SYSTEM_PLLCMDEN) |= GOSETEN2; // enabling the post division.
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_PLLCMDEN<-0x02\n");

          while ((DSLHAL_REG32(REG_SYSTEM_PLLSTAT) & 0x1) != 0)   // wait till we get the ready.
          {
            shim_osClockWait(0x64);
          }

          DSLHAL_REG32(REG_SYSTEM_PLLCMD) |= GOSET2; // this write actually cause the division.
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_PLLCMD<-0x01\n");


          DSLHAL_REG32(REG_SYSTEM_PLLCSR) |= PLLEN ;  // enabling the pll clock.
          shim_osClockWait(640);
          dgprintf(4,"REG_SYSTEM_PLLCSR<-0x01\n");


          /* AV: Added test for making sure that we come out of reset correctly */
          /* Reset ADSLSS so we can read and write the PMEM */
          DSLHAL_REG32(REG_PRCR) |=  (PRCR_ADSLSS);
          shim_osClockWait(640);

          /* Ensure ADSLADR2 maps to the start of DSP PMEM */
          DSLHAL_REG32(ADSLADR2) = 0;

          /* Write a pattern to DSP PMEM */
          *dsp_pmem_ptr = (volatile unsigned int)dslhal_support_byteSwap32(pattern);

          /* Delay to read back */
          shim_osClockWait(640);

          /* Check 1st instruction. If 0, we have encountered the problem. */
          if( *dsp_pmem_ptr == (volatile unsigned int)dslhal_support_byteSwap32(pattern) )
              break;

          dgprintf(4,"Retrying to read the DSP's memory.\n");

          shim_osClockWait(640);
      }//end retry for loop.

      if(retry_attmpts > PWR_DN_RETRYS)
          return DSLHAL_ERROR_RESET_ADSLSS;
    }
    else
    {
        /* We cannot boost the frequency. */
        return(DSLHAL_ERROR_GENERAL_FAILURE);
    }

    break;

  }

  return(DSLHAL_ERROR_NO_ERRORS);
}


/********************************************************************************************
* FUNCTION NAME: dslhal_support_hostDspAddressTranslate()
*
*********************************************************************************************
* DESCRIPTION:
*   Maps ax5 daugter card dsp memory address to avalanche memory space
*
* Input: unsigned int addr,  dsp memory address.
*
* Return: >=0, unsigned int, mapped Avalanche address(VBUS address).
*         -1,  mapping failed
*
*
********************************************************************************************/
/* static unsigned int bbifmap0,bbifmap1; */

unsigned int dslhal_support_hostDspAddressTranslate( unsigned int addr )
{
  unsigned int addrMap;
  unsigned int chipID=0x05;
  /* This function should just be used to move the memory window of the ADSLSS */
  dgprintf(9, "dslhal_support_hostDspAddressTranslate()\n");
  chipID = DSLHAL_REG32(REG_CVR) & 0xFFFF;
  dgprintf(9, "Chip Version %x\n",chipID);
  /*  select vbus to xbus memory  */
  /*  addrMap = addr & 0xff000000; */
  addrMap = addr & ADSLSSADRMASK;
  dgprintf(9, "dslhal_support_hostDspAddressTranslate() done\n");

  if ( ((chipID == CHIP_AR7O_212) ||(chipID == CHIP_AR7O_250_212))
      &&((addrMap == DSP_PMEM_MASK)||(addrMap == DSP_DMEM_MASK)))
    {
      switch(addrMap)
        {
        case DSP_PMEM_MASK:
#ifdef PRE_SILICON
                            return(ADSLSS2_BASE | (~ADSLSSADRMASK & addr)+ 0x00000100);
#else
                            return(ADSLSS2_BASE | (~ADSLSSADRMASK & addr));
#endif
                            break;
        case DSP_DMEM_MASK:
#ifdef PRE_SILICON
                            return(ADSLSS3_BASE | (~ADSLSSADRMASK & addr)+ 0x00000100);
#else
                            return(ADSLSS3_BASE | (~ADSLSSADRMASK & addr));
#endif
                            break;
        }
    }
  else
    {
      /* AR7 case & default case, neither PMEM nor DMEM for AR7O */
      DSLHAL_REG32(ADSLSSADR) = addrMap;
#ifdef PRE_SILICON
  /* Added 0x100 for Pre-Silicon VLNQ offset.. to be removed for Silicon */
      return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr))+ 0x00000100);
#else
      return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr)));
#endif
    }
  return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}


/******************************************************************************************
* FUNCTION NAME:     dslhal_support_unresetDslSubsystem
*
*******************************************************************************************
* DESCRIPTION: This function unreset Dsl Subsystem
*
* INPUT:  None
*
* RETURN: 0 if Pass; 1 if Fail
*
*****************************************************************************************/
int  dslhal_support_unresetDslSubsystem(void)
{
  unsigned int clock_pllm=0;
  unsigned int chip_id;
  int rc;

  chip_id = DSLHAL_REG32(REG_CVR) & 0xFFFF;

  switch(chip_id)
  {
      case CHIP_AR7:     /* Sangam Chip */
          dgprintf(5, "Start programming PLL for Sangam chip\n");
          /*
           * In Sangam, MIPS_PLL Multiplication factor is REG_MIPS_PLLM[15:12]
           * check PLLM to determine desired dsp clock at 200 or 250Mhz.
           * This value was set in dslhal_api_boostDspFrequency().
           * For this reason, this code need to be running after
           * dslhal_api_boostDspFrequency() has been executed
           */
          clock_pllm = (DSLHAL_REG32(REG_MIPS_PLLM) >> 12) & 0x0F;
          dgprintf(5, "clock_ ID = 0x%08x\n", clock_pllm);
          if ((clock_pllm < 7) || (clock_pllm > 9))
          {
             dgprintf(4," dslhal_support_unresetDslSubsystem()\n");
             /* Put ADSLSS in to reset */
             DSLHAL_REG32(REG_VSERCLKSELR) = 0x1;
             shim_osClockWait(64);
             dgprintf(5,"Selected APLL Reg \n");

             DSLHAL_REG32(REG_MIPS_PLLM) = 0x4;
             shim_osClockWait(64);
             dgprintf(5,"Enable Analog PLL \n");

             DSLHAL_REG32(REG_MIPS_PLLM) = 0x77fe;    /* set default to 200MHz */
             shim_osClockWait(64);
             dgprintf(5,"Set PLL for DSP\n");

             dgprintf(5, "Run DSP at 200Mhz\n");
          }
          else
          {
             dgprintf(5, "Run DSP at the preset freq\n");
          }

          break;

      case CHIP_AR7O_250_212:
      case CHIP_AR7O_212:   /* Ohio Chip */
      /*
       * Comment out the following code because:
       * - The setting for various clock mode (eg. 1:1 sync mode) is different.
       * - Change setting of these registers in DSLHAL might be too late for other
       *   peripherials that relys on the setting based on bootloader setting.
       * =>These setting should've been done in bootLoader
       */
#if 0
          dgprintf(5, "Start programming PLL for Ohio chip\n");
          DSLHAL_REG32(REG_MIPS_PLLCSR) = 0;
          DSLHAL_REG32(REG_MIPS_PREDIV) = DIVEN | (0 & 0x1F);
          DSLHAL_REG32(REG_MIPS_PLLM)   = 0x00000005;
          shim_osClockWait(64);

          while (DSLHAL_REG32(REG_MIPS_PLLSTAT) & GOSTAT)
             dgprintf(5, "Wait for GOSTAT in PLL STAT to go to 0 -- Step 1\n");

          DSLHAL_REG32(REG_MIPS_POSTDIV)  = DIVEN | (0 & 0x1F);
          DSLHAL_REG32(REG_MIPS_PLLCMDEN) = GOSETEN;
          DSLHAL_REG32(REG_MIPS_PLLCMD)   = GOSET;

          while (DSLHAL_REG32(REG_MIPS_PLLSTAT) & GOSTAT)
             dgprintf(5, "Wait for GOSTAT in PLL STAT to go to 0 -- Step 2\n");

          DSLHAL_REG32(REG_MIPS_PLLCSR)  |= PLLEN;
#endif
          break;

     default:
          return(DSLHAL_ERROR_UNRESET_ADSLSS);
  }


  /*  DSLHAL_REG32(0xa8611600) = 0x007f1bdf;*/
  DSLHAL_REG32(REG_PRCR) |= PRCR_ADSLSS;
  shim_osClockWait(64);
  dgprintf(5,"Brought ADSLSS out of Reset \n");

  DSLHAL_REG32(REG_GPIOENR) &= ~(BIT20|BIT21|BIT22|BIT23|BIT24|BIT25);
  shim_osClockWait(64);
  dgprintf(5,"Configured GPIO 20-25 for McBSP \n");


  /*  DSLHAL_REG32(0xa8611a04) = 0x00000001;
      shim_osClockWait(64); */

  /*
   * The following code is used to boost CODEC voltage for Sangam250 by setting
   * Buck Trim Bits in CTRL2. For Ohio250, the setting of Buck Trim Bits need
   * to be set in datapump code because each reset of CODEC will clean these
   * Buck Trim Bits.
   * For Ohio(212&250), the following code will be skipped.
   */

  if ((chip_id == CHIP_AR7) && (clock_pllm== 9))
  {
     rc = dslhal_support_hostDspAddressTranslate((unsigned int)0x02040010);
     if (rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
     {
        dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
        return DSLHAL_ERROR_ADDRESS_TRANSLATE;
     }
     DSLHAL_REG32(rc) |= 0x0000f000; /* set Buck Trim Bits in CTRL2 */
     shim_osClockWait(64);
     dgprintf(5,"Set Buck Voltage for DSP\n");
     dgprintf(6,"Current Contents of PRCR: 0x%x\n",(unsigned int)DSLHAL_REG32(REG_PRCR));
  }

  dgprintf(4," dslhal_support_unresetDslSubsystem done\n");
  return DSLHAL_ERROR_NO_ERRORS;
}


/******************************************************************************************
* FUNCTION NAME:    dslhal_support_unresetDsp()
*
*******************************************************************************************
* DESCRIPTION: This fuction takes ax5 daugter board out of reset.
*
* INPUT:  None
*
* RETURN: 0  --successful.
*         1  --failed
*
*****************************************************************************************/
int dslhal_support_unresetDsp(void)
{
#ifdef PRE_SILICON
  /* unsigned char value; */

  rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_SRC_ADDR);
  if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
    {
    dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
    return DSLHAL_ERROR_ADDRESS_TRANSLATE;
    }
  dgprintf(5,"MDMA SRC: %08x\n", rc);
  DSLHAL_REG32(rc) = 0x80000001;
  rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_DST_ADDR);
  if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
    {
    dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
    return DSLHAL_ERROR_ADDRESS_TRANSLATE;
    }
  dgprintf(5,"MDMA DST: %08x\n", rc);
  DSLHAL_REG32(rc) = 0x02090001;
  rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_CTL_ADDR);
  if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
    {
    dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
    return DSLHAL_ERROR_ADDRESS_TRANSLATE;
    }
  dgprintf(5,"MDMA CTL: %08x\n", rc);
  DSLHAL_REG32(rc) = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
                         DEV_MDMA_BURST1 | (1 << DEV_MDMA_LEN_SHF));
  /* statusMask = 0x00000010;*/
#else
  dgprintf(4, "dslhal_support_unresetDsp()\n");

  /* Bring the DSP core out of reset */
  /* DSLHAL_REG32(0xa8611600) = 0x00ff1bdf; */
  DSLHAL_REG32(REG_PRCR) |= PRCR_DSP;
//  shim_osClockWait(64);
  dgprintf(5,"Brought DSP out of Reset \n");

  /* DSLHAL_REG32(0xa8611a0c) = 0x00000007;
     shim_osClockWait(64); */
#endif

  dgprintf(4, "dslhal_support_unresetDsp() done\n");
  return DSLHAL_ERROR_NO_ERRORS;
}


/******************************************************************************************
* FUNCTION NAME:     dslhal_support_resetDslSubsystem
*
*******************************************************************************************
* DESCRIPTION: This function unreset Dsl Subsystem
*
* INPUT:  None
*
* RETURN: 0 if Pass; 1 if Fail
*
*****************************************************************************************/
int  dslhal_support_resetDslSubsystem(void)
{
  dgprintf(4, "dslhal_support_resetDslSubsystem \n");
  /* Put ADSLSS into reset */
  DSLHAL_REG32(REG_PRCR) &= ~PRCR_ADSLSS;
  shim_osClockWait(64);
  /*  DSLHAL_REG32(0xa8611a04) = 0x00000000;
      shim_osClockWait(64); */
  dgprintf(4, "dslhal_support_resetDslSubsystem Done \n");
  return DSLHAL_ERROR_NO_ERRORS;
}


/******************************************************************************************
* FUNCTION NAME:    dslhal_support_resetDsp()
*
*******************************************************************************************
* DESCRIPTION: This fuction takes ax5 daugter board into reset.
*
* INPUT:  None
*
* RETURN: 0  --successful.
*         1  --failed
*
*****************************************************************************************/
int dslhal_support_resetDsp(void)
{
  dgprintf(4, "dslhal_support_resetDsp \n");
  /* Put ADSLSS into reset */
  DSLHAL_REG32(REG_PRCR) &= ~PRCR_DSP;
  shim_osClockWait(64);
  dgprintf(4, "dslhal_support_resetDsp Done \n");
  return DSLHAL_ERROR_NO_ERRORS;
}


void dslhal_csl_clearInterrupt()
{
  /* Clear out the DSLSS Interrupt Registers to acknowledge Interrupt */
  if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_MAILBOX_INTERRUPTS)
  {
    DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_MAILBOX_INTERRUPTS;
    dgprintf(5,"Mailbox Interrupt \n");
  }
  if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_BITFIELD_INTERRUPTS)
  {
    DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_BITFIELD_INTERRUPTS;
    dgprintf(5,"Bitfield Interrupt \n");
  }
  if(DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_SOURCE_REGISTER))&MASK_HEARTBEAT_INTERRUPTS)
  {
    DSLHAL_REG32(dslhal_support_hostDspAddressTranslate(DSP_INTERRUPT_CLEAR_REGISTER))|=MASK_HEARTBEAT_INTERRUPTS;
    dgprintf(5,"HeartBeat Interrupt \n");
  }
}

#endif