/** * \file dsl_hal_csl.h * * \author Copyright (C) 2001-2006 Texas Instruments Incorporated. * * \brief This file contains DSL HAL CSL definitions for DSL device driver. * * \date 23Feb07 0.00.01 EP CQ11512: Added DSLSS peripherals. */ #ifndef __DSL_HAL_CSL_H__ #define __DSL_HAL_CSL_H__ 1 #ifdef offsetof #define OFFSET32(T, M) (offsetof(T, M) >> 2) #else #define OFFSET32(T, M) (((unsigned) &((T*)0)->M) >> 2) #endif /*** Define Bit Masks ***/ #define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004 #define BIT3 0x00000008 #define BIT4 0x00000010 #define BIT5 0x00000020 #define BIT6 0x00000040 #define BIT7 0x00000080 #define BIT8 0x00000100 #define BIT9 0x00000200 #define BIT10 0x00000400 #define BIT11 0x00000800 #define BIT12 0x00001000 #define BIT13 0x00002000 #define BIT14 0x00004000 #define BIT15 0x00008000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000 //#define BIT#i (1<<(i)) #ifndef NULL #define NULL 0 #endif #ifndef TRUE #define TRUE (1==1) #endif #ifndef FALSE #define FALSE (1==2) #endif #ifdef DEBUG_BUILD #define dgprintf dprintf #else #define dgprintf(uDbgLevel, szFmt, args...) #endif enum { DSLHAL_ERROR_NO_ERRORS, /* 00 */ DSLHAL_ERROR_UNRESET_ADSLSS, /* 01 */ DSLHAL_ERROR_RESET_ADSLSS, /* 02 */ DSLHAL_ERROR_UNRESET_DSP, /* 03 */ DSLHAL_ERROR_RESET_DSP, /* 04 */ DSLHAL_ERROR_NO_FIRMWARE_IMAGE, /* 05 */ DSLHAL_ERROR_MALLOC, /* 06 */ DSLHAL_ERROR_FIRMWARE_MALLOC, /* 07 */ DSLHAL_ERROR_DIAG_MALLOC, /* 08 */ DSLHAL_ERROR_OVERLAY_MALLOC, /* 09 */ DSLHAL_ERROR_CODE_DOWNLOAD, /* 10 */ DSLHAL_ERROR_DIAGCODE_DOWNLOAD, /* 11 */ DSLHAL_ERROR_BLOCK_READ, /* 12 */ DSLHAL_ERROR_BLOCK_WRITE, /* 13 */ DSLHAL_ERROR_MAILBOX_READ, /* 14 */ DSLHAL_ERROR_MAILBOX_WRITE, /* 15 */ DSLHAL_ERROR_MAILBOX_NOMAIL, /* 16 */ DSLHAL_ERROR_MAILBOX_OVERFLOW, /* 17 */ DSLHAL_ERROR_INVALID_PARAM, /* 18 */ DSLHAL_ERROR_ADDRESS_TRANSLATE, /* 19 */ DSLHAL_ERROR_FIRMWARE_CRC, /* 20 */ DSLHAL_ERROR_FIRMWARE_OFFSET, /* 21 */ DSLHAL_ERROR_CONFIG_API_FAILURE, /* 22 */ DSLHAL_ERROR_EOCREG_API_FAILURE, /* 23 */ DSLHAL_ERROR_VERSION_API_FAILURE, /* 24 */ DSLHAL_ERROR_STATS_API_FAILURE, /* 25 */ DSLHAL_ERROR_MARGIN_API_FAILURE, /* 26 */ DSLHAL_ERROR_CTRL_API_FAILURE, /* 27 */ DSLHAL_ERROR_HYBRID_API_FAILURE, /* 28 */ DSLHAL_ERROR_MODEMENV_API_FAILURE, /* 29 */ DSLHAL_ERROR_INTERRUPT_FAILURE, /* 30 */ DSLHAL_ERROR_INTERNAL_API_FAILURE, /* 31 */ DSLHAL_ERROR_DIGIDIAG_FAILURE, /* 32 */ DSLHAL_ERROR_TONETEST_FAILURE, /* 33 */ DSLHAL_ERROR_NOISETEST_FAILURE, /* 34 */ DSLHAL_ERROR_MODEMSTATE, /* 35 */ DSLHAL_ERROR_OVERLAY_CORRUPTED, /* 36 */ DSLHAL_ERROR_UNSUPPORTED_MODE, /* 37 */ DSLHAL_ERROR_GENERAL_FAILURE, /* 38 */ }; /*** Endianness ***/ /*i=0: LSB*/ #define OCTET(d, i) (((d) >> (((i)&3)<<3)) & 0x0FF) #ifdef EB #define BYTE_SWAP16(d) ((OCTET(d,0)<<8) | OCTET(d,1)) #define BYTE_SWAP32(d) ((OCTET(d,0)<<24)|(OCTET(d,1)<<16)|(OCTET(d,2)<<8)|OCTET(d,3)) #define SHORT_SWAP32(d) ((OCTET(d,1)<<24)|(OCTET(d,0)<<16)|(OCTET(d,3)<<8)|OCTET(d,2)) #define BYTE_GET(d, i) OCTET(d, (3-(i))) #else #define BYTE_SWAP16(d) (d) #define BYTE_SWAP32(d) (d) #define SHORT_SWAP32(d) (d) #define BYTE_GET(d, i) OCTET(d, i) #endif #define dslhal_support_byteSwap32(d) BYTE_SWAP32(d) #define dslhal_support_byteSwap16(d) BYTE_SWAP16(d) #define dslhal_support_shortSwap32(d) SHORT_SWAP32(d) /*TBD: Legacy support*/ #define dslhal_support_byteSwap32_BE dslhal_support_byteSwap32 #define HOST_MEM_V2P(x) (((x) & 0x1FFFFFFF) | 0xA0000000) #ifdef YAMUNA #ifdef VOLCANO #define DSP_RST_WORKAROUND /*work-around*/ #define DSLHAL_REG_DELAY 640 #else #define DSLHAL_REG_DELAY 64 #endif /*LEGACY*/ #define ADSLSS_PRCR_BASE (HOST_MEM_DSL_BASE | 0x0500) #define REG_ADSLSS_PRCR (ADSLSS_PRCR_BASE | 0x00) #define ADSLSS_PRCR_DSL_SPA 0x2 /******************************************************************************* * HOST Memory Map (Yamuna) *******************************************************************************/ #define HOST_MEM_DSL_BASE HOST_MEM_V2P(0x0100<<16) /* DSLSS Peripheral */ #define HOST_MEM_DSP_BASE HOST_MEM_V2P(0x01C0<<16) /* DSP DMEM */ #define HOST_MEM_REG_BASE HOST_MEM_V2P(0x0861<<16) /* HOST Peripheral */ /******************************************************************************* * DSLSS Register * * HOST: 0xA100:0000 * DSLSS: 0x0200:0000 *******************************************************************************/ #define DEV_MDMA_BASE (HOST_MEM_DSL_BASE | 0x0300) #define DEV_MDMA0_CTL_ADDR (DEV_MDMA_BASE | 0x08) #define DEV_MDMA1_CTL_ADDR (DEV_MDMA_BASE | 0x48) #define DEV_MDMA2_CTL_ADDR (DEV_MDMA_BASE | 0x88) #define DEV_MDMA3_CTL_ADDR (DEV_MDMA_BASE | 0xC8) #define DEV_PERIPH_PRCR_BASE (HOST_MEM_DSL_BASE | 0x0500) #define DEV_PERIPH_PRCR_424M BIT0 #define DEV_PERIPH_PRCR_360M BIT1 #define DEV_PERIPH_PRCR_DI BIT2 #define DEV_PERIPH_PRCR_NTR0 BIT3 #define DEV_PERIPH_PRCR_NTR1 BIT4 #define DEV_PERIPH_PRCR_ATMTC BIT5 #define DEV_PERIPH_PRCR_McDMA BIT6 #define DEV_PERIPH_PRCR_INT_CTRL BIT7 #define DEV_PERIPH_PRCR_UART BIT8 #define DSLSS_INTR_CTRL_BASE (HOST_MEM_DSL_BASE | 0x0600) #define DSP_INTR_SRC_REGISTER (DSLSS_INTR_CTRL_BASE | 0xA0) #define DSP_INTR_CLR_REGISTER (DSLSS_INTR_CTRL_BASE | 0xA4) #define MASK_INTR_MAILBOX BIT0 #define MASK_INTR_BITFIELD BIT1 #define MASK_INTR_HEARTBEAT BIT2 #define MASK_INTR_ALL (BIT0 | BIT1 | BIT2) #define DEV_PERIPH_DSPSS_REG_BASE (HOST_MEM_DSL_BASE | 0x80000) #define DEV_DSPSS_PRCONT_ADDR (DEV_PERIPH_DSPSS_REG_BASE | 0x14) /******************************************************************************/ /******************************************************************************* * HOST Register *******************************************************************************/ //GPIO Registers #define GPIO_BASE (HOST_MEM_REG_BASE + 0x0900) #define REG_GPIOENR (GPIO_BASE + 0x0C) /* GPIO Enable Register */ #define REG_CVR (GPIO_BASE + 0x14) /* Chip Version Register */ #define REG_DIDR1 (GPIO_BASE + 0x18) /* Die ID Register (low 32bit) */ #define REG_DIDR2 (GPIO_BASE + 0x1C) /* Die ID Register (high 32bit) */ //PDCR: Peripheral Power Down Register #define PDCR_BASE (HOST_MEM_REG_BASE + 0x0A00) #define REG_PDCR (PDCR_BASE + 0x00) //Selective Bit definitions for the PDCR Register #define PDCR_SARP 0x00000100 /* SAR Power Down Bit */ #define PDCR_ADSLP 0x00000200 /* ADSLSS Power Down Bit */ #define PDCR_ADSPP 0x00001000 /* DSP Power Down Bit */ // PRCR: Peripheral Reset Control Register #define PRCR_BASE (HOST_MEM_REG_BASE + 0x1600) #define REG_PRCR (PRCR_BASE + 0x00) // definitions for PRCR #define PRCR_UART0 BIT0 #define PRCR_I2C BIT1 #define PRCR_GPIO BIT6 #define PRCR_ADSLSS BIT7 #define PRCR_USB BIT8 #define PRCR_SAR BIT9 #define PRCR_EMAC1 BIT21 #define PRCR_DSP BIT23 /* Device Config Latch (DCL) */ #define DCL_BASE (HOST_MEM_REG_BASE + 0x1A00) #define REG_BOOTCR (DCL_BASE + 0x00) #define REG_PM2EMIF (DCL_BASE + 0x10) #define REG_DM2EMIF (DCL_BASE + 0x14) #define REG_MIPS2PERIPH (DCL_BASE + 0x5C) #define REG_MIPS2DMEM (DCL_BASE + 0x60) /* Interrupt Controller Register */ #define INTC_BASE (HOST_MEM_REG_BASE + 0x2400) #define REG_INTC_INTSR1 (INTC_BASE) /* Interrupt Status/Mask Reg 1 */ #define REG_INTC_INTSR2 (INTC_BASE + 0x04) /* Interrupt Status/Mask Reg 2 */ #define REG_INTC_INTCR1 (INTC_BASE + 0x10) /* Interrupt Clear/Raw Reg 1*/ #define REG_INTC_INTCR2 (INTC_BASE + 0x14) /* Interrupt Clear/Raw Reg 2*/ #define REG_INTC_INTESR1 (INTC_BASE + 0x20) /* Interrupt Enable Set Register 1 */ #define REG_INTC_INTESR2 (INTC_BASE + 0x24) /* Interrupt Enable Set Register 2 */ #define REG_INTC_INTTYPR1 (INTC_BASE + 0x60) /* Interrupt Type Register1 */ #define REG_INTC_INTTYPR2 (INTC_BASE + 0x64) /* Interrupt Type Register2 */ /******************************************************* * Interrupt sources. * The reserved sources are noted. *******************************************************/ #define INTR_CNTRL_SRC_SECOND 0 #define INTR_CNTRL_SRC_EXTERNAL0 1 #define INTR_CNTRL_SRC_EXTERNAL1 2 /* reserved sources ... */ #define INTR_CNTRL_SRC_TIMER0 5 #define INTR_CNTRL_SRC_TIMER1 6 #define INTR_CNTRL_SRC_UART0 7 #define INTR_CNTRL_SRC_UART1 8 #define INTR_CNTRL_SRC_DMA0 9 #define INTR_CNTRL_SRC_DMA1 10 /* reserved sources ... */ #define INTR_CNTRL_SRC_SAR 15 /* reserved sources ... */ #define INTR_CNTRL_SRC_EMAC0 19 /* reserved sources ... */ #define INTR_CNTRL_SRC_VLYNQ0 21 #define INTR_CNTRL_SRC_CODEC_WAKE 22 /* reserved sources ... */ #define INTR_CNTRL_SRC_USB 24 #define INTR_CNTRL_SRC_VLYNQ1 25 /* reserved sources ... */ #define INTR_CNTRL_SRC_EMAC1 28 #define INTR_CNTRL_SRC_I2C 29 #define INTR_CNTRL_SRC_DMA2 30 #define INTR_CNTRL_SRC_DMA3 31 /* reserved sources ... */ #define INTR_CNTRL_SRC_VDMA_RX 37 #define INTR_CNTRL_SRC_VDMA_TX 38 #define INTR_CNTRL_SRC_ADSLSS_SANGAM 39 /* for Sangam */ #define INTR_CNTRL_SRC_ADSLSS_OHIO 23 /* for Ohio */ /******************************************************************************/ /******************************************************************************* * DSP Access HOST Access * PMEM 0x1000:0000 | PMEM[27:6] + PM2EMIF[27:6] | PMEM[5:0] * DMEM 0x1000:0000 | DMEM[27:6] + DM2EMIF[27:6] | DMEM[5:0] * CPSS CPSS[27:0] *******************************************************************************/ #define DSP_CS_MASK 0xf0000000 #define DSP_PMEM_CS 0x00000000 #define DSP_DMEM_CS 0x10000000 #define DSP_CPSS_CS 0x20000000 #define DSP_TO_HOST_CS(addr) ((addr & DSP_CS_MASK)) #define DSP_TO_HOST_AD(addr) ((addr & ~DSP_CS_MASK)) #define DSP_TO_HOST_PMEM(addr) (DSP_TO_HOST_CS(addr) == DSP_PMEM_CS) #define DSP_TO_HOST_DMEM(addr) (DSP_TO_HOST_CS(addr) == DSP_DMEM_CS) #define DSP_TO_HOST_CPSS(addr) (DSP_TO_HOST_CS(addr) == DSP_CPSS_CS) #define HOST_MEM_DSP_CS 0x10000000 #ifdef PLATFORM #define CHIP_ID (DSLHAL_REG32(REG_CVR) & 0xFFFF) #else #define CHIP_ID 0x002B #endif #define PM2EMIF_OFFSET 0x05000000 #define DM2EMIF_OFFSET 0x05000000 #define DSL_GET32_RAW(a) (*(volatile unsigned int *)(HOST_MEM_V2P(a))) /* TBD -ep20060216 * AR7 chip does HW endian conversion, so SW conversion is done to reverse it. * if Yamuna chip does not do HW conversion, then SW should not reverse. */ #define DSL_GET32(a) BYTE_SWAP32(DSL_GET32_RAW(a)) #define DSL_SET32(a,d) (DSL_GET32_RAW(a) = BYTE_SWAP32(d)) #define HOST_REG(a) *(volatile unsigned int *)(a) #define DSLHAL_REG32 HOST_REG #else /*YAMUNA*/ #include #define DSL_GET32(a) BYTE_SWAP32(DSLHAL_REG32(a)) #define DSL_SET32(a,d) (DSLHAL_REG32(a) = BYTE_SWAP32(d)) #endif /******************************************************************************* ** Local *******************************************************************************/ #define MASK_MAILBOX_INTERRUPTS BIT0 #define MASK_BITFIELD_INTERRUPTS BIT1 #define MASK_HEARTBEAT_INTERRUPTS BIT2 /******************************************************************************* * Prototype *******************************************************************************/ void dslhal_csl_clearInterrupt(void); /****************************************************************************************** * FUNCTION NAME: dslhal_support_hostDspAddressTranslate * ******************************************************************************************* * DESCRIPTION: This function moves the address window to translate physical address * * INPUT: unsigned int addr : address that requires translation * * RETURN: Translated address or error condition * * *****************************************************************************************/ unsigned int dslhal_support_hostDspAddressTranslate ( unsigned int addr); /****************************************************************************************** * FUNCTION NAME: dslhal_support_unresetDslSubsystem * ******************************************************************************************* * DESCRIPTION: This function unreset Dsl Subsystem * * INPUT: None * * RETURN: 0 if Pass; 1 if Fail * *****************************************************************************************/ int dslhal_support_unresetDslSubsystem (void); /****************************************************************************************** * FUNCTION NAME: dslhal_support_unresetDsp() * ******************************************************************************************* * DESCRIPTION: This fuction takes ax5 daugter board out of reset. * * INPUT: None * * RETURN: 0 --successful. * 1 --failed * *****************************************************************************************/ int dslhal_support_unresetDsp (void); /****************************************************************************************** * FUNCTION NAME: dslhal_support_resetDslSubsystem * ******************************************************************************************* * DESCRIPTION: This function unreset Dsl Subsystem * * INPUT: None * * RETURN: 0 if Pass; 1 if Fail * *****************************************************************************************/ int dslhal_support_resetDslSubsystem (void); /****************************************************************************************** * FUNCTION NAME: dslhal_support_resetDsp() * ******************************************************************************************* * DESCRIPTION: This fuction takes ax5 daugter board out of reset. * * INPUT: None * * RETURN: 0 --successful. * 1 --failed * *****************************************************************************************/ int dslhal_support_resetDsp (void); /** * OS-dependent Function Prototype Declarations */ unsigned DDA_dsl_DspImageAddrGet(void); #ifdef NOT_DRV_BUILD extern unsigned int shim_osGetCpuFrequency(void); extern void shim_osClockWait(int val); extern unsigned int shim_osClockTick(void); extern int shim_osStringCmp(const char *s1, const char *s2); extern void dprintf( int uDbgLevel, char * szFmt, ...); extern int shim_osLoadFWImage(unsigned char *firmwareImage); extern int shim_osLoadDebugFWImage(unsigned char *debugFirmwareImage); extern unsigned int shim_read_overlay_page(void *ptr, unsigned int secOffset, unsigned int secLength); extern void shim_osMoveMemory(char *dst, char *src, unsigned int numBytes); extern void shim_osZeroMemory(char *dst, unsigned int numBytes); extern void *shim_osAllocateMemory(unsigned int size); extern void *shim_osAllocateVMemory(unsigned int size); extern void *shim_osAllocateDmaMemory(unsigned int size); extern void shim_osFreeMemory(void *ptr, unsigned int size); extern void shim_osFreeVMemory(void *ptr, unsigned int size); extern void shim_osFreeDmaMemory(void *ptr, unsigned int size); extern void shim_osWriteBackCache(void *pMem, unsigned int size); extern void shim_osCriticalEnter(void); extern void shim_osCriticalExit(void); #else /* TBD: replace "shim_os" with "DDA_" */ extern unsigned int shim_osGetCpuFrequency(void); extern void shim_osClockWait(int val); extern unsigned int shim_osClockTick(void); extern int shim_osStringCmp(const char *s1, const char *s2); extern void dprintf( int uDbgLevel, char * szFmt, ...); extern int shim_osLoadFWImage(unsigned char *firmwareImage); extern int shim_osLoadDebugFWImage(unsigned char *debugFirmwareImage); extern unsigned int shim_read_overlay_page(void *ptr, unsigned int secOffset, unsigned int secLength); extern void shim_osMoveMemory(char *dst, char *src, unsigned int numBytes); extern void shim_osZeroMemory(char *dst, unsigned int numBytes); extern void *shim_osAllocateMemory(unsigned int size); extern void *shim_osAllocateVMemory(unsigned int size); extern void *shim_osAllocateDmaMemory(unsigned int size); extern void shim_osFreeMemory(void *ptr, unsigned int size); extern void shim_osFreeVMemory(void *ptr, unsigned int size); extern void shim_osFreeDmaMemory(void *ptr, unsigned int size); extern void shim_osWriteBackCache(void *pMem, unsigned int size); extern void shim_osCriticalEnter(void); extern void shim_osCriticalExit(void); #endif /*NOT_DRV_BUILD*/ #endif /*__DSL_HAL_CSL_H__*/