#ifndef ___DSL_REGISTER_DEFINES_H___ #define ___DSL_REGISTER_DEFINES_H___ 1 /******************************************************************************* * FILE PURPOSE: DSL HAL H/W Registers and Constant Declarations for Sangam * ******************************************************************************** * FILE NAME: dsl_hal_register.h * * DESCRIPTION: * Contains DSL HAL APIs for Adam2 OS functions * * * (C) Copyright 2001-02, Texas Instruments, Inc. * History * Date Version Notes * 06Feb03 0.00.00 RamP Created * 21Mar03 0.00.01 RamP Changed header files for Modular * build framework * 21Mar03 0.00.02 RamP Introduced malloc size for DSP f/w * 07Apr03 0.00.03 RamP Implemented new error reporting scheme * Changed Commenting to C style only * 12Apr03 0.00.04 RamP Added Interrupt Mask defines * 14Apr03 0.00.05 RamP Renamed macros for REG8, REG16 & REG32 * 21Apr03 0.01.00 RamP Added Interrupt source/clear registers * Changed enum RSTATE_SHOWTIME to 5 * 24Apr03 0.01.01 RamP Moved the RSTATE enum to api.h * Added olay recovery error condition * 14May03 0.01.02 RamP Added defines for power computation * Added error condition for hybrids * 04Jun03 0.01.03 RamP Added enum for config flags, * Cleaned up AR5 register defines * Added defines for higher data rate * 06Jun03 0.01.04 RamP Added error & interrupt defines * 09Jun03 0.01.05 RamP Modified enum for current config * Added additional C-Rates defines * 18Jul03 0.01.06 RamP Modified internal build flow * 21Aug03 0.01.07 RamP Added constellation buffer size * 08Oct03 0.01.08 RamP Added us/ds Bits n gains size * 12Oct03 0.01.08 RamP Added ADSL2 Message sizes, lengths * and offsets for various formats * 29Oct03 0.01.09 RamP Added ADSL2 Delt offsets & sizes * 24Nov03 0.01.10 RamP Added bit field number, scan vector * 26Dec03 0.01.11 RamP Removed the oamFeature masks to api.h * 31Mar04 0.01.12 RamP Fixed length for RMSGPCB2L DELT message * Increased Max Sections to 400 * 20Apr04 0.01.12 RamP Increased Max Sections for ADSL2Plus * * 29Apr04 0.01.13 RamP Added indices for ADSL2+ DELT messages * Fixed length for RMSGPCB2L DELT message * Fixed index for RMSGPCB2PL message * 30Jun04 0.02.00 RamP Added register definitions for Ohio s/w * 27Jan05 0.02.01 CPH Added Ohio250 support & cleanup. * 02Feb05 0.02.02 CPH Remove DSLHAL_REG8() & DSLHAL_REG16() as * they are not endian neutral. * 21Feb05 0.02.03 CPH Pull included files out from this file so other * modules can use this file without catch * 01Apr05 0.02.04 CPH Added REG_SYSTEM_POSTDIV2 & * 20Jul05 0.02.05 AV Added Register definitions for the * PDCR:Peripheral Power Down Register and * the ADSLADR1, ADSLADR2 and ADSLADR3 Registers. * 17June05 0.02.05 CPH Resync datapump Msg Index (ctrl_msm_decl.h) * This fixed AnxdB ADSL2/2+ host crash problem. * 18July05 0.02.05 CPH CQ9600 Sync Training msg Index with ctrl_msm_decl.h. * 29July05 0.02.06 CPH Remove US_BNG_LENGTH & DS_BNG_LENGTH. * 05Sept05 0.02.07 CPH Added DSLHAL_ERROR_UNSUPPORTED_MODE & DSLHAL_ERROR_GENERAL_FAILURE. *******************************************************************************/ //#include //#ifdef INTERNAL_BUILD //#include //#endif //#include //#include #ifdef YAMUNA #include #else #define ADSLSS_BASE 0x01000000 #define ADSLSS2_BASE 0x01800000 #define ADSLSS3_BASE 0x01c00000 #define BBIF_BASE 0x02000000 #define ADSLSSADR (BBIF_BASE+0x0000) #define ADSLSSADR2 (BBIF_BASE+0x0004) #define ADSLSSADR3 (BBIF_BASE+0x0008) #define ADSLSSADRMASK 0xff000000 #define DSP_PMEM_MASK 0x00000000 #define DSP_DMEM_MASK 0x80000000 #define WAKEUP_DSP 0x00000001 enum CHIP_ID { CHIP_AR7 =0x05, /* Sangam Chip ID */ CHIP_AR7O_212 =0x18, /* Ohio212 Chip ID */ CHIP_AR7O_250_212 =0x2B /* Ohio250/Ohio212(new) Chip ID */ }; #define DSP_PRPH_START_ADDR 0xA1000000 #define DSP_PMEM_START_ADDR 0xA1800000 #define DSP_DMEM_START_ADDR 0xA1C00000 #define ADSLSS_PRCR_BASE 0xA1000600 /* DSP:0x02000600 */ #define REG_ADSLSS_PRCR (ADSLSS_PRCR_BASE + 0x00) #define ADSLSS_PRCR_DSL_SPA 0x40 #define ADSLADR_BASE 0xA2000000 #define ADSLADR1 (ADSLADR_BASE + 0) #define ADSLADR2 (ADSLADR_BASE + 4) #define ADSLADR3 (ADSLADR_BASE + 8) /* Codec Registers */ #define CODEC_BASE 0xa1040000 #define REG_CODEC_CTRL2 (CODEC_BASE+0x10) /* CTRL1,CTRL2,CTRL3,CTRL4: CTRL2 is byte1 */ #define REG_BUCKTRIM_PWD (CODEC_BASE+0x64) /* BuckTrimPwd is byte 3 */ #define REG_BUCKTRIM_READ (CODEC_BASE+0x18) /* BuckTrim Read is byte 1(offset 0x19), bit 2:0 */ #define DSP_INTERRUPT_SOURCE_REGISTER 0x020007A0 #define DSP_INTERRUPT_CLEAR_REGISTER 0x020007A4 //GPIO Registers #define GPIO_BASE 0xA8610900 #define REG_GPIOENR (GPIO_BASE + 0x0C) /* GPIO Enable Register */ #define REG_CVR (GPIO_BASE + 0x14) /* Chip Version Register */ #define REG_DIDR1 (GPIO_BASE + 0x18) /* Die ID Register (low 32bit) */ #define REG_DIDR2 (GPIO_BASE + 0x1C) /* Die ID Register (high 32bit) */ // PRCR: Peripheral Reset Control Register #define PRCR_BASE 0xA8611600 #define REG_PRCR (PRCR_BASE + 0x00) // definitions for PRCR #define PRCR_UART0 0x00000001 #define PRCR_I2C 0x00000002 #define PRCR_GPIO 0x00000040 #define PRCR_ADSLSS 0x00040080 #define PRCR_USB 0x00000100 #define PRCR_SAR 0x00000200 #define PRCR_DSP 0x00800000 #define PRCR_EMAC1 0x00200000 /* EMAC1 reset */ #define PRCR_ADSLSS_ONLY 0x00000080 //PDCR: Peripheral Power Down Register #define PDCR_BASE 0xA8610A00 #define REG_PDCR (PDCR_BASE + 0x00) //Selective Bit definitions for the PDCR Register #define PDCR_SARP 0x00000100 /* SAR Power Down Bit */ #define PDCR_ADSLP 0x00000200 /* ADSLSS Power Down Bit */ #define PDCR_ADSPP 0x00001000 /* DSP Power Down Bit */ /* Ohio Registers */ #define MIPS_PLL_BASE 0xa8610a80 /* MIPS PLL base address */ #define REG_MIPS_PLLCSR (MIPS_PLL_BASE) #define REG_MIPS_PLLM (MIPS_PLL_BASE + 0x10) #define REG_MIPS_PREDIV (MIPS_PLL_BASE + 0x14) #define REG_MIPS_POSTDIV (MIPS_PLL_BASE + 0x18) #define REG_MIPS_PLLCMD (MIPS_PLL_BASE + 0x38) #define REG_MIPS_PLLSTAT (MIPS_PLL_BASE + 0x3c) #define REG_MIPS_PLLCMDEN (MIPS_PLL_BASE + 0x40) #define DIVEN 0x00008000 #define GOSTAT 0x00000001 #define PLLEN 0x00000001 #define GOSET 0x00000001 #define GOSET2 0x00000002 /* GOSET for REG_SYSTEM_POSTDIV2 */ #define GOSETEN 0x00000001 #define GOSETEN2 0x00000002 /* GOSETEN for REG_SYSTEM_POSTDIV2 */ #define SYSTEM_PLL_BASE 0xa8610b00 /* System PLL base addr */ #define REG_SYSTEM_PLLCSR (SYSTEM_PLL_BASE) #define REG_SYSTEM_PLLM (SYSTEM_PLL_BASE + 0x10) #define REG_SYSTEM_PREDIV (SYSTEM_PLL_BASE + 0x14) #define REG_SYSTEM_POSTDIV (SYSTEM_PLL_BASE + 0x18) #define REG_SYSTEM_POSTDIV2 (SYSTEM_PLL_BASE + 0x1C) #define REG_SYSTEM_PLLCMD (SYSTEM_PLL_BASE + 0x38) #define REG_SYSTEM_PLLSTAT (SYSTEM_PLL_BASE + 0x3C) #define REG_SYSTEM_PLLCMDEN (SYSTEM_PLL_BASE + 0x40) //Clock multiplier to get 212 MHz from MIPS PLL #define OHIO_MIPS_PLLM_RATIO 5 // bit definition for REG_SYSTEM_POSTDIV2 #define OHIO_SYS_POSTDIV2_RATIO 0 // bit definition for REG_SYSTEM_PLLM #define OHIO_SYS_PLLM_RATIO 9 #define REG_VSERCLKSELR 0xa8611a10 // bit definition for REG_VSERCLKSELR #define OHIO_250_MODE 0x100 #define REG_PLL_TEST 0xa8611a0c /* Interrupt Controller Register */ #define INTC_BASE 0xa8612400 /* Interrupt Controller Base addr */ #define REG_INTC_INTSR1 (INTC_BASE) /* Interrupt Status/Mask Reg 1 */ #define REG_INTC_INTSR2 (INTC_BASE + 0x04) /* Interrupt Status/Mask Reg 2 */ #define REG_INTC_INTCR1 (INTC_BASE + 0x10) /* Interrupt Clear/Raw Reg 1*/ #define REG_INTC_INTCR2 (INTC_BASE + 0x14) /* Interrupt Clear/Raw Reg 2*/ #define REG_INTC_INTESR1 (INTC_BASE + 0x20) /* Interrupt Enable Set Register 1 */ #define REG_INTC_INTESR2 (INTC_BASE + 0x24) /* Interrupt Enable Set Register 2 */ #define REG_INTC_INTTYPR1 (INTC_BASE + 0x60) /* Interrupt Type Register1 */ #define REG_INTC_INTTYPR2 (INTC_BASE + 0x64) /* Interrupt Type Register2 */ /******************************************************* Interrupt sources on Ax7 interrupt controller. The reserved sources are noted. *******************************************************/ #define INTR_CNTRL_SRC_SECOND 0 #define INTR_CNTRL_SRC_EXTERNAL0 1 #define INTR_CNTRL_SRC_EXTERNAL1 2 /* reserved sources ... */ #define INTR_CNTRL_SRC_TIMER0 5 #define INTR_CNTRL_SRC_TIMER1 6 #define INTR_CNTRL_SRC_UART0 7 #define INTR_CNTRL_SRC_UART1 8 #define INTR_CNTRL_SRC_DMA0 9 #define INTR_CNTRL_SRC_DMA1 10 /* reserved sources ... */ #define INTR_CNTRL_SRC_SAR 15 /* reserved sources ... */ #define INTR_CNTRL_SRC_EMAC0 19 /* reserved sources ... */ #define INTR_CNTRL_SRC_VLYNQ0 21 #define INTR_CNTRL_SRC_CODEC_WAKE 22 /* reserved sources ... */ #define INTR_CNTRL_SRC_USB 24 #define INTR_CNTRL_SRC_VLYNQ1 25 /* reserved sources ... */ #define INTR_CNTRL_SRC_EMAC1 28 #define INTR_CNTRL_SRC_I2C 29 #define INTR_CNTRL_SRC_DMA2 30 #define INTR_CNTRL_SRC_DMA3 31 /* reserved sources ... */ #define INTR_CNTRL_SRC_VDMA_RX 37 #define INTR_CNTRL_SRC_VDMA_TX 38 #define INTR_CNTRL_SRC_ADSLSS_SANGAM 39 /* for Sangam */ #define INTR_CNTRL_SRC_ADSLSS_OHIO 23 /* for Ohio */ #ifndef K0BASE #define K0BASE 0x80000000 #endif #ifndef K1BASE #define K1BASE 0xA0000000 #endif #ifndef PHYS_ADDR #define PHYS_ADDR(X) ((X) & 0X1FFFFFFF) #endif #ifndef PHYS_TO_K0 #define PHYS_TO_K0(X) (PHYS_ADDR(X)|K0BASE) #endif #ifndef PHYS_TO_K1 #define PHYS_TO_K1(X) (PHYS_ADDR(X)|K1BASE) #endif #ifndef DSLHAL_REG32 #define DSLHAL_REG32( addr ) (*(volatile unsigned int *)PHYS_TO_K1(addr)) #endif /******************************************************************************* * Type Defines for Library ********************************************************************************/ #define TIDSL_HW_CREATED 0x00000001 #define TIDSL_HW_OPENED 0x00000002 #define TIDSL_HW_STARTED 0x00000004 #define TIDSL_OS_INITIALIZED 0x00000008 #define virtual2Physical(a) (((int)a)&~0xe0000000) #endif /*YAMUNA*/ #endif /* pairs #ifndef ___DSL_REGISTER_DEFINES_H___ */