/** * \file dsl_hal_support.h * * \author Copyright (C) 2001-2006 Texas Instruments Incorporated. * * \brief This file contains DSL HAL support function definitions. * * \date 23Feb07 0.00.09 EP CQ11512: Added API for retrieving DSP heartbeat info. */ #ifndef DSL_HAL_SUPPORT_H__ #define DSL_HAL_SUPPORT_H__ 1 #include #include #ifdef NOT_DRV_BUILD #include #endif /*** Primary ***/ /** * \brief HOST-DSP mailbox communication message handling. * * @param ptidsl Pointer to main DSL HAL data structure. * @return ErrCode */ unsigned dslhal_support_processMailBox(tidsl_t *ptidsl, unsigned intFlag); unsigned dslhal_support_readDspMailbox (tidsl_t *ptidsl, int *pcmd, int *ptag, int *pprm1, int *pprm2); unsigned dslhal_support_writeHostMailbox (tidsl_t *ptidsl, int cmd, int tag, int p1, int p2); unsigned dslhal_support_processModemStateBitField (tidsl_t *ptidsl); unsigned dslhal_support_parseInterruptSource(tidsl_t *ptidsl, unsigned *intrSrc); /*** Data Logging ***/ #define NUM_TONE_DS_DEFAULT 256 #define NUM_TONE_DS_ADSL2PLUS 512 #define NUM_TONE_US_DEFAULT 32 #define NUM_TONE_US_ADSL_B 64 /* Data Pump CRATES Table Defines */ #define SIZE_OF_CRATES1_TABLE 120 #define CRATES1_BF_LS0 7 #define CRATES1_BI_LS0 17 #define CRATES1_BF_AS0 0 #define CRATES1_BI_AS0 10 #define CRATES1_BF_DSRS 20 #define CRATES1_BI_DSRS 21 #define CRATES1_BFI_DSS 22 #define CRATES1_BFI_DSI 23 #define CRATES1_BF_USRS 25 #define CRATES1_BI_USRS 26 #define CRATES1_BFI_USS 27 #define CRATES1_BFI_USI 28 #define FAST_PATH 0 #define INTERLEAVED_PATH 1 #define LINE_NOT_CONNECTED 0 #define LINE_CONNECTED 1 #define LINE_DISCONNECTED 2 #define LINE_NOT_TO_CONNECT 3 #define MAXSECTIONS 400 /* ADSL Message offsets from Host Interface Pointer */ /* ADSL2 Messages Index and Length defines */ /* * !!Important: * These definition must match the same definition of * ctrl_msm_decl.h in datapump. */ #if 1 //cph, sync for RP5 changes #define CRATES1_INDEX 0 #define CMSGS1_INDEX 1 #define RRATES1_INDEX 2 #define RMSGS1_INDEX 3 #define RMSGS2_INDEX 4 #define RRATES2_INDEX 5 #define CMSGS2_INDEX 6 #define CRATES2_INDEX 7 #define CBNG_INDEX 8 #define RBNG_INDEX 9 #define RMSGSRA_INDEX 10 #define RRATESRA_INDEX 11 #define CMSGSRA_INDEX 12 #define CRATESRA_INDEX 0 #define CMSGFMT_INDEX 0 // Same as CRATES1 #define CMSGPCB_INDEX 1 // Same as CMSGS1 #define RMSGFMT_INDEX 2 // Same as RRATES1 #define RMSGPCB_INDEX 3 // Same as RMSGS1 #define RMSG1LD_INDEX 13 #define RMSG2LD_INDEX 14 #define RMSG3LD_INDEX 15 #define RMSG4LD_INDEX 16 #define RMSG5LD_INDEX 17 #define RMSG6LD_INDEX 18 #define RMSG7LD_INDEX 19 #define RMSG8LD_INDEX 20 #define RMSG9LD_INDEX 21 #define RMSG10LD_INDEX 22 #define RMSG11LD_INDEX 23 #define RMSG12LD_INDEX 24 #define RMSG13LD_INDEX 25 #define RMSG14LD_INDEX 26 #define RMSG15LD_INDEX 27 #define RMSG16LD_INDEX 28 #define RMSG17LD_INDEX 29 #define CMSG1LD_INDEX 30 #define CMSG2LD_INDEX 31 #define CMSG3LD_INDEX 32 #define CMSG4LD_INDEX 33 #define CMSG5LD_INDEX 34 #define RMSGACK_INDEX 35 #define CMSGPCB2_INDEX 36 // Same as CMSGS1 #define CMSGPCB2L_INDEX 37 // Same as CMSGS1 #define RMSGFMT2_INDEX 38 // Same as RMSGS1 #define RMSGPCB2L_INDEX 39 // Same as RRATES1 #define CMSG1ADSL2_INDEX 40 #define RMSG1ADSL2_INDEX 41 #define CMSG2ADSL2_INDEX 42 #define RMSG2ADSL2_INDEX 43 #define CPARAMS_INDEX 44 #define RPARAMS_INDEX 45 #define CMSG1ADSL2P_INDEX 46 #define RMSG2ADSL2P_INDEX 47 #define CPARAMSPL_INDEX 48 #define RPARAMSPL_INDEX 49 #define RMSGPCB2PL_INDEX 50 // Same as CRATES1 #else #define CMSGFMT_INDEX 0 #define CMSGPCB_INDEX 1 #define RMSGFMT_INDEX 2 #define RMSGPCB_INDEX 3 #define RMSG1LD_INDEX 13 #define RMSG2LD_INDEX 14 #define RMSG3LD_INDEX 15 #define RMSG4LD_INDEX 16 #define RMSG5LD_INDEX 17 #define RMSG6LD_INDEX 18 #define RMSG7LD_INDEX 19 #define RMSG8LD_INDEX 20 #define RMSG9LD_INDEX 21 #define CMSG1LD_INDEX 22 #define CMSG2LD_INDEX 23 #define CMSG3LD_INDEX 24 #define CMSG4LD_INDEX 25 #define CMSG5LD_INDEX 26 #define CMSGPCB2_INDEX 28 #define CMSGPCB2L_INDEX 29 #define RMSGFMT2_INDEX 30 #define RMSGPCB2L_INDEX 31 #define CMSG1ADSL2_INDEX 32 #define RMSG1ADSL2_INDEX 33 #define CMSG2ADSL2_INDEX 34 #define RMSG2ADSL2_INDEX 35 #define CPARAMS_INDEX 36 #define RPARAMS_INDEX 37 #define CMSG1ADSL2P_INDEX 38 #define RMSG2ADSL2P_INDEX 39 #define CPARAMSPL_INDEX 40 #define RPARAMSPL_INDEX 41 #define RMSGPCB2PL_INDEX 42 #define RMSG10LD_INDEX 43 #define RMSG11LD_INDEX 44 #define RMSG12LD_INDEX 45 #define RMSG13LD_INDEX 46 #define RMSG14LD_INDEX 47 #define RMSG15LD_INDEX 48 #define RMSG16LD_INDEX 49 #define RMSG17LD_INDEX 50 #endif /* ADSL2 Message Sizes */ #define CMSGFMT_SIZE 2 #define RMSGFMT_SIZE 2 #define CMSGPCB_SIZE 2 #define CMSGPCB2_SIZE 6 /* Annex A with Blackout */ #define CMSGPCB2L_SIZE 10 /* Annex B with Blackout */ #define RMSGPCB_SIZE 38 #define RMSGPCB2L_SIZE 36 #define RMSG1LD_SIZE 16 #define RMSGxLD_SIZE 258 #define CMSG1LD_SIZE 16 #define CMSG2LD_SIZE 130 #define CMSG3LD_SIZE 66 #define CMSG4LD_SIZE 34 #define CMSG5LD_SIZE 34 #define CMSG1ADSL2_SIZE 24 #define RMSG1ADSL2_SIZE 4 #define CMSG2ADSL2_SIZE 4 #define RMSG2ADSL2_SIZE 32 #define CPARAMS_SIZE 136 #define RPARAMS_SIZE 808 /* ADSL2 Plus Message Sizes (if Different from ADSL2) */ #define RMSGPCB2PL_SIZE 68 /* Missing an Index */ #define CMSG1ADSL2P_SIZE 40 /* With Blackout */ #define RMSG2ADSL2P_SIZE 64 #define CPARAMSPL_SIZE 168 #define RPARAMSPL_SIZE 2088 /* #define CPARAMS_PB_SIZE 296 #define RPARAMS_PB_SIZE 2088 */ unsigned dslhal_support_getHlog(tidsl_t *ptidsl, unsigned index); unsigned dslhal_support_aocBitSwapProcessing(tidsl_t *ptidsl,unsigned int usDs); unsigned dslhal_support_gatherEocMessages(tidsl_t *ptidsl, unsigned usDs, unsigned msgPart1, unsigned msgPart2); unsigned dslhal_support_gatherSnrPerBin(tidsl_t *ptidsl,unsigned int snrParm); unsigned dslhal_support_gatherAdsl2Messages(tidsl_t *ptidsl, unsigned msgTag); unsigned dslhal_support_gatherRateMessages(tidsl_t *ptidsl); unsigned dslhal_support_updateTrainMode(tidsl_t *ptidsl); unsigned dslhal_support_IsADSL1Mode(tidsl_t *ptidsl); void dslhal_support_resetTrainFailureLog(tidsl_t *ptidsl); void dslhal_support_addTrainFailureLog(tidsl_t *ptidsl, unsigned failState); /*** Interface Access ***/ #define IFACE_OFFSET(M) OFFSET32(DEV_HOST_dspOamSharedInterface_t, M) #define IFACE_INT_OFFSET(M) OFFSET32(DEV_HOST_dspOamInternalSharedInterface_t, M) #define IFACE_DSPVER_OFFSET(M) OFFSET32(DEV_HOST_dspVersionDef_t, M) #define IFACE_MDMSTT_OFFSET(M) OFFSET32(DEV_HOST_modemStateBitField_t, M) #define IFACE_DSPWRI_OFFSET(M) OFFSET32(DEV_HOST_dspWrNegoParaDef_t, M) #define IFACE_OAMWRI_OFFSET(M) OFFSET32(DEV_HOST_oamWrNegoParaDef_t, M) #define IFACE_RAMSGS_OFFSET(M) OFFSET32(DEV_HOST_raMsgsDef_t, M) #define IFACE_HSTMSG_OFFSET(M) OFFSET32(DEV_HOST_msg_t, M) #define IFACE_EOCVAR_OFFSET(M) OFFSET32(DEV_HOST_eocVarDef_t, M) #define IFACE_INTMSK_OFFSET(M) OFFSET32(DEV_HOST_hostInterruptMask_t, M) #define IFACE_INTSRC_OFFSET(M) OFFSET32(DEV_HOST_hostInterruptSource_t, M) #define IFACE_MDMENV_OFFSET(M) OFFSET32(DEV_HOST_modemEnvPublic_t, M) #define IFACE_OLRRX__OFFSET(M) OFFSET32(DEV_HOST_olrDspRxDef_t, M) #define IFACE_OLRTX__OFFSET(M) OFFSET32(DEV_HOST_olrDspTxDef_t, M) #define IFACE_PHYCTL_OFFSET(M) OFFSET32(DEV_HOST_phyControlStructure_t, M) #define IFACE_PHYCNF_OFFSET(M) OFFSET32(DEV_HOST_phyFeatureConfiguration_t, M) #define IFACE_INT_MDMENV_OFFSET(M) OFFSET32(DEV_HOST_modemEnv_t, M) int dslhal_support_blockRead (void *addr, void *buffer, unsigned count); int dslhal_support_blockWrite (void *buffer, void *addr, unsigned count); unsigned dslhal_support_interfaceRW( unsigned baseAddr, unsigned *offset, unsigned rw, void *outBuf, unsigned numBytes ); unsigned dslhal_support_InterfaceGet(tidsl_t *ptidsl, void *hostPtr); unsigned dslhal_support_getDspVersion(tidsl_t *ptidsl, void *buf); unsigned dslhal_support_getNetService(tidsl_t *ptidsl); unsigned dslhal_support_getDspVerStruct(tidsl_t *ptidsl, void *buf); unsigned dslhal_support_getModemState(tidsl_t *ptidsl, void *buf); unsigned dslhal_support_getTrellis(tidsl_t *ptidsl); unsigned dslhal_support_dbgHalt(tidsl_t *ptidsl, unsigned rw, unsigned *d); unsigned dslhal_support_getStateLog(tidsl_t *ptidsl); unsigned dslhal_support_autoRetrain(tidsl_t *ptidsl, unsigned rw, unsigned *d); unsigned dslhal_support_getATUCVendorId(tidsl_t *ptidsl, void *d); unsigned dslhal_support_getGhsMsg(tidsl_t *ptidsl, void *d, unsigned size); unsigned dslhal_support_getTrainMode(tidsl_t *ptidsl, unsigned *d); unsigned dslhal_support_getSubState(tidsl_t *ptidsl, unsigned *d); unsigned dslhal_support_intrSrc(tidsl_t *ptidsl, unsigned rw, unsigned *d); unsigned dslhal_support_getRMsgsRa(tidsl_t *ptidsl); unsigned dslhal_support_getCMsgsRa(tidsl_t *ptidsl); unsigned int dslhal_support_setInterruptMask (tidsl_t * ptidsl, unsigned int inputMask); unsigned dslhal_support_getAdsl2MessageLocation(tidsl_t *ptidsl, unsigned msgOffset); unsigned dslhal_support_getModemStatistics(tidsl_t *ptidsl); unsigned dslhal_support_getDspSharedTbls(tidsl_t *ptidsl); /***TBD***/ int dslhal_support_setDsp250MHzTrigger(tidsl_t *ptidsl); /*** Code Download ***/ /*** TBD ***/ #define CRC32_QUOTIENT 0x04c11db7 int dslhal_support_hostDspCodeDownload (tidsl_t * ptidsl); unsigned int dslhal_support_checkOverlayPage (tidsl_t *ptidsl, unsigned tag); int dslhal_support_restoreTrainingInfo(tidsl_t * ptidsl); int dslhal_support_clearTrainingInfo(tidsl_t * ptidsl); void dslhal_support_freeOverlayPage(tidsl_t *ptidsl); #endif /* DSL_HAL_SUPPORT_H__ */