/*******************************************************************************
**+--------------------------------------------------------------------------+**
**|                            ****                                          |**
**|                            ****                                          |**
**|                            ******o***                                    |**
**|                      ********_///_****                                   |**
**|                      ***** /_//_/ ****                                   |**
**|                       ** ** (__/ ****                                    |**
**|                           *********                                      |**
**|                            ****                                          |**
**|                            ***                                           |**
**|                                                                          |**
**|         Copyright (c) 1998-2005 Texas Instruments Incorporated           |**
**|                        ALL RIGHTS RESERVED                               |**
**|                                                                          |**
**+--------------------------------------------------------------------------+**
*******************************************************************************/

/** \file   cslr_sar.h
    \brief  SAR CSL Header - Register Layer Abstraction

    Register layer abstraction of SAR peripheral device.

    9/15/2006 AV & GSG     Merging in the changes due to the new SAR firmware, 
                           and PDSP memory map.
    2/7/2007  MK           CQ11291: Added OAM ping support.
    @author     Greg Guyotte
 */

#ifndef __CSLR_SAR_H__
#define __CSLR_SAR_H__

#include "csl_defs.h"

#ifdef YAMUNA
/* UPDATED FIRMWARE MAPPING */
typedef struct
{
  CSL_Reg32   AAL5_Tx_State[8];
  CSL_Reg32   AAL5_Rx_State[8];
  CSL_Reg32   AAL5_Tx_VP_State[4];
  CSL_Reg32   AAL5_Rx_VP_State[4];
  CSL_Reg32   PDSP_General_Use[8];
}CSL_PDSP_Ch_State_RAM;
#else
/* OLD FIRMWARE MAPPING */
typedef struct
{
  CSL_Reg32   Reserved[20];
  CSL_Reg32   AAL5_Tx_State[8];
  CSL_Reg32   AAL5_Rx_State[8];
  CSL_Reg32   AAL5_Tx_VP_State[4];
  CSL_Reg32   AAL5_Rx_VP_State[4];
  CSL_Reg32   PDSP_General_Use[20];
}CSL_PDSP_State_RAM;
#endif


#ifdef YAMUNA
typedef struct
{
  CSL_Reg32   OAM_Config[8];
  CSL_Reg32   Reserved1[24];
  CSL_Reg32   OAM_Padding[16];
  CSL_Reg32   Reserved2[16];
  CSL_Reg32   Ping_Resp_0[16];
  CSL_Reg32   Ping_Resp_1[16];
}CSL_PDSP_Oam_State_RAM;
#else
typedef struct
{
  CSL_Reg32   OAM_Config[8];
  CSL_Reg32   OAM_Padding[20];
}CSL_PDSP_Oam_State_RAM;
#endif

/**
 * \brief SAR Peripheral Device Register Memory Layout structure
 *
 * The structure instance variable points to SAR register space in
 * SOC memory map directly.
 * This is a template only, no memory is ever allocated for this!
 *
 * Please note that several of the registers defined below are not
 * intended for normal host/driver access.  The intentions are noted in
 * comments below - but all registers are defined here for
 * access by test or diagnostic code.
 */
typedef struct  
{
  /* Global Registers - host accesses these */
  CSL_Reg32   IdVer;
  CSL_Reg32   Reserved1;
  CSL_Reg32   Status_Set;
  CSL_Reg32   Status_Clear;
  CSL_Reg32   Host_Int_Enable_Set;
  CSL_Reg32   Host_Int_Enable_Clear;
  CSL_Reg32   PDSP_Int_Enable_Set;
  CSL_Reg32   PDSP_Int_Enable_Clear;
  CSL_Reg32   Host_Mailbox[8];
  CSL_Reg32   EOI;
  CSL_Reg32   Int_Vector;
  CSL_Reg32   Reserved2[14];

  /* SAR RLUT Registers - see below for registers intended for Host access*/
  CSL_Reg32   Rx_LUT_Global_Config;             /* Host access */
  CSL_Reg32   Reserved3[3];
  CSL_Reg32   Rx_LUT_Ch_Setup_Req;              /* Host access */
  CSL_Reg32   Rx_LUT_Ch_Setup_Req_VPI_VCI;      /* Host access */
  CSL_Reg32   Reserved4;
  CSL_Reg32   Rx_LUT_Ch_Teardown_Req;
  CSL_Reg32   Rx_LUT_Ch_Setup;
  CSL_Reg32   Rx_LUT_Ch_Setup_VPI_VCI;
  CSL_Reg32   Reserved5;
  CSL_Reg32   Rx_LUT_Ch_Teardown;
  CSL_Reg32   Rx_LUT_Lookup_Ctrl;
  CSL_Reg32   Rx_LUT_Lookup_Result[3];
  CSL_Reg32   Rx_LUT_Unknown_Protocol;          /* Host access */
  CSL_Reg32   Rx_LUT_Unknown_Protocol_Counter;  /* Host access */
  CSL_Reg32   Rx_LUT_Stats_Mailbox;             /* Host access */
  CSL_Reg32   Reserved6[13];

  /* SAR Tx Scheduler Registers - used only by SPDSP, not host */
  CSL_Reg32   TXS_Command;
  CSL_Reg32   TXS_Absolute_Delta;
  CSL_Reg32   TXS_Status;
  CSL_Reg32   TXS_Output;
  CSL_Reg32   TXS_Output_Update[8];
  CSL_Reg32   Reserved7[4];
  CSL_Reg32   TXS_Timer_Update;
  CSL_Reg32   TXS_Timer_LSB;
  CSL_Reg32   TXS_Timer_MSB;
  CSL_Reg32   Reserved8[9];
  CSL_Reg32   TXS_Channel_Config;
  CSL_Reg32   Reserved9[3];
  CSL_Reg32   Reserved10[32];

  /* SAR Tx PPU 0 Read Interface - not for host use */
  CSL_Reg32   Reserved11;
  CSL_Reg32   Tx_PPU0_Read_CRC32_Preset;
  CSL_Reg32   Tx_PPU0_Read_CRC32;
  CSL_Reg32   Reserved12[2];
  CSL_Reg32   Tx_PPU0_Read_CRC16_Preset;
  CSL_Reg32   Tx_PPU0_Read_CRC16;
  CSL_Reg32   Reserved13[7];
  CSL_Reg32   Tx_PPU0_Read_Cell_Info;
  CSL_Reg32   Tx_PPU0_Read_FIFO_Advance;
  CSL_Reg32   Tx_PPU0_Read_FIFO_Word[16];
  CSL_Reg32   Reserved14[96];

  /* SAR Tx PPU 1 Read Interface - not for host use */
  CSL_Reg32   Reserved15;
  CSL_Reg32   Tx_PPU1_Read_CRC32_Preset;
  CSL_Reg32   Tx_PPU1_Read_CRC32;
  CSL_Reg32   Reserved16[2];
  CSL_Reg32   Tx_PPU1_Read_CRC16_Preset;
  CSL_Reg32   Tx_PPU1_Read_CRC16;
  CSL_Reg32   Reserved17[7];
  CSL_Reg32   Tx_PPU1_Read_Cell_Info;
  CSL_Reg32   Tx_PPU1_Read_FIFO_Advance;
  CSL_Reg32   Tx_PPU1_Read_FIFO_Word[16];
  CSL_Reg32   Reserved18[32];

  /* SAR Rx PPU Write Interface - not for host use */
  CSL_Reg32   Reserved19;
  CSL_Reg32   Rx_PPU_Write_CRC32_Preset;
  CSL_Reg32   Rx_PPU_Write_CRC32;
  CSL_Reg32   Rx_PPU_Write_CRC10_Preset;
  CSL_Reg32   Rx_PPU_Write_CRC10;
  CSL_Reg32   Rx_PPU_Write_CRC16_Preset;
  CSL_Reg32   Rx_PPU_Write_CRC16;
  CSL_Reg32   Reserved20[7];
  CSL_Reg32   Rx_PPU_Write_Cell_Info;
  CSL_Reg32   Rx_PPU_Write_FIFO_Advance;
  CSL_Reg32   Rx_PPU_Write_FIFO_Word[16];
  CSL_Reg32   Reserved21[12];
  CSL_Reg32   Reserved22[146];

  /* Cell Interface Bridge - not for host use */
  CSL_Reg32   Tx_Ch_0_Config;
  CSL_Reg32   Tx_Ch_0_Base_Addr;
  CSL_Reg32   Tx_Ch_0_Buffer_Size;
  CSL_Reg32   Tx_Ch_0_Offset;
  CSL_Reg32   Tx_Ch_0_Increment;
  CSL_Reg32   Tx_Ch_0_Cell_Count;
  CSL_Reg32   Reserved23[2];
  CSL_Reg32   Tx_Ch_1_Config;
  CSL_Reg32   Tx_Ch_1_Base_Addr;
  CSL_Reg32   Tx_Ch_1_Buffer_Size;
  CSL_Reg32   Tx_Ch_1_Offset;
  CSL_Reg32   Tx_Ch_1_Increment;
  CSL_Reg32   Tx_Ch_1_Cell_Count;
  CSL_Reg32   Reserved24[2];
  CSL_Reg32   Rx_Ch_0_Config;
  CSL_Reg32   Rx_Ch_0_Base_Addr;
  CSL_Reg32   Rx_Ch_0_Buffer_Size;
  CSL_Reg32   Rx_Ch_0_Offset;
  CSL_Reg32   Rx_Ch_0_Increment;
  CSL_Reg32   Rx_Ch_0_Cell_Count;
  CSL_Reg32   Reserved25[2];
  CSL_Reg32   Rx_Ch_1_Config;
  CSL_Reg32   Rx_Ch_1_Base_Addr;
  CSL_Reg32   Rx_Ch_1_Buffer_Size;
  CSL_Reg32   Rx_Ch_1_Offset;
  CSL_Reg32   Rx_Ch_1_Increment;
  CSL_Reg32   Rx_Ch_1_Cell_Count;
  CSL_Reg32   Reserved26[36];

  /* skip past gap up to SAR Scratchpad RAM */
  CSL_Reg32   Reserved27[3520];

  /* PDSP State RAM */
#ifdef YAMUNA
  CSL_Reg32   Reserved28[1024];
#else
  CSL_PDSP_State_RAM PDSP_RAM[16];
#endif

  /* Big gap, skips past CPPI 4.0 DMA regs */
  
  CSL_Reg32   Reserved29[8384];

  /* SPDSP Control/Status Registers */
  CSL_Reg32   Control;                       /* Host access */
  CSL_Reg32   Status;                        /* Host access */
  CSL_Reg32   Constant_Table_Block_Index[2];
  CSL_Reg32   Constant_Table_Prg_Ptr[2];

  /* Big gap */
  CSL_Reg32   Reserved30[142138];
 
  /* PDSP Instruction RAM - firmware goes here */
  CSL_Reg32   PDSP_IRAM[2048];

  /*CSL_Reg32   Reserved30[614400];*/
} CSL_SarRegs;

/* GSG : the only reason I broke the registers into two parts
is because I was getting a compiler exception that I couldn't 
explain when I was using one large memory map.  I believe the
compiler simply couldn't support the address offsets that 
resulted from having a structure that large. */

#ifdef YAMUNA
typedef struct  
{
  /* Direct RAM Access Region - documented in SSRAM spec */
  CSL_PDSP_Ch_State_RAM PDSP_CH_RAM[16];
  CSL_PDSP_Oam_State_RAM PDSP_OAM_RAM;
  CSL_Reg32   PDSP_RESERVED_RAM[160]; //was 228
  /*CSL_Reg32   Scratchpad[768];*/
  CSL_Reg32   Tx_PPU_0_FIFO[32];
  CSL_Reg32   Tx_PPU_1_FIFO[32];
  CSL_Reg32   Rx_PPU_FIFO[32];
  CSL_Reg32   Rx_LUT[32];
  CSL_Reg32   AtmHeader[16];
  CSL_Reg32   CpcsUU[16];
} CSL_ScratchpadRegs;
#else
typedef struct  
{
  /* Direct RAM Access Region - documented in SSRAM spec */
  CSL_Reg32   Scratchpad[768];
  CSL_Reg32   Tx_PPU_0_FIFO[32];
  CSL_Reg32   Tx_PPU_1_FIFO[32];
  CSL_Reg32   Rx_PPU_FIFO[32];
  CSL_Reg32   Rx_LUT[32];
  CSL_Reg32   AtmHeader[16];
  CSL_Reg32   CpcsUU[16];
} CSL_ScratchpadRegs;
#endif

/*
 * \brief SAR register overlay pointer
 *
 * Can be used in DDC layer directly for performance considerations.
 */
typedef volatile CSL_SarRegs *CSL_SarRegsOvly;
typedef volatile CSL_ScratchpadRegs *CSL_ScratchpadRegsOvly;

/* Statistics clear value */
#define SAR_NUM_STAT_REGS                     36
#define SAR_STAT_CLEAR                        0xFFFFFFFF

/* SAR Teardown Value */
#define SAR_TEARDOWN_VALUE                    0xFFFFFFFC

/* TX / RX Control bits */
#define SAR_TX_CONTROL_TX_ENABLE_VAL          0x1
#define SAR_RX_CONTROL_RX_ENABLE_VAL          0x1

/* Host interrupt bits */
#define SAR_SAR_HOST_ERR_INTMASK_VAL          0x2
#define SAR_SAR_STAT_INT_INTMASK_VAL          0x1

/* SAR RX Max packet length mask */
#define CSL_SAR_RX_BUFFER_OFFSET_SHIFT        0
#define CSL_SAR_RX_BUFFER_OFFSET_MASK         0xFFFF

/* INT_VECTOR register bit fields */
#define SAR_INT_VECTOR_STATUS_INT          (1 << 19)
#define SAR_INT_VECTOR_HOST_INT            (1 << 18)
#define SAR_INT_VECTOR_RX_INT_OR           (1 << 17)
#define SAR_INT_VECTOR_TX_INT_OR           (1 << 16)
#define SAR_INT_VECTOR_RX_INT_VEC          (7 << 8)
#define SAR_INT_VECTOR_TX_INT_VEC          (7)

/* CPPI bit positions */
#define SAR_CPPI_SOP_BIT                      0x80000000  /*(1 << 31)*/
#define SAR_CPPI_EOP_BIT                      0x40000000  /*(1 << 30*/
#define SAR_CPPI_OWNERSHIP_BIT                0x20000000  /*(1 << 29)*/
#define SAR_CPPI_EOQ_BIT                      0x10000000  /*(1 << 28)*/
#define SAR_CPPI_TEARDOWN_COMPLETE_BIT        0x8000000   /*(1 << 27)*/
#define SAR_CPPI_PASS_CRC_BIT                 0x4000000   /*(1 << 26)*/

/* software reset bits */
#define SAR_SOFT_RESET_BIT                    0x00000001
#define SAR_SOFT_RESET_COMPLETE               0x00000000

/* PDSP Defines */
#define NUM_PDSP_AAL5_STATE_WORDS           24
#define NUM_PDSP_AAL5_TX_STATE_WORDS        8
#define NUM_PDSP_AAL5_TX_VP_STATE_WORDS     4
#define NUM_PDSP_AAL5_RX_STATE_WORDS        8
#define NUM_PDSP_AAL5_RX_VP_STATE_WORDS     4
#ifdef YAMUNA
#define PDSP_STATE_RAM_SIZE                 768
#else
#define PDSP_STATE_RAM_SIZE                 1024
#endif
#define IRAM_SIZE                           1536
#define NUM_OAM_RATES                       11

#define ATMHEADER_VCI_MASK                  0x000ffff0
#define ATMHEADER_VPI_VCI_MASK              0x0ffffff0

//AV_SM
/* Interrupt line number */
#define CPPI4_MIN_TX_INT_LINE 15
#define CPPI4_MAX_TX_INT_LINE 18
#define CPPI4_MIN_RX_INT_LINE 32
#define CPPI4_MAX_RX_INT_LINE 39

/* CPPI4 Buffer Descriptor Macros */
#define CPPI4_BD_BUF_SIZE_MASK          0xFFFF;
#define CPPI4_BD_PKT_LENGTH_MASK        0xFFFF
/* Only CPPI specified bytes need to be invalidated */
#define CPPI4_BD_LENGTH_FOR_CACHE       32
/* This MUST be an integer multiple of 32, nothing else will work */
#define CPPI4_BD_ALIGN                  64

#define IS_TX_INTR(i) ((i >= CPPI4_MIN_TX_INT_LINE) && (i <= CPPI4_MAX_TX_INT_LINE))
#define IS_RX_INTR(i) ((i >= CPPI4_MIN_RX_INT_LINE) && (i <= CPPI4_MAX_RX_INT_LINE))

#define CPSAR_VIRT_2_PHYS(addr)     (((Uint)(addr)) &~ 0xE0000000)
#define CPSAR_PHYS_2_VIRT(addr)     ((Ptr)(((Uint)(addr)) | 0x80000000))
#define CPSAR_VIRT_NOCACHE(addr)    ((Ptr)((PAL_CPPI4_VIRT_2_PHYS(addr)) | 0xA0000000))
#define CPSAR_CACHE_INVALIDATE      DDC_atm_data_invalidate
#define CPSAR_CACHE_WRITEBACK       DDC_atm_data_writeback

#endif /* __CSLR_SAR_H__ */