/*
 *  * Nitin Dhingra, iamnd@ti.com
 *   * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.
 *    *
 *     * ########################################################################
 *      *
 *       *  This program is free software; you can distribute it and/or modify it
 *        *  under the terms of the GNU General Public License (Version 2) as
 *         *  published by the Free Software Foundation.
 *          *
 *           *  This program is distributed in the hope it will be useful, but WITHOUT
 *            *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *             *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *              *  for more details.
 *               *
 *                *  You should have received a copy of the GNU General Public License along
 *                 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *                  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *                   *
 *                    * ########################################################################
 *                     *
 *                      * Routines for generic manipulation of the interrupts found on the Texas
 *                       * Instruments avalanche board
 *                        *
 *                         */

#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/proc_fs.h>
#include <asm/irq.h>
#include <asm/atomic.h>
#include <asm/mips-boards/prom.h>
#include "pal.h"
#include "avalanche_intc.h"
#include <asm/gdb-stub.h>

#if defined (CONFIG_AVALANCHE_INTC_PACING) 
extern unsigned int avalanche_get_intc_input_freq(void);
#endif


/*******************************************************************************
 * * Avalanche primary interrupts
 * *******************************************************************************/
extern irq_desc_t irq_desc [NR_IRQS];

/* Interrupt control regs (primary)     */
struct avalanche_ictrl_regs         *avalanche_hw0_icregs;  
/* Exception control regs (secondary)   */
struct avalanche_exctrl_regs        *avalanche_hw0_ecregs;  
/* Interrupt pacing registers           */
struct avalanche_ipace_regs         *avalanche_hw0_ipaceregs;
/* Channel control registers            */
struct avalanche_channel_int_number *avalanche_hw0_chregs;  

extern asmlinkage void mipsIRQ(void);

#define INTERRUPT_PANIC(irq) \
            printk("whee, invalid irq_nr %d at %s line %d\n", \
                                                                (irq), __FILE__, __LINE__);\
        panic("IRQ, you lose...");



/*
 *  *   The avalanche/MIPS interrupt line numbers are used to represent the
 *   *   interrupts within the irqaction arrays.  The index notation is
 *    *   is as follows:
 *     *
 *      *           0-7    MIPS CPU Exceptions  (HW/SW)
 *       *           8-47   Primary Interrupts   (Avalanche)
 *        *          48-79   Secondary Interrupts (Avalanche)
 *         *          80-111  Low Vlynq Interrupts (Vlynq)
 *          *         112-143  High Vlynq Interrupts(Vlynq)
 *           *
 *            */

/*
 *  * This remaps interrupts to exist on other channels than the default
 *   * channels.  essentially we can use the line# as the index for this
 *    * array
 *     */
static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];

/* ******************** AVALANCHE INTC S/W IRQ SUPPORT **************************** */


static struct avalanche_intc_vect_t av_irq_desc[AVALANCHE_INT_END];






#ifdef CONFIG_AVALANCHE_INTC_PACING

#define AVALANCHE_MAX_PACING_BLK   3
#define AVALANCHE_PACING_LOW_VAL   2
#define AVALANCHE_PACING_HIGH_VAL 63

int avalanche_request_intr_pacing(int irq_nr, unsigned int blk_num,
                             unsigned int pace_value)
{
        unsigned int  blk_offset;
            unsigned long flags;

                if(irq_nr <  MIPS_EXCEPTION_OFFSET ||
                               irq_nr >= AVALANCHE_INT_END_PRIMARY)
                            return (-1);

                    if(blk_num > AVALANCHE_MAX_PACING_BLK)
                                return(-1);

                        if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
                                       pace_value < AVALANCHE_PACING_LOW_VAL)
                                return(-1);

                            blk_offset = blk_num*8;

                                save_and_cli(flags);

                                    /* disable the interrupt pacing, if enabled previously */
                                    avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);

                                        /* clear the pacing map */
                                        avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);

                                            /* setup the new values */
                                            avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr))   << blk_offset);
                                                avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value)  << blk_offset);

                                                    restore_flags(flags);

                                                        return(0);
}

int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_val)
{
            return(avalanche_request_intr_pacing(irq_nr,blk_num,pace_val));
}

#endif

#if defined(CONFIG_AVALANCHE_INTC_PACING)
/* EXPORT_SYMBOL(avalanche_request_intr_pacing); */ 
/* EXPORT_SYMBOL(avalanche_request_pacing); */ 
#endif