#ifndef _ASM_ARCH_H_DAVINCI_
#define _ASM_ARCH_H_DAVINCI_

#define CE0_BASE            0x02000000
#define CS0_SIZE            (32*1024*1024)
#define CE1_BASE            0x04000000
#define CS1_SIZE            CS0_SIZE
#define CE2_BASE            0x06000000
#define CS2_SIZE            CS0_SIZE
#define CE3_BASE            0x08000000
#define CS3_SIZE            CS0_SIZE

#define RAM_BASE            0x80000000

#define UART0_BASE          0x01C20000
#define UART1_BASE          0x01C20400
#define UART2_BASE          0x01C20800
#define I2C_BASE            0x01C21000

#define TIMER0_BASE         0x01C21400
#define TIMER1_BASE         0x01C21800
#define TIMER2_BASE         0x01C21C00
#define TIMER_PID_OFF       0x00
#define TIMER_EMUMGT_OFF    0x04
#define TIMER_TIM12         0x10
#define TIMER_TIM34         0x14
#define TIMER_PRD12         0x18
#define TIMER_PRD34         0x1C
#define TIMER_TCR           0x20
#define TIMER_TGCR          0x24
#define TIMER_WDTCR         0x28

#define PWM0_BASE           0x01C22000
#define PWM1_BASE           0x01C22400
#define PWM2_BASE           0x01C22800

#define SYSTEM_BASE         0x01C40000
#define PINMUX0_OFFSET      0x00
#define PINMUX1_OFFSET      0x04
#define BOOTCFG_OFFSET      0x14
#define DEVICE_ID_OFFSET    0x28
#define DRRVTPER_OFFSET     0x4C

#define PLL1_BASE           0x01C40800
#define PLL2_BASE           0x01C40C00
#define PLLCTL_OFFSET       0x100
#define PLLM_OFFSET         0x110
#define PLLDIV1_OFFSET      0x118
#define PLLDIV2_OFFSET      0x11C
#define PLLDIV3_OFFSET      0x120
#define POSTDIV_OFFSET      0x128
#define BPDIV_OFFSET        0x12C
#define PLLCMD_OFFSET       0x138
#define PLLSTAT_OFFSET      0x13C
#define PLLDIV4_OFFSET      0x160
#define PLLDIV5_OFFSET      0x164

#define PSC_BASE            0x01C41000
#define PID_OFF             0x00
#define GBLCTL_OFF          0x10
#define INTEVAL_OFF         0x18
#define MERRPR0_OFF         0x40
#define MERRPR1_OFF         0x44
#define MERRCR0_OFF         0x50
#define MERRCR1_OFF         0x54
#define PERRPR_OFF          0x60
#define PERRCR_OFF          0x68
#define EPCPR_OFF           0x70
#define EPCCR_OFF           0x78
#define PTCMD_OFF           0x120
#define PTSTAT_OFF          0x128
#define PDSTAT0_OFF         0x200
#define PDSTAT1_OFF         0x204
#define PDCTL0_OFF          0x300
#define PDCTL1_OFF          0x304
#define MCKOUT0             0x510
#define MCKOUT1             0x514
#define MDSTAT_BASE_OFF     0x800
#define MDCTL_BASE_OFF      0xA00

#define DFT_BASE            0x01C42000          /*--- undokumentiert!!! ---*/
#define MMARG_BRF0_OFF      0x10
#define DDRVTPR_OFF         0x30

#define INTERRUPT_BASE      0x01C48000
#define EINT_EN0_OFF        0x18
#define EINT_EN1_OFF        0x1C

#define USB20_BASE          0x01C64000
#define ATACF_BASE          0x01C66000
#define SPI_BASE            0x01C66800
#define GPIO_BASE           0x01C67000
#define VPSS_BASE           0x01C70000

#define EMAC_BASE           0x01C80000
#define CTL_MODUL_OFF       0x01000
#define EWCTL_OFF           0x04
#define EWINTTCNT_OFF       0x08
#define RAM_OFF             0x2000

#define MDIO_BASE           0x01C84000

#define IMAGE_CO_BASE       0x01CC0000

#define EMIFA_BASE          0x01E00000
#define WAITCFG_OFFSET      0x04
#define ACFG2_OFFSET        0x10
#define ACFG3_OFFSET        0x14
#define ACFG4_OFFSET        0x18
#define ACFG5_OFFSET        0x1C

#define VLYNQ_BASE          0x01E01000
#define ASP_BASE            0x01E02000
#define MMCSD_BASE          0x01E10000

#define DDR2_BASE           0x20000000
#define SDSTAT_OFF          0x04
#define SDBCR_OFF           0x08
#define SDRCR_OFF           0x0C
#define SDTIMR_OFF          0x10
#define SDTIMR2_OFF         0x14
#define SDPBBPR_OFF         0x20
#define SDIRR_OFF           0xC0
#define SDIMR_OFF           0xC4
#define SDIMSR_OFF          0xC8
#define SDIMCR_OFF          0xCC
#define DDRPHYCR_OFF        0xE4
#define VTPIOCR_OFF         0xF0


#define CACHED                                  /*--- KSEG0 im mips ---*/
#define UNCACHED                                /*--- KSEG1 im mips ---*/
#define PHYS                    (unsigned int)  /*--- KUSEG im mips ---*/

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
#define MHZ(x)                      ((x) * 1000 * 1000)

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
#define BASE_CLOCK                  MHZ(27)

#define FIRMWARE_CPU_CLOCK          MHZ(216)
#define FIRMWARE_SYSTEM_CLOCK       BASE_CLOCK

#define UART_CLOCK                  BASE_CLOCK

#if defined(__ASSEMBLY__)

#else /*--- #if defined(__ASSEMBLY__) ---*/

#define PAGE_SHIFT                  12
#define PAGE_SIZE		            (1UL << PAGE_SHIFT)

#endif /*--- #else ---*/ /*--- #if defined(__ASSEMBLY__) ---*/
#endif /*--- #ifndef _ASM_ARCH_H_DAVINCI_ ---*/