/*------------------------------------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------------------------------------*/
#ifndef _hw_clock_h_
#define _hw_clock_h_

#define PLL1CTL_REG         (*(volatile unsigned int *)(PLL1_BASE + PLLCTL_OFFSET))
#define PLL1M_REG           (*(volatile unsigned int *)(PLL1_BASE + PLLM_OFFSET))
#define PLL1DIV1_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLDIV1_OFFSET))
#define PLL1DIV2_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLDIV2_OFFSET))
#define PLL1DIV3_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLDIV3_OFFSET))
#define PLL1DIV4_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLDIV4_OFFSET))
#define PLL1DIV5_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLDIV5_OFFSET))
#define PLL1POSTDIV_REG     (*(volatile unsigned int *)(PLL1_BASE + POSTDIV_OFFSET))
#define PLL1BPDIV_REG       (*(volatile unsigned int *)(PLL1_BASE + BPDIV_OFFSET))
#define PLL1CMD_REG         (*(volatile unsigned int *)(PLL1_BASE + PLLCMD_OFFSET))
#define PLL1STAT_REG        (*(volatile unsigned int *)(PLL1_BASE + PLLSTAT_OFFSET))

#define PLL2CTL_REG         (*(volatile unsigned int *)(PLL2_BASE + PLLCTL_OFFSET))
#define PLL2M_REG           (*(volatile unsigned int *)(PLL2_BASE + PLLM_OFFSET))
#define PLL2DIV1_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLDIV1_OFFSET))
#define PLL2DIV2_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLDIV2_OFFSET))
#define PLL2DIV3_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLDIV3_OFFSET))
#define PLL2DIV4_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLDIV4_OFFSET))
#define PLL2DIV5_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLDIV5_OFFSET))
#define PLL2POSTDIV_REG     (*(volatile unsigned int *)(PLL2_BASE + POSTDIV_OFFSET))
#define PLL2BPDIV_REG       (*(volatile unsigned int *)(PLL2_BASE + BPDIV_OFFSET))
#define PLL2CMD_REG         (*(volatile unsigned int *)(PLL2_BASE + PLLCMD_OFFSET))
#define PLL2STAT_REG        (*(volatile unsigned int *)(PLL2_BASE + PLLSTAT_OFFSET))

/*--- PLLCTL ---*/
#define PLLEN       (1 << 0)
#define PLLPWRDN    (1 << 1)
#define PLLRST      (1 << 3)
#define PLLDIS      (1 << 4)
#define PLLENSRC    (1 << 5)
#define CLKMODE     (1 << 8)

union _pll_ctl_ {
    volatile unsigned int Reg;
    volatile struct __pll_ctl__ {
        unsigned int pllen       : 1;
        unsigned int pllpwrdn    : 1;
        unsigned int reserved2   : 1;
        unsigned int pllrst      : 1;
        unsigned int plldis      : 1;
        unsigned int pllensrc    : 1;
        unsigned int reserved67  : 2;
        unsigned int clkmode     : 1;
        unsigned int reserved931 : 22;
    } Bits;
} pll_ctl;

union _pll_div_ {
    volatile unsigned int Reg;
    volatile struct __pll_div__ {
        unsigned int ratio        : 5;
        unsigned int reserved514  : 9;
        unsigned int diven        : 1;
        unsigned int reserved1431 : 17;
    } Bits;
} pll_div;

union _pll_cmd_ {
    volatile unsigned int Reg;
    volatile struct __pll_cmd__ {
        unsigned int goset        : 1;
        unsigned int reserved     : 31;
    } Bits;
} pll_cmd;

union _pll_stat_ {
    volatile unsigned int Reg;
    volatile struct __pll_stat__ {
        unsigned int gostat       : 1;
        unsigned int reserved1    : 1;
        unsigned int stable       : 1;
        unsigned int reserved331  : 29;
    } Bits;
} pll_stat;

struct _hw_psc {
    unsigned int pid; /* 0x00 */
    unsigned int reserved0[(0x18 - 0x04) / sizeof(unsigned int)];
    volatile unsigned int inteval; /* 0x18 */
    unsigned int reserved1[(0x40 - 0x1C) / sizeof(unsigned int)];
    volatile unsigned int merrpr0; /* 0x40 */
    volatile unsigned int merrpr1; /* 0x44 */
    unsigned int reserved2[(0x50 - 0x48) / sizeof(unsigned int)];
    volatile unsigned int merrcr0; /* 50 */
    volatile unsigned int merrcr1; /* 54 */
    unsigned int reserved3[(0x60 - 0x58) / sizeof(unsigned int)];
    volatile unsigned int perrpr; /* 60 */
    unsigned int reserved4[(0x68 - 0x64) / sizeof(unsigned int)];
    volatile unsigned int perrcr; /* 68 */
    unsigned int reserved5[(0x70 - 0x6C) / sizeof(unsigned int)];
    volatile unsigned int epcpr; /* 70 */
    unsigned int reserved6[(0x78 - 0x74) / sizeof(unsigned int)];
    volatile unsigned int epccr; /* 78 */
    unsigned int reserved7[(0x120 - 0x7C) / sizeof(unsigned int)];
    volatile unsigned int ptcmd; /* 0x120 */
    unsigned int reserved8[(0x128 - 0x124) / sizeof(unsigned int)];
    volatile unsigned int ptstat; /* 0x128 */
    unsigned int reserved9[(0x200 - 0x12C) / sizeof(unsigned int)];
    volatile unsigned int pdstat[2]; /* 0x200 - 0x204 */
    unsigned int reserved10[(0x300 - 0x208) / sizeof(unsigned int)];
    volatile unsigned int pdctl[2]; /* 0x300 - 0x304 */
    unsigned int reserved11[(0x800 - 0x308) / sizeof(unsigned int)];
    volatile unsigned int mdstat[41]; /* 0x800 - 0x868 */
    unsigned int reserved12[(0xA00 - 0x86C) / sizeof(unsigned int)];
    volatile unsigned int mdctl[41]; /* 0xA00 - 0xA68 */
};


#endif /*--- #ifndef _hw_clock_h_ ---*/