/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
#ifndef _hw_uart_h_
#define _hw_uart_h_

/*--- fifo Control Register ---*/
#define FCR_FIFO_EN         (1<<0)		/* Fifo enable */
#define FCR_RXCLR           (1<<1)		/* Receiver soft reset */
#define FCR_TXCLR           (1<<2)		/* Transmitter soft reset */
#define DMA_MODE            (1<<3)

/*--- line Control Register ---*/
#define LCR_WLS_MSK	        0x03		/* character length slect mask */
#define LCR_WLS_5	        0		            /* 5 bit character length */
#define LCR_WLS_6	        (1<<0) 		        /* 6 bit character length */
#define LCR_WLS_7	        (1<<1)		        /* 7 bit character length */
#define LCR_WLS_8	        ((1<<0)+(1<<1))		/* 8 bit character length */
#define LCR_STB		        (1<<2)		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN		        (1<<3)		/* Parity eneble */
#define LCR_EPS		        (1<<4)		/* Even Parity Select */
#define LCR_STKP	        (1<<5)		/* Stick Parity */
#define LCR_SBRK	        (1<<6)		/* Set Break */
#define LCR_BKSE	        (1<<7)		/* Bank select enable */

/*--- modem Control Register ---*/
#define MCR_DTR             (1<<0)      /*--- no used ---*/ 
#define MCR_RTS             (1<<1)      /*--- rts/cts Control enable ---*/
#define MCR_LOOP            (1<<4)      /*--- loop-back-mode enable ---*/
#define MCR_AFE             (1<<5)      /*--- Autoflow enable ---*/

/*--- line Status Register ---*/
#define LSR_DR		        (1<<0)		/* Data ready */
#define LSR_OE		        (1<<1)		/* Overrun */
#define LSR_PE		        (1<<2)		/* Parity error */
#define LSR_FE		        (1<<3)		/* Framing error */
#define LSR_BI		        (1<<4)		/* Break */
#define LSR_THRE	        (1<<5)		/* Xmit holding register empty */
#define LSR_TEMT	        (1<<6)		/* Xmitter empty */
#define LSR_ERR		        (1<<7)		/* Error */

#define MODE_X_DIV 16

struct _sio_ {
    volatile unsigned int DAT;                  /*--- 0x00 ---*/
    volatile unsigned int IE;                   /*--- 0x04 ---*/
    volatile unsigned int IIR;                  /*--- 0x08 ---*/
    volatile unsigned int LC;                   /*--- 0x0C ---*/
    volatile unsigned int MC;                   /*--- 0x10 ---*/
    volatile unsigned int LS;                   /*--- 0x14 ---*/
    volatile unsigned int reserved;             /*--- 0x18 ---*/
    volatile unsigned int reserved1;            /*--- 0x1C ---*/
    volatile unsigned int DLL;                  /*--- 0x20 ---*/
    volatile unsigned int DLH;                  /*--- 0x24 ---*/
    volatile unsigned int PID1;                 /*--- 0x28 ---*/
    volatile unsigned int PID2;                 /*--- 0x2C ---*/
    volatile unsigned int PWREMU_MGMT;          /*--- 0x30 ---*/
};

#endif /*--- #define _hw_uart_h_ ---*/