/*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ #ifndef _HW_PSC_ #define _HW_PSC_ /* PSC Domains */ #define LPSC_VPSSMSTR 0 // VPSS Master LPSC #define LPSC_VPSSSLV 1 // VPSS Slave LPSC #define LPSC_TPCC 2 // TPCC LPSC #define LPSC_TPTC0 3 // TPTC0 LPSC #define LPSC_TPTC1 4 // TPTC1 LPSC #define LPSC_EMAC 5 // EMAC LPSC #define LPSC_EMAC_WRAPPER 6 // EMAC WRAPPER LPSC #define LPSC_MDIO 7 // MDIO LPSC #define LPSC_IEEE1394 8 // IEEE1394 LPSC #define LPSC_USB 9 // USB LPSC #define LPSC_ATA 10 // ATA LPSC #define LPSC_VLYNQ 11 // VLYNQ LPSC #define LPSC_UHPI 12 // UHPI LPSC #define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC #define LPSC_AEMIF 14 // AEMIF LPSC #define LPSC_MMC_SD 15 // MMC_SD LPSC #define LPSC_MEMSTICK 16 // MEMSTICK LPSC #define LPSC_McBSP 17 // McBSP LPSC #define LPSC_I2C 18 // I2C LPSC #define LPSC_UART0 19 // UART0 LPSC #define LPSC_UART1 20 // UART1 LPSC #define LPSC_UART2 21 // UART2 LPSC #define LPSC_SPI 22 // SPI LPSC #define LPSC_PWM0 23 // PWM0 LPSC #define LPSC_PWM1 24 // PWM1 LPSC #define LPSC_PWM2 25 // PWM2 LPSC #define LPSC_GPIO 26 // GPIO LPSC #define LPSC_TIMER0 27 // TIMER0 LPSC #define LPSC_TIMER1 28 // TIMER1 LPSC #define LPSC_TIMER2 29 // TIMER2 LPSC #define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC #define LPSC_ARM 31 // ARM LPSC #define LPSC_SCR2 32 // SCR2 LPSC #define LPSC_SCR3 33 // SCR3 LPSC #define LPSC_SCR4 34 // SCR4 LPSC #define LPSC_CROSSBAR 35 // CROSSBAR LPSC #define LPSC_CFG27 36 // CFG27 LPSC #define LPSC_CFG3 37 // CFG3 LPSC #define LPSC_CFG5 38 // CFG5 LPSC #define LPSC_GEM 39 // GEM LPSC #define LPSC_IMCOP 40 // IMCOP LPSC struct psc_regs { volatile unsigned int pid; volatile unsigned int reserved1[3]; volatile unsigned int gblctl; /*--- 0x10 ---*/ volatile unsigned int reserved2; volatile unsigned int inteval; /*--- 0x18 ---*/ volatile unsigned int reserved3[9]; volatile unsigned int merrpr0; /*--- 0x40 ---*/ volatile unsigned int merrpr1; /*--- 0x44 ---*/ volatile unsigned int reserved4[2]; volatile unsigned int merrcr0; /*--- 0x50 ---*/ volatile unsigned int merrcr1; /*--- 0x54 ---*/ volatile unsigned int reserved5[2]; volatile unsigned int perrpr; /*--- 0x60 ---*/ volatile unsigned int reserved6; volatile unsigned int percpr; /*--- 0x68 ---*/ volatile unsigned int reserved7; volatile unsigned int epcpr; /*--- 0x70 ---*/ volatile unsigned int reserved8; volatile unsigned int epccr; /*--- 0x78 ---*/ volatile unsigned int reserved9[33]; volatile unsigned int railstat; /*--- 0x100 ---*/ volatile unsigned int railctl; /*--- 0x104 ---*/ volatile unsigned int railsel; /*--- 0x108 ---*/ volatile unsigned int reserved10[5]; volatile unsigned int ptcmd; /*--- 0x120 ---*/ volatile unsigned int reserved11; volatile unsigned int ptstat; /*--- 0x128 ---*/ volatile unsigned int reserved12[53]; volatile unsigned int pdstat0; /*--- 0x200 ---*/ volatile unsigned int pdstat1; /*--- 0x204 ---*/ volatile unsigned int reserved13[62]; volatile unsigned int pdctl0; /*--- 0x300 ---*/ volatile unsigned int pdctl1; /*--- 0x304 ---*/ volatile unsigned int reserved14[130]; volatile unsigned int mckout0; /*--- 0x510 ---*/ volatile unsigned int mckout1; /*--- 0x514 ---*/ volatile unsigned int reserved15[58]; volatile unsigned int mdcfg[41]; /*--- 0x600 ---*/ volatile unsigned int reserved16[87]; volatile unsigned int mdstat[41]; /*--- 0x800 ---*/ volatile unsigned int reserved17[87]; volatile unsigned int mdctl[41]; /*--- 0xA00 ---*/ volatile unsigned int reserved18[87]; }; #endif