--- zzzz-none-000/linux-2.6.13.1/arch/mips/mips-boards/generic/mipsIRQ.S	2005-09-10 02:42:58.000000000 +0000
+++ ohio-7170-487/linux-2.6.13.1/arch/mips/mips-boards/generic/mipsIRQ.S	2006-11-08 10:37:31.000000000 +0000
@@ -84,24 +84,27 @@
 
 	/* First we check for r4k counter/timer IRQ. */
 	andi	a0, s0, CAUSEF_IP7
-	beq	a0, zero, 1f
-	 andi	a0, s0, CAUSEF_IP2	# delay slot, check hw0 interrupt
+	beq	a0, zero, mips_irq_check_hw_interrupt_0
+	andi	a0, s0, CAUSEF_IP2	# delay slot, check hw0 interrupt
 
 	/* Wheee, a timer interrupt. */
 	move	a0, sp
 	jal	mips_timer_interrupt
-	 nop
+	nop
 
 	j	ret_from_irq
-	 nop
+	nop
 
-1:
-#if defined(CONFIG_MIPS_SEAD)
-	beq	a0, zero, 1f
-	 andi	a0, s0, CAUSEF_IP3	# delay slot, check hw1 interrupt
+    /*--------------------------------------------------------------------------------------*\
+     * Pruefen ob ein HW Interrupt vorliegt
+    \*--------------------------------------------------------------------------------------*/
+mips_irq_check_hw_interrupt_0:
+#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_AR7) || defined(CONFIG_MIPS_OHIO) || defined(CONFIG_MIPS_UR8)
+	beq	a0, zero, mips_irq_check_hw_interrupt_1
+	andi	a0, s0, CAUSEF_IP3	# delay slot, check hw1 interrupt
 #else
-	beq	a0, zero, 1f		# delay slot, check hw3 interrupt
- 	 andi	a0, s0, CAUSEF_IP5
+	beq	a0, zero, mips_irq_check_hw_interrupt_1
+ 	andi	a0, s0, CAUSEF_IP5
 #endif
 
 	/* Wheee, combined hardware level zero interrupt. */
@@ -111,6 +114,12 @@
 	jal	malta_hw0_irqdispatch
 #elif defined(CONFIG_MIPS_SEAD)
 	jal	sead_hw0_irqdispatch
+#elif defined(CONFIG_MIPS_OHIO)
+	jal	ohio_hw0_irqdispatch
+#elif defined(CONFIG_MIPS_AR7)
+	jal	ar7_hw0_irqdispatch
+#elif defined(CONFIG_MIPS_UR8)
+	jal	ur8_hw0_irqdispatch
 #else
 #error "MIPS board not supported\n"
 #endif
@@ -119,16 +128,44 @@
 	j	ret_from_irq
 	 nop				# delay slot
 
-1:
+    /*--------------------------------------------------------------------------------------*\
+     * Pruefen ob ein HW Interrupt vorliegt
+    \*--------------------------------------------------------------------------------------*/
+mips_irq_check_hw_interrupt_1:
 #if defined(CONFIG_MIPS_SEAD)
 	beq	a0, zero, 1f
-	 andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
+	andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
 	jal	sead_hw1_irqdispatch
 	 move	a0, sp			# delay slot
 	j	ret_from_irq
 	 nop				# delay slot
 1:
 #endif
+#if defined(CONFIG_MIPS_OHIO)
+	beq	a0, zero, 1f
+	andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
+	jal	ohio_hw1_irqdispatch
+	 move	a0, sp			# delay slot
+	j	ret_from_irq
+	 nop				# delay slot
+1:
+#elif defined(CONFIG_MIPS_AR7)
+	beq	a0, zero, 1f
+	andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
+	jal	ar7_hw1_irqdispatch
+	 move	a0, sp			# delay slot
+	j	ret_from_irq
+	 nop				# delay slot
+1:
+#elif defined(CONFIG_MIPS_UR8)
+	beq	a0, zero, 1f
+	andi	a0, s0, CAUSEF_IP5	# delay slot, check hw3 interrupt
+	jal	ur8_hw1_irqdispatch
+	 move	a0, sp			# delay slot
+	j	ret_from_irq
+	 nop				# delay slot
+1:
+#endif
 #if defined(CONFIG_MIPS_MALTA)
 	beq	a0, zero, 1f            # check hw3 (coreHI) interrupt
 	 nop
@@ -138,15 +175,15 @@
 	 nop
 1:
 #endif
-	/*
+    /*--------------------------------------------------------------------------------------*\
 	 * Here by mistake?  This is possible, what can happen is that by the
 	 * time we take the exception the IRQ pin goes low, so just leave if
 	 * this is the case.
-	 */
 	move	a1,s0
 	PRINT("Got interrupt: c0_cause = %08x\n")
 	mfc0	a1, CP0_EPC
 	PRINT("c0_epc = %08x\n")
+    \*--------------------------------------------------------------------------------------*/
 
 	j	ret_from_irq
 	 nop