/******************************************************************************
**
** FILE NAME    : ifx_pmon.h
** PROJECT      : IFX UEIP
** MODULES      : PMON
**
** DATE         : 21 July 2009
** AUTHOR       : Lei Chuanhua
** DESCRIPTION  : IFX Performance Monitor
** COPYRIGHT    :       Copyright (c) 2009
**                      Infineon Technologies AG
**                      Am Campeon 1-12, 85579 Neubiberg, Germany
**
**    This program is free software; you can redistribute it and/or modify
**    it under the terms of the GNU General Public License as published by
**    the Free Software Foundation; either version 2 of the License, or
**    (at your option) any later version.
**
** HISTORY
** $Date        $Author         $Comment
** 21 July 2009  Lei Chuanhua    The first UEIP release
*******************************************************************************/

/**
  \defgroup IFX_PMON Performance Monitor Interface Module
  \brief ifx pmon driver module
*/

/*!
  \defgroup IFX_PMON_DEFINITIONS Defintions and structures
  \ingroup IFX_PMON
  \brief definitions for ifx pmon driver 
*/

/*!
  \defgroup IFX_PMON_IOCTL User API IOCTL
  \ingroup IFX_PMON
  \brief IOCTL Commands used by user application.
 */

/*!
  \file ifx_pmon.h
  \ingroup IFX_PMON
  \brief ifx pmon driver header file for APIs
*/
#ifndef IFX_PMON_H
#define IFX_PMON_H
/*!
  \addtogroup IFX_PMON_DEFINITIONS
 */
/* @{ */
/*! \enum  IFX_PMON_EVENT  
    \brief External PMON Event defintion 
 */
enum IFX_PMON_EVENT {
    IFX_PMON_EVENT_NONE     = 0, /*!< No input (default) */
#define IFX_PMON_EVENT_MIN     IFX_PMON_EVENT_NONE            
    IFX_PMON_EVENT_DDR_READ,  /*!< DDR read commands, independent of length */
    IFX_PMON_EVENT_DDR_WRITE, /*!< DDR write commands, independent of length */
    IFX_PMON_EVENT_DDR_MASK_WRITE, /*!< DDR masked write commands */
    IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_READ,/*!< Single-word 64-bit read commands */
    IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_READ,/*!< 2-beat burst 64-bit read commands */
    IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_READ,/*!< 4-word 64-bit read commands */
    IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_READ,/*!< 8-word 64-bit read commands */
    IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_WRITE,/*!< Single 64-bit write commands */
    IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_WRITE, /*!< 2-word 64-bit write commands */
    IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_WRITE,/*!< 4-word 64-bit write commands */
    IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_WIRTE,/*!< 8-word 64-bit write commands */
    IFX_PMON_EVENT_AHB_READ_CYCLES, /*!< DMA 32-bit receive block counter */
    IFX_PMON_EVENT_AHB_READ_CPT,    /*!< DMA 32-bit transmit block counter */
    IFX_PMON_EVENT_AHB_WRITE_CYCLES,/*!< AHB read completed */
    IFX_PMON_EVENT_AHB_WRITE_CPT,   /*!< AHB write completed */
    IFX_PMON_EVENT_DMA_RX_BLOCK_CNT,/*!< AHB total read cycles */
    IFX_PMON_EVENT_DMA_TX_BLOCK_CNT,/*!< AHB total write cycles */
#define IFX_PMON_EVENT_MAX   IFX_PMON_EVENT_DMA_TX_BLOCK_CNT
};

/*! 
 * \def IFX_PMON_PERF_L2WB
 * \brief Map to performance counter 0 L2 Cache Writeback event
 */
#define IFX_PMON_PERF_L2WB        0
/*! 
 * \def IFX_PMON_PERF_L2CACHMISS
 * \brief Map to performance counter 0 L2 Cache Miss event
 */
#define IFX_PMON_PERF_L2CACHMISS  2

/*! 
 * \def IFX_PMON_PERF_L2ACC
 * \brief Map to performance counter 1 L2 Cache Access event
 */
#define IFX_PMON_PERF_L2ACC       1

/*! 
 * \def IFX_PMON_PERF_L2DATAMISS
 * \brief Map to performance counter 1 L2 Data Cache Miss
 */
#define IFX_PMON_PERF_L2DATAMISS  3
/* @} */

#define IFX_PMON_PERF_MIN IFX_PMON_PERF_L2WB
#define IFX_PMON_PERF_MAX IFX_PMON_PERF_L2DATAMISS

/*!
  \addtogroup IFX_PMON_IOCTL
 */
/* @{ */
/*!
    \brief Structure describing pmon version
 */
struct ifx_pmon_ioctl_version {
    unsigned int    major;   /*!< Version Major number */
    unsigned int    mid;     /*!< Version Mid number */
    unsigned int    minor;   /*!< Version Minor number */
};

/*!
    \brief Structure describing pmon event
 */
struct ifx_pmon_ioctl_event {
    unsigned int    pmon_event;   /*!< PMON external even id */
    unsigned int    perf_idx;     /*!< CPU performance counter event idx */
};

/*! 
 * \def IFX_PMON_IOC_MAGIC
 * \brief PMON IOCTL Magic number
 */
#define IFX_PMON_IOC_MAGIC               0xef
/*! 
 * \def IFX_PMON_IOC_VERSION
 * \brief PMON IOCTL to get version number
 */
#define IFX_PMON_IOC_VERSION             _IOR( IFX_PMON_IOC_MAGIC, 0, struct ifx_pmon_ioctl_version)
/*! 
 * \def IFX_PMON_IOC_EVENT
 * \brief PMON IOCTL to configure external event and CPU performance counter 0/1
 */
#define IFX_PMON_IOC_EVENT               _IOWR(IFX_PMON_IOC_MAGIC, 1, struct ifx_pmon_ioctl_event)
/*! 
 * \def IFX_PMON_IOC_DISABLE
 * \brief PMON IOCTL to disable PMON module
 */

#define IFX_PMON_IOC_DISABLE             _IOWR(IFX_PMON_IOC_MAGIC, 2, int)
/* @} */

#endif /* IFX_PMON_H */