/**************************************************************************** Copyright (c) 2010 Lantiq Deutschland GmbH Am Campeon 3; 85579 Neubiberg, Germany For licensing information, see the file 'LICENSE' in the root folder of this software module. ***************************************************************************** \file ifxmips_gphy_sw.h \remarks implement GPHY driver on VR9 platform *****************************************************************************/ #ifndef _IFXMIPS_GPHY_SW_H_ #define _IFXMIPS_GPHY_SW_H_ #include #include #include /** default board related configuration */ #if defined(CONFIG_MII0_PORT_ENABLED) #define CONFIG_MAC0 1 #else #define CONFIG_MAC0 0 #endif #if defined(CONFIG_MII1_PORT_ENABLED) #define CONFIG_MAC1 1 #else #define CONFIG_MAC1 0 #endif #if defined(CONFIG_MII2_PORT_ENABLED) #define CONFIG_MAC2 1 #else #define CONFIG_MAC2 0 #endif #if defined(CONFIG_MII3_PORT_ENABLED) #define CONFIG_MAC3 1 #else #define CONFIG_MAC3 0 #endif #if defined(CONFIG_MII4_PORT_ENABLED) #define CONFIG_MAC4 1 #else #define CONFIG_MAC4 0 #endif #if defined(CONFIG_MII5_PORT_ENABLED) #define CONFIG_MAC5 1 #else #define CONFIG_MAC5 0 #endif #if defined(CONFIG_MII0_RGMII_MAC_MODE) #define MII0_MODE_SETUP RGMII_MODE #elif defined(CONFIG_MII0_RMII_MAC_MODE) #define MII0_MODE_SETUP RMII_MAC_MODE #elif defined(CONFIG_MII0_RMII_PHY_MODE) #define MII0_MODE_SETUP RMII_PHY_MODE #elif defined(CONFIG_MII0_MII_MAC_MODE) #define MII0_MODE_SETUP MII_MAC_MODE #elif defined(CONFIG_MII0_MII_PHY_MODE) #define MII0_MODE_SETUP MII_PHY_MODE #endif #if defined(CONFIG_MII1_RGMII_MAC_MODE) #define MII1_MODE_SETUP RGMII_MODE #elif defined(CONFIG_MII1_RMII_MAC_MODE) #define MII1_MODE_SETUP RMII_MAC_MODE #elif defined(CONFIG_MII1_RMII_PHY_MODE) #define MII1_MODE_SETUP RMII_PHY_MODE #elif defined(CONFIG_MII1_MII_MAC_MODE) #define MII1_MODE_SETUP MII_MAC_MODE #elif defined(CONFIG_MII1_MII_PHY_MODE) #define MII1_MODE_SETUP MII_PHY_MODE #endif #if defined(CONFIG_MII2_GMII_MODE) #define MII2_MODE_SETUP GMII_MAC_MODE #elif defined(CONFIG_MII2_MII_MAC_MODE) #define MII2_MODE_SETUP MII_MAC_MODE #endif #if defined(CONFIG_MII3_MII_MAC_MODE) #define MII3_MODE_SETUP MII_MAC_MODE #endif #if defined(CONFIG_MII4_GMII_MODE) #define MII4_MODE_SETUP GMII_MAC_MODE #elif defined(CONFIG_MII4_MII_MAC_MODE) #define MII4_MODE_SETUP MII_MAC_MODE #endif #if defined(CONFIG_MII5_RGMII_MODE) #define MII5_MODE_SETUP RGMII_MODE #elif defined(CONFIG_MII5_MII_MAC_MODE) #define MII5_MODE_SETUP MII_PHY_MODE #endif #ifdef CONFIG_VR9 #define NUM_ETH_INF 4 #define CONFIG_PMAC_DMA_ENABLE 1 /*g_pmac_dma */ #define CONFIG_DMA_PMAC_ENABLE 1 /*g_dma_pmac*/ #else /*--- #ifdef CONFIG_VR9 ---*/ #ifdef CONFIG_SW_ROUTING_MODE #define CONFIG_PMAC_DMA_ENABLE 1 /*g_pmac_dma */ #define CONFIG_DMA_PMAC_ENABLE 1 /*g_dma_pmac*/ #else #define CONFIG_PMAC_DMA_ENABLE 0 /*g_pmac_dma */ #define CONFIG_DMA_PMAC_ENABLE 0 /*g_dma_pmac*/ #endif #if defined(CONFIG_PMAC_DMA_ENABLE) && CONFIG_PMAC_DMA_ENABLE #define NUM_ETH_INF 2 #else #define NUM_ETH_INF 1 #endif #endif /*--- #else ---*/ /*--- #ifdef CONFIG_VR9 ---*/ #define GPHY_FW_LEN 65536 static const char gphy_fw_data[GPHY_FW_LEN]; static inline void ifxmips_mdelay( int delay){ int i; for ( i=delay; i > 0; i--) udelay(1000); } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ void vr9_write_mdio(unsigned int phyAddr, unsigned int regAddr,unsigned int data ) { unsigned int reg; reg = SW_READ_REG32(MDIO_CTRL_REG); while (reg & MDIO_CTRL_MBUSY ) { reg = SW_READ_REG32(MDIO_CTRL_REG); } reg = MDIO_READ_WDATA(data); SW_WRITE_REG32( reg, MDIO_WRITE_REG); reg = ( MDIO_CTRL_OP_WR | MDIO_CTRL_PHYAD_SET(phyAddr) | MDIO_CTRL_REGAD(regAddr) ); reg |= MDIO_CTRL_MBUSY; SW_WRITE_REG32( reg, MDIO_CTRL_REG); udelay(100); reg = SW_READ_REG32(MDIO_CTRL_REG); while (reg & MDIO_CTRL_MBUSY ) { reg = SW_READ_REG32(MDIO_CTRL_REG); udelay(10); } return ; } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ unsigned short vr9_read_mdio(unsigned int phyAddr, unsigned int regAddr ) { unsigned int reg; reg = SW_READ_REG32(MDIO_CTRL_REG); while (reg & MDIO_CTRL_MBUSY ) { reg = SW_READ_REG32(MDIO_CTRL_REG); } reg = ( MDIO_CTRL_OP_RD | MDIO_CTRL_PHYAD_SET(phyAddr) | MDIO_CTRL_REGAD(regAddr) ); reg |= MDIO_CTRL_MBUSY; SW_WRITE_REG32( reg, MDIO_CTRL_REG); reg = SW_READ_REG32(MDIO_CTRL_REG); while (reg & MDIO_CTRL_MBUSY ) { reg = SW_READ_REG32(MDIO_CTRL_REG); } reg = SW_READ_REG32(MDIO_READ_REG); return (MDIO_READ_RDATA(reg)); } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ int vr9_gphy_reset(int phy_num_mask) { unsigned int reg; reg = ifx_rcu_rst_req_read(); if ( phy_num_mask & 0x01 ) reg |= (1 << 31); if ( phy_num_mask & 0x02 ) reg |= (1 << 29); ifx_rcu_rst_req_write(reg, reg); return 0; } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ int vr9_gphy_reset_released(int phy_num_mask) { unsigned int reg; reg = ifx_rcu_rst_req_read(); if ( phy_num_mask & 0x01 ) reg |= ( 1 << 31 ); if ( phy_num_mask & 0x02 ) reg |= ( 1 << 29 ); ifx_rcu_rst_req_write(0, reg); return 0; } #if 0 /*------------------------------------------------------------------------------------------*\ * seit UGW 4.3.1 \*------------------------------------------------------------------------------------------*/ int vr9_gphy_reset_released(int phy_num) { unsigned int mask = 0; if (phy_num == 2) mask = ( 1 << 31 ) | (1 << 29); else if ( phy_num == 0 ) mask = ( 1 << 31 ); else if ( phy_num == 1 ) mask = ( 1 << 29 ); else return 1; ifx_rcu_rst_req_write(0, mask); return 0; } #endif /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ int vr9_gphy_pmu_set(void) { /* Config GPIO3 clock */ SWITCH_PMU_SETUP(IFX_PMU_ENABLE); GPHY_PMU_SETUP(IFX_PMU_ENABLE); return 0; } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ int vr9_gphy_gpio_init(void) { unsigned int reg; /* Config GPIO3 clock */ // SW_WRITE_REG32( 0x2008, P0_ALTSEL0); // SW_WRITE_REG32( 0x80, P0_ALTSEL1); /* Set direction */ // SW_WRITE_REG32( 0x2000, P0_DIR); ifx_gpio_register(IFX_GPIO_MODULE_INTERNAL_SWITCH); /* Config GPHY clock mux to take clock from GPIO3 */ reg = SW_READ_REG32(IF_CLK); reg = (reg & ~(7 << 2)) | (4 << 2); SW_WRITE_REG32(reg, IF_CLK); return 0; } /*------------------------------------------------------------------------------------------*\ \*------------------------------------------------------------------------------------------*/ int vr9_phy_hw_init(void) { /* GPHY Init routine if necessary */ return 0; } #endif /*_IFXMIPS_GPHY_SW_H_ */