#ifndef _ARCH_ASM_MACH_VIRIAN_AR7242_H_ #define _ARCH_ASM_MACH_VIRIAN_AR7242_H_ #define VIRIAN_USB_REGISTER_OFFSET 0x00000000 #define VIRIAN_DDR_REGISTER_OFFSET 0x18000000 #define VIRIAN_UART_REGISTER_OFFSET 0x18020000 #define VIRIAN_GPIO_REGISTER_OFFSET 0x18040000 #define VIRIAN_PLL_CONTROL_REGISTER_OFFSET 0x18050000 #define VIRIAN_RESET_REGISTER_OFFSET 0x18060000 #define VIRIAN_GMAC_REGISTER_OFFSET 0x18070000 #define VIRIAN_MBOX_REGISTER_OFFSET 0x180A0000 #define VIRIAN_I2S_REGISTER_OFFSET 0x180B0000 #define VIRIAN_PCIE_REGISTER_OFFSET 0x180F0000 #define VIRIAN_ETH0_REGISTER_OFFSET 0x19000000 #define VIRIAN_ETH1_REGISTER_OFFSET 0x1A000000 #define VIRIAN_SPI_REGISTER_OFFSET 0x1F000000 #define VIRIAN_MAC_REGISTER_OFFSET 0x00000000 #define VIRIAN_PCIE_CONFIG_REGISTER_OFFSET 0x10000000 /*------------------------------------------------------------------------------------------*\ SPI Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_SPI_CONTROL_REGISTER (SPI_REGISTER_OFFSET + 0x00000004) #define VIRIAN_SPI_CONTROL_REMAP_DISABLE_SHIFT 6 #define VIRIAN_SPI_CONTROL_REMAP_DISABLE_MASK (((1 << 1) - 1) << 6) #define VIRIAN_SPI_CONTROL_REMAP_DISABLE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_SPI_CONTROL_REMAP_DISABLE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_CONTROL_REGISTER)) >> 6) #define VIRIAN_SPI_CONTROL_CLOCK_DIVIDER_SHIFT 0 #define VIRIAN_SPI_CONTROL_CLOCK_DIVIDER_MASK (((1 << 6) - 1) << 0) #define VIRIAN_SPI_CONTROL_CLOCK_DIVIDER_SET_VALUE(value) ((((1 << 6) - 1) & (value)) << 0) #define VIRIAN_SPI_CONTROL_CLOCK_DIVIDER_GET_VALUE ((((1 << 6) - 1) & *((volatile unsigned int *)VIRIAN_SPI_CONTROL_REGISTER)) >> 0) typedef union __virian_spi_control { struct _virian_spi_control { volatile unsigned int reserved1 : 25; /*--- Bits 7 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int REMAP_DISABLE : 1; /*--- Bit 6 Remaps 4 MB space over unless explicity disabled by setting this bit to 1. If set to 1, 16 MB is accessible. ---*/ volatile unsigned int CLOCK_DIVIDER : 6; /*--- Bits 0 ... 5 Specifies the clock devider setting. Actual clock frequency would be (AHB_CLK/((CLOCK_DIVIDER+1)*2)). Therefore by default, if the AHB_CLK is 200 MHz, this would give 200/18 = ~ 11 MHz ---*/ } Bits; volatile unsigned int Register; } virian_spi_control_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Interrupt Type \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_INT_TYPE_REGISTER (GPIO_REGISTER_OFFSET + 0x00000018) #define VIRIAN_GPIO_INT_TYPE_TYPE_SHIFT 0 #define VIRIAN_GPIO_INT_TYPE_TYPE_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_INT_TYPE_TYPE_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_INT_TYPE_TYPE_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_INT_TYPE_REGISTER)) >> 0) typedef union __virian_gpio_int_type { struct _virian_gpio_int_type { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int TYPE : 20; /*--- Bits 0 ... 19 0 = Indicates the bit is a level-sensitive interrupt, 1 = Indicates the bit is an edge-sensitive interrupt ---*/ } Bits; volatile unsigned int Register; } virian_gpio_int_type_t; /*------------------------------------------------------------------------------------------*\ Watchdog Timer Control Register \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_REGISTER (RST_REGISTER_OFFSET + 0x00000008) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_LAST_SHIFT 31 #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_LAST_MASK (((1 << 1) - 1) << 31) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_LAST_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 31) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_LAST_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_WATCHDOG_TIMER_CONTROL_REGISTER)) >> 31) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_ACTION_SHIFT 0 #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_ACTION_MASK (((1 << 2) - 1) << 0) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_ACTION_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_RST_WATCHDOG_TIMER_CONTROL_ACTION_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_RST_WATCHDOG_TIMER_CONTROL_REGISTER)) >> 0) typedef union __virian_rst_watchdog_timer_control { struct _virian_rst_watchdog_timer_control { volatile const unsigned int LAST : 1; /*--- Bit 31 Indicates if the last reset was due to a watchdog timeout ---*/ volatile const unsigned int reserved1 : 29; /*--- Bits 2 ... 30 Reserved. Must be written with zero. Contains zero when read. ---*/ volatile unsigned int ACTION : 2; /*--- Bits 0 ... 1 The action to be taken after timer reaches zero (00 = No action, 01 = General purpose interrupt, 10 Non-maskable interrupt, 11 = Full chip reset) ---*/ } Bits; volatile unsigned int Register; } virian_rst_watchdog_timer_control_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Interrupt Mask \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_INT_MASK_REGISTER (GPIO_REGISTER_OFFSET + 0x00000024) #define VIRIAN_GPIO_INT_MASK_MASK_SHIFT 0 #define VIRIAN_GPIO_INT_MASK_MASK_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_INT_MASK_MASK_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_INT_MASK_MASK_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_INT_MASK_REGISTER)) >> 0) typedef union __virian_gpio_int_mask { struct _virian_gpio_int_mask { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int MASK : 20; /*--- Bits 0 ... 19 For each bit that is set, the corresponding interrupt in the register 'General Purpose I/O Interrupt Pending (GPIO_INT_PENDING)' is passed on to the central interrupt controller ---*/ } Bits; volatile unsigned int Register; } virian_gpio_int_mask_t; /*------------------------------------------------------------------------------------------*\ FIFO Timeout Period \*------------------------------------------------------------------------------------------*/ #define VIRIAN_FIFO_TIMEOUT_REGISTER (MBOX_REGISTER_OFFSET + 0x00000034) #define VIRIAN_FIFO_TIMEOUT_ENABLE_SHIFT 8 #define VIRIAN_FIFO_TIMEOUT_ENABLE_MASK (((1 << 1) - 1) << 8) #define VIRIAN_FIFO_TIMEOUT_ENABLE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_FIFO_TIMEOUT_ENABLE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_FIFO_TIMEOUT_REGISTER)) >> 8) #define VIRIAN_FIFO_TIMEOUT_VALUE_SHIFT 0 #define VIRIAN_FIFO_TIMEOUT_VALUE_MASK (((1 << 8) - 1) << 0) #define VIRIAN_FIFO_TIMEOUT_VALUE_SET_VALUE(value) ((((1 << 8) - 1) & (value)) << 0) #define VIRIAN_FIFO_TIMEOUT_VALUE_GET_VALUE ((((1 << 8) - 1) & *((volatile unsigned int *)VIRIAN_FIFO_TIMEOUT_REGISTER)) >> 0) typedef union __virian_fifo_timeout { struct _virian_fifo_timeout { volatile unsigned int reserved1 : 23; /*--- Bits 9 ... 31 Reserved ---*/ volatile unsigned int ENABLE : 1; /*--- Bit 8 0 = FIFO timeouts are disabled, 1 = FIFO timeouts are enabled ---*/ volatile unsigned int VALUE : 8; /*--- Bits 0 ... 7 Timeout value (in ms) when CORE_CLK = 40 MHz, or in 0.5 ms when CORE_CLK = 80 MHz; should never be set to 0 ---*/ } Bits; volatile unsigned int Register; } virian_fifo_timeout_t; /*------------------------------------------------------------------------------------------*\ Global Interrupt Status \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER (RST_REGISTER_OFFSET + 0x00000018) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_SHIFT 5 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_MASK (((1 << 1) - 1) << 5) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 5) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_SHIFT 4 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_MASK (((1 << 1) - 1) << 4) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 4) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_SHIFT 3 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_MASK (((1 << 1) - 1) << 3) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 3) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_SHIFT 2 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_MASK (((1 << 1) - 1) << 2) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 2) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_USB_INT_SHIFT 1 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_USB_INT_MASK (((1 << 1) - 1) << 1) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_USB_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_USB_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 1) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_SHIFT 0 #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_MASK (((1 << 1) - 1) << 0) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER)) >> 0) typedef union __virian_rst_global_interrupt_status { struct _virian_rst_global_interrupt_status { volatile const unsigned int reserved1 : 26; /*--- Bits 6 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile const unsigned int TIMER_INT : 1; /*--- Bit 5 Internal count/compare timer interrupt ---*/ volatile const unsigned int MISC_INT : 1; /*--- Bit 4 Miscellaneous interrupt; source of the interrupt available on the 'Miscellaneous Interrupt Status (RST_MISC_INTERRUPT_STATUS)' register ---*/ volatile const unsigned int GE1_INT : 1; /*--- Bit 3 Ethernet1 interrupt; information available in the Ethernet1 register space ---*/ volatile const unsigned int GE0_INT : 1; /*--- Bit 2 Ethernet0 interrupt; information available in the Ethernet0 register space ---*/ volatile const unsigned int USB_INT : 1; /*--- Bit 1 USB interrupt; information available in the USB register space ---*/ volatile const unsigned int PCIE_INT : 1; /*--- Bit 0 PCIE interrupt ---*/ } Bits; volatile unsigned int Register; } virian_rst_global_interrupt_status_t; /*------------------------------------------------------------------------------------------*\ USB PHY Charger Detection \*------------------------------------------------------------------------------------------*/ #define VIRIAN_USB_PHY_CHARGER_REGISTER (USB_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_USB_PHY_CHARGER_CHGRDET_SHIFT 4 #define VIRIAN_USB_PHY_CHARGER_CHGRDET_MASK (((1 << 1) - 1) << 4) #define VIRIAN_USB_PHY_CHARGER_CHGRDET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_USB_PHY_CHARGER_CHGRDET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_CHARGER_REGISTER)) >> 4) #define VIRIAN_USB_PHY_CHARGER_ONDCD_SHIFT 3 #define VIRIAN_USB_PHY_CHARGER_ONDCD_MASK (((1 << 1) - 1) << 3) #define VIRIAN_USB_PHY_CHARGER_ONDCD_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_USB_PHY_CHARGER_ONDCD_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_CHARGER_REGISTER)) >> 3) #define VIRIAN_USB_PHY_CHARGER_CHGRMODE_SHIFT 2 #define VIRIAN_USB_PHY_CHARGER_CHGRMODE_MASK (((1 << 1) - 1) << 2) #define VIRIAN_USB_PHY_CHARGER_CHGRMODE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_USB_PHY_CHARGER_CHGRMODE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_CHARGER_REGISTER)) >> 2) #define VIRIAN_USB_PHY_CHARGER_CHGRDETEN_SHIFT 1 #define VIRIAN_USB_PHY_CHARGER_CHGRDETEN_MASK (((1 << 1) - 1) << 1) #define VIRIAN_USB_PHY_CHARGER_CHGRDETEN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_USB_PHY_CHARGER_CHGRDETEN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_CHARGER_REGISTER)) >> 1) #define VIRIAN_USB_PHY_CHARGER_CHGRDETON_SHIFT 0 #define VIRIAN_USB_PHY_CHARGER_CHGRDETON_MASK (((1 << 1) - 1) << 0) #define VIRIAN_USB_PHY_CHARGER_CHGRDETON_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_USB_PHY_CHARGER_CHGRDETON_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_CHARGER_REGISTER)) >> 0) typedef union __virian_usb_phy_charger { struct _virian_usb_phy_charger { volatile unsigned int reserved1 : 27; /*--- Bits 5 ... 31 Reserved ---*/ volatile unsigned int CHGRDET : 1; /*--- Bit 4 Charger detector output ---*/ volatile unsigned int ONDCD : 1; /*--- Bit 3 Enables data contact detect circuitry. Note: Cannot be asserted together with EN_CHGRDET ---*/ volatile unsigned int CHGRMODE : 1; /*--- Bit 2 Charger detector mode. Note: Maximum response time = 10ms (0 = Host charger detection, 1 = Device charger detection) ---*/ volatile unsigned int CHGRDETEN : 1; /*--- Bit 1 Enable charger detector ---*/ volatile unsigned int CHGRDETON : 1; /*--- Bit 0 Charger detector power on control. Note: Must be asserted at least 10ms before EN_CHGRDET assertion ---*/ } Bits; volatile unsigned int Register; } virian_usb_phy_charger_t; /*------------------------------------------------------------------------------------------*\ Reset and Clear MBOX FIFOs \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_FIFO_RESET_REGISTER (MBOX_REGISTER_OFFSET + 0x00000040) #define VIRIAN_MBOX_FIFO_RESET_RX_INIT_SHIFT 2 #define VIRIAN_MBOX_FIFO_RESET_RX_INIT_MASK (((1 << 2) - 1) << 2) #define VIRIAN_MBOX_FIFO_RESET_RX_INIT_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 2) #define VIRIAN_MBOX_FIFO_RESET_RX_INIT_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FIFO_RESET_REGISTER)) >> 2) #define VIRIAN_MBOX_FIFO_RESET_TX_INIT_SHIFT 0 #define VIRIAN_MBOX_FIFO_RESET_TX_INIT_MASK (((1 << 2) - 1) << 0) #define VIRIAN_MBOX_FIFO_RESET_TX_INIT_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_MBOX_FIFO_RESET_TX_INIT_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FIFO_RESET_REGISTER)) >> 0) typedef union __virian_mbox_fifo_reset { struct _virian_mbox_fifo_reset { volatile unsigned int reserved1 : 28; /*--- Bits 4 ... 31 Reserved ---*/ volatile unsigned int RX_INIT : 2; /*--- Bits 2 ... 3 Writing a 1 causes a Rx FIFO reset. The register is automatically reset to 0, and will always return 0 on a read. (RX_INIT[0] = Resets MBOX 0, RX_INIT[1] = Resets MBOX 1) ---*/ volatile unsigned int TX_INIT : 2; /*--- Bits 0 ... 1 Writing a 1 causes a Tx FIFO reset. The register is automatically reset to 0, and will always return 0 on a read. (TX_INIT[0] = Resets MBOX 0, TX_INIT[1] = Resets MBOX 1) ---*/ } Bits; volatile unsigned int Register; } virian_mbox_fifo_reset_t; /*------------------------------------------------------------------------------------------*\ DDR Read Data Capture Bit Mask \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_RD_DATA_THIS_CYCLE_REGISTER (DDR_REGISTER_OFFSET + 0x00000018) #define VIRIAN_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0 #define VIRIAN_DDR_RD_DATA_THIS_CYCLE_VEC_MASK (((1 << 24) - 1) << 0) #define VIRIAN_DDR_RD_DATA_THIS_CYCLE_VEC_SET_VALUE(value) ((((1 << 24) - 1) & (value)) << 0) #define VIRIAN_DDR_RD_DATA_THIS_CYCLE_VEC_GET_VALUE ((((1 << 24) - 1) & *((volatile unsigned int *)VIRIAN_DDR_RD_DATA_THIS_CYCLE_REGISTER)) >> 0) typedef union __virian_ddr_rd_data_this_cycle { struct _virian_ddr_rd_data_this_cycle { volatile unsigned int reserved1 : 8; /*--- Bits 24 ... 31 Reserved ---*/ volatile unsigned int VEC : 24; /*--- Bits 0 ... 23 Each bit represents a cycle of valid data ---*/ } Bits; volatile unsigned int Register; } virian_ddr_rd_data_this_cycle_t; /*------------------------------------------------------------------------------------------*\ USB Configuration \*------------------------------------------------------------------------------------------*/ #define VIRIAN_USB_CONFIG_REGISTER (USB_REGISTER_OFFSET + 0x00000004) #define VIRIAN_USB_CONFIG_CONF3_SHIFT 18 #define VIRIAN_USB_CONFIG_CONF3_MASK (((1 << 1) - 1) << 18) #define VIRIAN_USB_CONFIG_CONF3_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 18) #define VIRIAN_USB_CONFIG_CONF3_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 18) #define VIRIAN_USB_CONFIG_CONF2_SHIFT 17 #define VIRIAN_USB_CONFIG_CONF2_MASK (((1 << 1) - 1) << 17) #define VIRIAN_USB_CONFIG_CONF2_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 17) #define VIRIAN_USB_CONFIG_CONF2_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 17) #define VIRIAN_USB_CONFIG_EXTCAL_SHIFT 12 #define VIRIAN_USB_CONFIG_EXTCAL_MASK (((1 << 5) - 1) << 12) #define VIRIAN_USB_CONFIG_EXTCAL_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 12) #define VIRIAN_USB_CONFIG_EXTCAL_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 12) #define VIRIAN_USB_CONFIG_CALBP_SHIFT 11 #define VIRIAN_USB_CONFIG_CALBP_MASK (((1 << 1) - 1) << 11) #define VIRIAN_USB_CONFIG_CALBP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 11) #define VIRIAN_USB_CONFIG_CALBP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 11) #define VIRIAN_USB_CONFIG_CLK_SEL_SHIFT 9 #define VIRIAN_USB_CONFIG_CLK_SEL_MASK (((1 << 2) - 1) << 9) #define VIRIAN_USB_CONFIG_CLK_SEL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 9) #define VIRIAN_USB_CONFIG_CLK_SEL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 9) #define VIRIAN_USB_CONFIG_HOST_ONLY_SHIFT 8 #define VIRIAN_USB_CONFIG_HOST_ONLY_MASK (((1 << 1) - 1) << 8) #define VIRIAN_USB_CONFIG_HOST_ONLY_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_USB_CONFIG_HOST_ONLY_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 8) #define VIRIAN_USB_CONFIG_PHY_TEST_MODE_SHIFT 7 #define VIRIAN_USB_CONFIG_PHY_TEST_MODE_MASK (((1 << 1) - 1) << 7) #define VIRIAN_USB_CONFIG_PHY_TEST_MODE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 7) #define VIRIAN_USB_CONFIG_PHY_TEST_MODE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 7) #define VIRIAN_USB_CONFIG_CORE_TEST_MODE_SHIFT 6 #define VIRIAN_USB_CONFIG_CORE_TEST_MODE_MASK (((1 << 1) - 1) << 6) #define VIRIAN_USB_CONFIG_CORE_TEST_MODE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_USB_CONFIG_CORE_TEST_MODE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 6) #define VIRIAN_USB_CONFIG_AHB_HRDATA_SWAP_SHIFT 5 #define VIRIAN_USB_CONFIG_AHB_HRDATA_SWAP_MASK (((1 << 1) - 1) << 5) #define VIRIAN_USB_CONFIG_AHB_HRDATA_SWAP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_USB_CONFIG_AHB_HRDATA_SWAP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 5) #define VIRIAN_USB_CONFIG_AHB_HWDATA_SWAP_SHIFT 4 #define VIRIAN_USB_CONFIG_AHB_HWDATA_SWAP_MASK (((1 << 1) - 1) << 4) #define VIRIAN_USB_CONFIG_AHB_HWDATA_SWAP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_USB_CONFIG_AHB_HWDATA_SWAP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 4) #define VIRIAN_USB_CONFIG_HS_MODE_EN_SHIFT 2 #define VIRIAN_USB_CONFIG_HS_MODE_EN_MASK (((1 << 1) - 1) << 2) #define VIRIAN_USB_CONFIG_HS_MODE_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_USB_CONFIG_HS_MODE_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 2) #define VIRIAN_USB_CONFIG_UTMI_PHY_EN_SHIFT 1 #define VIRIAN_USB_CONFIG_UTMI_PHY_EN_MASK (((1 << 1) - 1) << 1) #define VIRIAN_USB_CONFIG_UTMI_PHY_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_USB_CONFIG_UTMI_PHY_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 1) #define VIRIAN_USB_CONFIG_ONCLOCK_SHIFT 0 #define VIRIAN_USB_CONFIG_ONCLOCK_MASK (((1 << 1) - 1) << 0) #define VIRIAN_USB_CONFIG_ONCLOCK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_USB_CONFIG_ONCLOCK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_CONFIG_REGISTER)) >> 0) typedef union __virian_usb_config { struct _virian_usb_config { volatile unsigned int reserved1 : 13; /*--- Bits 19 ... 31 Reserved ---*/ volatile unsigned int CONF3 : 1; /*--- Bit 18 During non-driving (opmode < 1:0> = 01): If conf3 = 1, the 15 K pulldown resistors are connected (if dppulldown = dnpulldown = 1); should be tied to 0 for device-only applications ---*/ volatile unsigned int CONF2 : 1; /*--- Bit 17 Active high; when asserted, turns on OTG comparators during suspend (SUSPEND = 0) ---*/ volatile unsigned int EXTCAL : 5; /*--- Bits 12 ... 16 Externally controls calibration values; valid when CALBP = 1 ---*/ volatile unsigned int CALBP : 1; /*--- Bit 11 Enables calibration bypass for both DP and DN lines ---*/ volatile unsigned int CLK_SEL : 2; /*--- Bits 9 ... 10 select input clock frequency to USB PHY (0 = 12, 1 = 19.2, 2 = 24, 3 = Reserved) ---*/ volatile unsigned int HOST_ONLY : 1; /*--- Bit 8 If set to 1, the IDPULLUP input to UTMI PHY is tied to 0 to make sure the ID signal is not sampled by the PHY ---*/ volatile unsigned int PHY_TEST_MODE : 1; /*--- Bit 7 Bypass the USB core and connect all USB PHY I/Os to the USB PHY test bus ---*/ volatile unsigned int CORE_TEST_MODE : 1; /*--- Bit 6 Bypass the USB PHY and connect all USB core I/Os to the USB CORE test bus ---*/ volatile unsigned int AHB_HRDATA_SWAP : 1; /*--- Bit 5 Swap the read data on AHB bus ---*/ volatile unsigned int AHB_HWDATA_SWAP : 1; /*--- Bit 4 Swap the write data on AHB bus ---*/ volatile unsigned int reserved2 : 1; /*--- Bit 3 Reserved ---*/ volatile const unsigned int HS_MODE_EN : 1; /*--- Bit 2 Asserted when the HS interface is selected ---*/ volatile const unsigned int UTMI_PHY_EN : 1; /*--- Bit 1 Asserted when the UTMI interface is selected ---*/ volatile unsigned int ONCLOCK : 1; /*--- Bit 0 Allows system clocks to clock out and the SIE clock to be available even if suspend is asserted ---*/ } Bits; volatile unsigned int Register; } virian_usb_config_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Output value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_OUT_REGISTER (GPIO_REGISTER_OFFSET + 0x00000008) #define VIRIAN_GPIO_OUT_OUT_SHIFT 0 #define VIRIAN_GPIO_OUT_OUT_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_OUT_OUT_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_OUT_OUT_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_OUT_REGISTER)) >> 0) typedef union __virian_gpio_out { struct _virian_gpio_out { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int OUT : 20; /*--- Bits 0 ... 19 Driver output value. If the corresponding bit in the OE register is set to 1, the GPIO pin will drive the value in the corresponding bit of the register ---*/ } Bits; volatile unsigned int Register; } virian_gpio_out_t; /*------------------------------------------------------------------------------------------*\ Reset \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_RESET_REGISTER (RST_REGISTER_OFFSET + 0x0000001C) #define VIRIAN_RST_RESET_EXTERNAL_RESET_SHIFT 28 #define VIRIAN_RST_RESET_EXTERNAL_RESET_MASK (((1 << 1) - 1) << 28) #define VIRIAN_RST_RESET_EXTERNAL_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 28) #define VIRIAN_RST_RESET_EXTERNAL_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 28) #define VIRIAN_RST_RESET_FULL_CHIP_RESET_SHIFT 24 #define VIRIAN_RST_RESET_FULL_CHIP_RESET_MASK (((1 << 1) - 1) << 24) #define VIRIAN_RST_RESET_FULL_CHIP_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 24) #define VIRIAN_RST_RESET_FULL_CHIP_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 24) #define VIRIAN_RST_RESET_CPU_NMI_SHIFT 21 #define VIRIAN_RST_RESET_CPU_NMI_MASK (((1 << 1) - 1) << 21) #define VIRIAN_RST_RESET_CPU_NMI_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 21) #define VIRIAN_RST_RESET_CPU_NMI_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 21) #define VIRIAN_RST_RESET_CPU_COLD_RESET_SHIFT 20 #define VIRIAN_RST_RESET_CPU_COLD_RESET_MASK (((1 << 1) - 1) << 20) #define VIRIAN_RST_RESET_CPU_COLD_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 20) #define VIRIAN_RST_RESET_CPU_COLD_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 20) #define VIRIAN_RST_RESET_DDR_RESET_SHIFT 16 #define VIRIAN_RST_RESET_DDR_RESET_MASK (((1 << 1) - 1) << 16) #define VIRIAN_RST_RESET_DDR_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 16) #define VIRIAN_RST_RESET_DDR_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 16) #define VIRIAN_RST_RESET_GE1_MAC_RESET_SHIFT 13 #define VIRIAN_RST_RESET_GE1_MAC_RESET_MASK (((1 << 1) - 1) << 13) #define VIRIAN_RST_RESET_GE1_MAC_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 13) #define VIRIAN_RST_RESET_GE1_MAC_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 13) #define VIRIAN_RST_RESET_PCIE_PHY_SERIAL_RESET_SHIFT 10 #define VIRIAN_RST_RESET_PCIE_PHY_SERIAL_RESET_MASK (((1 << 1) - 1) << 10) #define VIRIAN_RST_RESET_PCIE_PHY_SERIAL_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 10) #define VIRIAN_RST_RESET_PCIE_PHY_SERIAL_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 10) #define VIRIAN_RST_RESET_GE0_MAC_RESET_SHIFT 9 #define VIRIAN_RST_RESET_GE0_MAC_RESET_MASK (((1 << 1) - 1) << 9) #define VIRIAN_RST_RESET_GE0_MAC_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 9) #define VIRIAN_RST_RESET_GE0_MAC_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 9) #define VIRIAN_RST_RESET_ETH_MACPHY_RESET_SHIFT 8 #define VIRIAN_RST_RESET_ETH_MACPHY_RESET_MASK (((1 << 1) - 1) << 8) #define VIRIAN_RST_RESET_ETH_MACPHY_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_RST_RESET_ETH_MACPHY_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 8) #define VIRIAN_RST_RESET_PCIE_PHY_RESET_SHIFT 7 #define VIRIAN_RST_RESET_PCIE_PHY_RESET_MASK (((1 << 1) - 1) << 7) #define VIRIAN_RST_RESET_PCIE_PHY_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 7) #define VIRIAN_RST_RESET_PCIE_PHY_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 7) #define VIRIAN_RST_RESET_PCIE_RESET_SHIFT 6 #define VIRIAN_RST_RESET_PCIE_RESET_MASK (((1 << 1) - 1) << 6) #define VIRIAN_RST_RESET_PCIE_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_RST_RESET_PCIE_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 6) #define VIRIAN_RST_RESET_USB_HOST_RESET_SHIFT 5 #define VIRIAN_RST_RESET_USB_HOST_RESET_MASK (((1 << 1) - 1) << 5) #define VIRIAN_RST_RESET_USB_HOST_RESET_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_RST_RESET_USB_HOST_RESET_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_RESET_REGISTER)) >> 5) typedef union __virian_rst_reset { struct _virian_rst_reset { volatile unsigned int reserved1 : 3; /*--- Bits 29 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int EXTERNAL_RESET : 1; /*--- Bit 28 Commands an external reset (SYS_RST_L pin); inverted before being sent to the pin. ---*/ volatile unsigned int reserved2 : 3; /*--- Bits 25 ... 27 Reserved ---*/ volatile unsigned int FULL_CHIP_RESET : 1; /*--- Bit 24 Used to command a full chip reset. this is the software equivalent of pulling the reset pin. The system will reboot with PLL disabled. Always zero when read. ---*/ volatile unsigned int reserved3 : 2; /*--- Bits 22 ... 23 Reserved ---*/ volatile unsigned int CPU_NMI : 1; /*--- Bit 21 Used to send an NMI to the CPU. always zero when read. ---*/ volatile unsigned int CPU_COLD_RESET : 1; /*--- Bit 20 Used to cold reset the CPU. Always zero when read. ---*/ volatile unsigned int reserved4 : 3; /*--- Bits 17 ... 19 Reserved ---*/ volatile unsigned int DDR_RESET : 1; /*--- Bit 16 Used to reset the DDR controller ---*/ volatile unsigned int reserved5 : 2; /*--- Bits 14 ... 15 Reserved ---*/ volatile unsigned int GE1_MAC_RESET : 1; /*--- Bit 13 Used to reset the GE1 MAC ---*/ volatile unsigned int reserved6 : 2; /*--- Bits 11 ... 12 Reserved ---*/ volatile unsigned int PCIE_PHY_SERIAL_RESET : 1; /*--- Bit 10 Resets the PCIE PHY Shift reset ---*/ volatile unsigned int GE0_MAC_RESET : 1; /*--- Bit 9 Resetes the GE0 MAC ---*/ volatile unsigned int ETH_MACPHY_RESET : 1; /*--- Bit 8 Resets the Ethernet MAC/PHY ---*/ volatile unsigned int PCIE_PHY_RESET : 1; /*--- Bit 7 Used to reset the PCIE host controller ---*/ volatile unsigned int PCIE_RESET : 1; /*--- Bit 6 Used to reset the PCIE host controller. This bit will reset the endpoint as well. ---*/ volatile unsigned int USB_HOST_RESET : 1; /*--- Bit 5 Used to reset the USB controller ---*/ volatile unsigned int reserved7 : 1; /*--- Bit 4 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int reserved8 : 4; /*--- Bits 0 ... 3 Reserved ---*/ } Bits; volatile unsigned int Register; } virian_rst_reset_t; /*------------------------------------------------------------------------------------------*\ Mailbox 0 Rx DMA Descriptors Base Address \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_REGISTER (MBOX_REGISTER_OFFSET + 0x00000010) #define VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SHIFT 2 #define VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK (((1 << 26) - 1) << 2) #define VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET_VALUE(value) ((((1 << 26) - 1) & (value)) << 2) #define VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET_VALUE ((((1 << 26) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_REGISTER)) >> 2) typedef union __virian_mbox0_dma_rx_descriptor_base { struct _virian_mbox0_dma_rx_descriptor_base { volatile unsigned int reserved1 : 4; /*--- Bits 28 ... 31 Reserved ---*/ volatile unsigned int ADDRESS : 26; /*--- Bits 2 ... 27 Most significant 26 bits of the 4-byte-aligned address of the first descriptor in the DMA ---*/ volatile unsigned int reserved2 : 2; /*--- Bits 0 ... 1 Reserved ---*/ } Bits; volatile unsigned int Register; } virian_mbox0_dma_rx_descriptor_base_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Output enable \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_OE_REGISTER (GPIO_REGISTER_OFFSET + 0x00000000) #define VIRIAN_GPIO_OE_OE_SHIFT 0 #define VIRIAN_GPIO_OE_OE_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_OE_OE_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_OE_OE_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_OE_REGISTER)) >> 0) typedef union __virian_gpio_oe { struct _virian_gpio_oe { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Must to set to zero ---*/ volatile unsigned int OE : 20; /*--- Bits 0 ... 19 Per bit output enable; bits[19:18] must be set to 0x3 by software; bits[17:13] cannot be set as inputs. (0 = this bit is used as input, 1 = enables the bit as output) ---*/ } Bits; volatile unsigned int Register; } virian_gpio_oe_t; /*------------------------------------------------------------------------------------------*\ DDR Bank Arbiter Per Client Burst Size \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_BURST_REGISTER (DDR_REGISTER_OFFSET + 0x00000098) #define VIRIAN_DDR_BURST_CPU_PRIORITY_SHIFT 31 #define VIRIAN_DDR_BURST_CPU_PRIORITY_MASK (((1 << 1) - 1) << 31) #define VIRIAN_DDR_BURST_CPU_PRIORITY_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 31) #define VIRIAN_DDR_BURST_CPU_PRIORITY_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 31) #define VIRIAN_DDR_BURST_CPU_PRIORITY_BE_SHIFT 30 #define VIRIAN_DDR_BURST_CPU_PRIORITY_BE_MASK (((1 << 1) - 1) << 30) #define VIRIAN_DDR_BURST_CPU_PRIORITY_BE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 30) #define VIRIAN_DDR_BURST_CPU_PRIORITY_BE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 30) #define VIRIAN_DDR_BURST_ENABLE_RWP_MASK_SHIFT 28 #define VIRIAN_DDR_BURST_ENABLE_RWP_MASK_MASK (((1 << 2) - 1) << 28) #define VIRIAN_DDR_BURST_ENABLE_RWP_MASK_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 28) #define VIRIAN_DDR_BURST_ENABLE_RWP_MASK_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 28) #define VIRIAN_DDR_BURST_MAX_WRITE_BURST_SHIFT 24 #define VIRIAN_DDR_BURST_MAX_WRITE_BURST_MASK (((1 << 4) - 1) << 24) #define VIRIAN_DDR_BURST_MAX_WRITE_BURST_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 24) #define VIRIAN_DDR_BURST_MAX_WRITE_BURST_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 24) #define VIRIAN_DDR_BURST_MAX_READ_BURST_SHIFT 20 #define VIRIAN_DDR_BURST_MAX_READ_BURST_MASK (((1 << 4) - 1) << 20) #define VIRIAN_DDR_BURST_MAX_READ_BURST_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 20) #define VIRIAN_DDR_BURST_MAX_READ_BURST_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 20) #define VIRIAN_DDR_BURST_CPU_MAX_BL_SHIFT 16 #define VIRIAN_DDR_BURST_CPU_MAX_BL_MASK (((1 << 4) - 1) << 16) #define VIRIAN_DDR_BURST_CPU_MAX_BL_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 16) #define VIRIAN_DDR_BURST_CPU_MAX_BL_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 16) #define VIRIAN_DDR_BURST_USB_MAX_BL_SHIFT 12 #define VIRIAN_DDR_BURST_USB_MAX_BL_MASK (((1 << 4) - 1) << 12) #define VIRIAN_DDR_BURST_USB_MAX_BL_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 12) #define VIRIAN_DDR_BURST_USB_MAX_BL_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 12) #define VIRIAN_DDR_BURST_PCIE_MAX_BL_SHIFT 8 #define VIRIAN_DDR_BURST_PCIE_MAX_BL_MASK (((1 << 4) - 1) << 8) #define VIRIAN_DDR_BURST_PCIE_MAX_BL_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 8) #define VIRIAN_DDR_BURST_PCIE_MAX_BL_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 8) #define VIRIAN_DDR_BURST_GE1_MAX_BL_SHIFT 4 #define VIRIAN_DDR_BURST_GE1_MAX_BL_MASK (((1 << 4) - 1) << 4) #define VIRIAN_DDR_BURST_GE1_MAX_BL_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 4) #define VIRIAN_DDR_BURST_GE1_MAX_BL_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 4) #define VIRIAN_DDR_BURST_GE0_MAX_BL_SHIFT 0 #define VIRIAN_DDR_BURST_GE0_MAX_BL_MASK (((1 << 4) - 1) << 0) #define VIRIAN_DDR_BURST_GE0_MAX_BL_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 0) #define VIRIAN_DDR_BURST_GE0_MAX_BL_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_BURST_REGISTER)) >> 0) typedef union __virian_ddr_burst { struct _virian_ddr_burst { volatile unsigned int CPU_PRIORITY : 1; /*--- Bit 31 Setting this bit causes bank arbiters to break the current burst and grant CPU ---*/ volatile unsigned int CPU_PRIORITY_BE : 1; /*--- Bit 30 Setting it makes the bank arbiters to break only at current burst completion and grant CPU ---*/ volatile unsigned int ENABLE_RWP_MASK : 2; /*--- Bits 28 ... 29 Enable read/write mask, precharge mask ---*/ volatile unsigned int MAX_WRITE_BURST : 4; /*--- Bits 24 ... 27 Max write burst size until reads are masked in BANK_ARB ---*/ volatile unsigned int MAX_READ_BURST : 4; /*--- Bits 20 ... 23 Max read burst size until writes are maeked in BANK_ARB ---*/ volatile unsigned int CPU_MAX_BL : 4; /*--- Bits 16 ... 19 USB burst size ---*/ volatile unsigned int USB_MAX_BL : 4; /*--- Bits 12 ... 15 USB burst size ---*/ volatile unsigned int PCIE_MAX_BL : 4; /*--- Bits 8 ... 11 PCIE burst size ---*/ volatile unsigned int GE1_MAX_BL : 4; /*--- Bits 4 ... 7 GE1 burst size ---*/ volatile unsigned int GE0_MAX_BL : 4; /*--- Bits 0 ... 3 Ethernet burst size ---*/ } Bits; volatile unsigned int Register; } virian_ddr_burst_t; /*------------------------------------------------------------------------------------------*\ Watchdog Timer Register \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_watchdog_TIMER_REGISTER (RST_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_RST_watchdog_TIMER_TIMER_SHIFT 0 #define VIRIAN_RST_watchdog_TIMER_TIMER_MASK (((1 << 32) - 1) << 0) #define VIRIAN_RST_watchdog_TIMER_TIMER_SET_VALUE(value) ((((1 << 32) - 1) & (value)) << 0) #define VIRIAN_RST_watchdog_TIMER_TIMER_GET_VALUE ((((1 << 32) - 1) & *((volatile unsigned int *)VIRIAN_RST_watchdog_TIMER_REGISTER)) >> 0) typedef union __virian_rst_watchdog_timer { struct _virian_rst_watchdog_timer { volatile unsigned int TIMER : 32; /*--- Bits 0 ... 31 Counts down to zero until the software sets this timer to another value. These bits should be set to a non-zero value before updating the 'Watchdog Timer Control Register (RST_WATCHDOG_TIMER_CONTROL)' register to a non-zero number. ---*/ } Bits; volatile unsigned int Register; } virian_rst_watchdog_timer_t; /*------------------------------------------------------------------------------------------*\ Miscellaneous Interrupt Mask \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER (RST_REGISTER_OFFSET + 0x00000014) #define VIRIAN_RST_MISC_INTERRUPT_MASK_ETH_MAC_INT_MASK_SHIFT 12 #define VIRIAN_RST_MISC_INTERRUPT_MASK_ETH_MAC_INT_MASK_MASK (((1 << 1) - 1) << 12) #define VIRIAN_RST_MISC_INTERRUPT_MASK_ETH_MAC_INT_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 12) #define VIRIAN_RST_MISC_INTERRUPT_MASK_ETH_MAC_INT_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 12) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER3_MASK_SHIFT 10 #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER3_MASK_MASK (((1 << 1) - 1) << 10) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER3_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 10) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER3_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 10) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER2_MASK_SHIFT 9 #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER2_MASK_MASK (((1 << 1) - 1) << 9) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER2_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 9) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER2_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 9) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER1_MASK_SHIFT 8 #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER1_MASK_MASK (((1 << 1) - 1) << 8) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER1_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER1_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 8) #define VIRIAN_RST_MISC_INTERRUPT_MASK_MBOX_MASK_SHIFT 7 #define VIRIAN_RST_MISC_INTERRUPT_MASK_MBOX_MASK_MASK (((1 << 1) - 1) << 7) #define VIRIAN_RST_MISC_INTERRUPT_MASK_MBOX_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 7) #define VIRIAN_RST_MISC_INTERRUPT_MASK_MBOX_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 7) #define VIRIAN_RST_MISC_INTERRUPT_MASK_PC_MASK_SHIFT 5 #define VIRIAN_RST_MISC_INTERRUPT_MASK_PC_MASK_MASK (((1 << 1) - 1) << 5) #define VIRIAN_RST_MISC_INTERRUPT_MASK_PC_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_RST_MISC_INTERRUPT_MASK_PC_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 5) #define VIRIAN_RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_SHIFT 4 #define VIRIAN_RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_MASK (((1 << 1) - 1) << 4) #define VIRIAN_RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 4) #define VIRIAN_RST_MISC_INTERRUPT_MASK_UART_MASK_SHIFT 3 #define VIRIAN_RST_MISC_INTERRUPT_MASK_UART_MASK_MASK (((1 << 1) - 1) << 3) #define VIRIAN_RST_MISC_INTERRUPT_MASK_UART_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_RST_MISC_INTERRUPT_MASK_UART_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 3) #define VIRIAN_RST_MISC_INTERRUPT_MASK_GPIO_MASK_SHIFT 2 #define VIRIAN_RST_MISC_INTERRUPT_MASK_GPIO_MASK_MASK (((1 << 1) - 1) << 2) #define VIRIAN_RST_MISC_INTERRUPT_MASK_GPIO_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_RST_MISC_INTERRUPT_MASK_GPIO_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 2) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER_MASK_SHIFT 0 #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER_MASK_MASK (((1 << 1) - 1) << 0) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER_MASK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_RST_MISC_INTERRUPT_MASK_TIMER_MASK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER)) >> 0) typedef union __virian_rst_misc_interrupt_mask { struct _virian_rst_misc_interrupt_mask { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int ETH_MAC_INT_MASK : 1; /*--- Bit 12 Enables the interrupt generated by the Ethernet MAC/PHY ---*/ volatile unsigned int reserved2 : 1; /*--- Bit 11 Reserved ---*/ volatile unsigned int TIMER3_MASK : 1; /*--- Bit 10 When set, enables Timer 3 interrupt ---*/ volatile unsigned int TIMER2_MASK : 1; /*--- Bit 9 When set, enables Timer 2 interrupt ---*/ volatile unsigned int TIMER1_MASK : 1; /*--- Bit 8 When set, enables Timer 1 interrupt ---*/ volatile unsigned int MBOX_MASK : 1; /*--- Bit 7 When set, enables MBOX interrupt ---*/ volatile unsigned int reserved3 : 1; /*--- Bit 6 Reserved ---*/ volatile unsigned int PC_MASK : 1; /*--- Bit 5 When set, enables CPU performance counter interrupt ---*/ volatile unsigned int WATCHDOG_MASK : 1; /*--- Bit 4 When set, enables UART interrupt ---*/ volatile unsigned int UART_MASK : 1; /*--- Bit 3 When set, enables GPIO interrupt ---*/ volatile unsigned int GPIO_MASK : 1; /*--- Bit 2 When set, ---*/ volatile unsigned int reserved4 : 1; /*--- Bit 1 Reserved ---*/ volatile unsigned int TIMER_MASK : 1; /*--- Bit 0 When set, enables timer interrupt ---*/ } Bits; volatile unsigned int Register; } virian_rst_misc_interrupt_mask_t; /*------------------------------------------------------------------------------------------*\ DDR Extended Mode Value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_EXTENDED_MODE_REGISTER_REGISTER (DDR_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_DDR_EXTENDED_MODE_REGISTER_VALUE_SHIFT 0 #define VIRIAN_DDR_EXTENDED_MODE_REGISTER_VALUE_MASK (((1 << 13) - 1) << 0) #define VIRIAN_DDR_EXTENDED_MODE_REGISTER_VALUE_SET_VALUE(value) ((((1 << 13) - 1) & (value)) << 0) #define VIRIAN_DDR_EXTENDED_MODE_REGISTER_VALUE_GET_VALUE ((((1 << 13) - 1) & *((volatile unsigned int *)VIRIAN_DDR_EXTENDED_MODE_REGISTER_REGISTER)) >> 0) typedef union __virian_ddr_extended_mode_register { struct _virian_ddr_extended_mode_register { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved ---*/ volatile unsigned int VALUE : 13; /*--- Bits 0 ... 12 Extende4d mode register value. Reset to weak driver, DLL on ---*/ } Bits; volatile unsigned int Register; } virian_ddr_extended_mode_register_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Per Bit Set \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_SET_REGISTER (GPIO_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_GPIO_SET_SET_SHIFT 0 #define VIRIAN_GPIO_SET_SET_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_SET_SET_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_SET_SET_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_SET_REGISTER)) >> 0) typedef union __virian_gpio_set { struct _virian_gpio_set { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int SET : 20; /*--- Bits 0 ... 19 One a write, any bit that is set causes the corresponding GPIO bit to be set; any bit that is not set will have no effect ---*/ } Bits; volatile unsigned int Register; } virian_gpio_set_t; /*------------------------------------------------------------------------------------------*\ DDR Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_CONTROL_REGISTER (DDR_REGISTER_OFFSET + 0x00000010) #define VIRIAN_DDR_CONTROL_EMR3_SHIFT 5 #define VIRIAN_DDR_CONTROL_EMR3_MASK (((1 << 1) - 1) << 5) #define VIRIAN_DDR_CONTROL_EMR3_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_DDR_CONTROL_EMR3_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 5) #define VIRIAN_DDR_CONTROL_EMR2_SHIFT 4 #define VIRIAN_DDR_CONTROL_EMR2_MASK (((1 << 1) - 1) << 4) #define VIRIAN_DDR_CONTROL_EMR2_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_DDR_CONTROL_EMR2_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 4) #define VIRIAN_DDR_CONTROL_PREA_SHIFT 3 #define VIRIAN_DDR_CONTROL_PREA_MASK (((1 << 1) - 1) << 3) #define VIRIAN_DDR_CONTROL_PREA_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_DDR_CONTROL_PREA_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 3) #define VIRIAN_DDR_CONTROL_REF_SHIFT 2 #define VIRIAN_DDR_CONTROL_REF_MASK (((1 << 1) - 1) << 2) #define VIRIAN_DDR_CONTROL_REF_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_DDR_CONTROL_REF_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 2) #define VIRIAN_DDR_CONTROL_EMRS_SHIFT 1 #define VIRIAN_DDR_CONTROL_EMRS_MASK (((1 << 1) - 1) << 1) #define VIRIAN_DDR_CONTROL_EMRS_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_DDR_CONTROL_EMRS_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 1) #define VIRIAN_DDR_CONTROL_MRS_SHIFT 0 #define VIRIAN_DDR_CONTROL_MRS_MASK (((1 << 1) - 1) << 0) #define VIRIAN_DDR_CONTROL_MRS_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_DDR_CONTROL_MRS_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONTROL_REGISTER)) >> 0) typedef union __virian_ddr_control { struct _virian_ddr_control { volatile unsigned int reserved1 : 26; /*--- Bits 6 ... 31 Reserved ---*/ volatile unsigned int EMR3 : 1; /*--- Bit 5 Force an EMR3S update cycle ---*/ volatile unsigned int EMR2 : 1; /*--- Bit 4 Force an EMR2S update cycle ---*/ volatile unsigned int PREA : 1; /*--- Bit 3 Force a PRECHARGE ALL cycle ---*/ volatile unsigned int REF : 1; /*--- Bit 2 Force an AUTO REFRESH cycle ---*/ volatile unsigned int EMRS : 1; /*--- Bit 1 Force an EMRS update cycle ---*/ volatile unsigned int MRS : 1; /*--- Bit 0 Force a MRS update cycle ---*/ } Bits; volatile unsigned int Register; } virian_ddr_control_t; /*------------------------------------------------------------------------------------------*\ DDR2 Configuration \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_DDR2_CONFIG_REGISTER (DDR_REGISTER_OFFSET + 0x0000008C) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TWL_SHIFT 10 #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TWL_MASK (((1 << 3) - 1) << 10) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TWL_SET_VALUE(value) ((((1 << 3) - 1) & (value)) << 10) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TWL_GET_VALUE ((((1 << 3) - 1) & *((volatile unsigned int *)VIRIAN_DDR_DDR2_CONFIG_REGISTER)) >> 10) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TFAW_SHIFT 2 #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TFAW_MASK (((1 << 6) - 1) << 2) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TFAW_SET_VALUE(value) ((((1 << 6) - 1) & (value)) << 2) #define VIRIAN_DDR_DDR2_CONFIG_DDR2_TFAW_GET_VALUE ((((1 << 6) - 1) & *((volatile unsigned int *)VIRIAN_DDR_DDR2_CONFIG_REGISTER)) >> 2) #define VIRIAN_DDR_DDR2_CONFIG_ENABLE_DDR2_SHIFT 0 #define VIRIAN_DDR_DDR2_CONFIG_ENABLE_DDR2_MASK (((1 << 1) - 1) << 0) #define VIRIAN_DDR_DDR2_CONFIG_ENABLE_DDR2_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_DDR_DDR2_CONFIG_ENABLE_DDR2_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_DDR2_CONFIG_REGISTER)) >> 0) typedef union __virian_ddr_ddr2_config { struct _virian_ddr_ddr2_config { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved ---*/ volatile unsigned int DDR2_TWL : 3; /*--- Bits 10 ... 12 Delay between WE_L/CAS_L assertion on DQS, DQ assertion for a DDR2 write transaction (in DDR_CLK cycles) ---*/ volatile unsigned int reserved2 : 2; /*--- Bits 8 ... 9 Reserved ---*/ volatile unsigned int DDR2_TFAW : 6; /*--- Bits 2 ... 7 tFAW parameter in core DDR_CLK cycles ---*/ volatile unsigned int reserved3 : 1; /*--- Bit 1 Reserved ---*/ volatile unsigned int ENABLE_DDR2 : 1; /*--- Bit 0 (0 = DDR1, 1 = DDR2) ---*/ } Bits; volatile unsigned int Register; } virian_ddr_ddr2_config_t; /*------------------------------------------------------------------------------------------*\ Non-Destructive FIFO Status Query \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_FIFO_STATUS_REGISTER (MBOX_REGISTER_OFFSET + 0x00000008) #define VIRIAN_MBOX_FIFO_STATUS_EMPTY_SHIFT 2 #define VIRIAN_MBOX_FIFO_STATUS_EMPTY_MASK (((1 << 2) - 1) << 2) #define VIRIAN_MBOX_FIFO_STATUS_EMPTY_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 2) #define VIRIAN_MBOX_FIFO_STATUS_EMPTY_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FIFO_STATUS_REGISTER)) >> 2) #define VIRIAN_MBOX_FIFO_STATUS_FULL_SHIFT 0 #define VIRIAN_MBOX_FIFO_STATUS_FULL_MASK (((1 << 2) - 1) << 0) #define VIRIAN_MBOX_FIFO_STATUS_FULL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_MBOX_FIFO_STATUS_FULL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FIFO_STATUS_REGISTER)) >> 0) typedef union __virian_mbox_fifo_status { struct _virian_mbox_fifo_status { volatile const unsigned int reserved1 : 28; /*--- Bits 4 ... 31 Reserved ---*/ volatile const unsigned int EMPTY : 2; /*--- Bits 2 ... 3 On a read: returns an empty status for the Tx mailbox (Bit[3] = MBOX 1 Tx FIFO is empty (I2S1), Bit[2] = MBOX 0 Tx FIFO is empty (I2S0)) ---*/ volatile const unsigned int FULL : 2; /*--- Bits 0 ... 1 On a read: returns an empty status for the Rx mailbox (Bit[3] = MBOX 1 Rx FIFO is empty (I2S1), Bit[2] = MBOX 0 Rx FIFO is empty (I2S0)) ---*/ } Bits; volatile unsigned int Register; } virian_mbox_fifo_status_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Input Value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_ETH_LED_REGISTER (GPIO_REGISTER_OFFSET + 0x0000002C) #define VIRIAN_ETH_LED_LINK_SHIFT 15 #define VIRIAN_ETH_LED_LINK_MASK (((1 << 5) - 1) << 15) #define VIRIAN_ETH_LED_LINK_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 15) #define VIRIAN_ETH_LED_LINK_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_ETH_LED_REGISTER)) >> 15) #define VIRIAN_ETH_LED_DUPL_SHIFT 10 #define VIRIAN_ETH_LED_DUPL_MASK (((1 << 5) - 1) << 10) #define VIRIAN_ETH_LED_DUPL_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 10) #define VIRIAN_ETH_LED_DUPL_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_ETH_LED_REGISTER)) >> 10) #define VIRIAN_ETH_LED_COLL_SHIFT 5 #define VIRIAN_ETH_LED_COLL_MASK (((1 << 5) - 1) << 5) #define VIRIAN_ETH_LED_COLL_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 5) #define VIRIAN_ETH_LED_COLL_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_ETH_LED_REGISTER)) >> 5) #define VIRIAN_ETH_LED_ACTV_SHIFT 0 #define VIRIAN_ETH_LED_ACTV_MASK (((1 << 5) - 1) << 0) #define VIRIAN_ETH_LED_ACTV_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 0) #define VIRIAN_ETH_LED_ACTV_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_ETH_LED_REGISTER)) >> 0) typedef union __virian_eth_led { struct _virian_eth_led { volatile const unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile const unsigned int LINK : 5; /*--- Bits 15 ... 19 Current value of LED_LINK100N_O and LED_LINK10N_O ---*/ volatile const unsigned int DUPL : 5; /*--- Bits 10 ... 14 Current value of LED_DUPLEXN_O ---*/ volatile const unsigned int COLL : 5; /*--- Bits 5 ... 9 Current value of LED_COLN_O ---*/ volatile const unsigned int ACTV : 5; /*--- Bits 0 ... 4 Current value of LED_ACTN_O ---*/ } Bits; volatile unsigned int Register; } virian_eth_led_t; /*------------------------------------------------------------------------------------------*\ Miscellaneous Interrupt Status \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER (RST_REGISTER_OFFSET + 0x00000010) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_ETH_MAC_INT_SHIFT 12 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_ETH_MAC_INT_MASK (((1 << 1) - 1) << 12) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_ETH_MAC_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 12) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_ETH_MAC_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 12) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER3_INT_SHIFT 10 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER3_INT_MASK (((1 << 1) - 1) << 10) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER3_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 10) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER3_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 10) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER2_INT_SHIFT 9 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER2_INT_MASK (((1 << 1) - 1) << 9) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER2_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 9) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER2_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 9) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER1_INT_SHIFT 8 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER1_INT_MASK (((1 << 1) - 1) << 8) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER1_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER1_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 8) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_PC_INT_SHIFT 5 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_PC_INT_MASK (((1 << 1) - 1) << 5) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_PC_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_PC_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 5) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_SHIFT 4 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_MASK (((1 << 1) - 1) << 4) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 4) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_UART_INT_SHIFT 3 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_UART_INT_MASK (((1 << 1) - 1) << 3) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_UART_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_UART_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 3) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_GPIO_INT_SHIFT 2 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_GPIO_INT_MASK (((1 << 1) - 1) << 2) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_GPIO_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_GPIO_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 2) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER_INT_SHIFT 0 #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER_INT_MASK (((1 << 1) - 1) << 0) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER_INT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_RST_MISC_INTERRUPT_STATUS_TIMER_INT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER)) >> 0) typedef union __virian_rst_misc_interrupt_status { struct _virian_rst_misc_interrupt_status { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int ETH_MAC_INT : 1; /*--- Bit 12 The interrupt generated by the Ethernet MAC/PHY. ---*/ volatile unsigned int reserved2 : 1; /*--- Bit 11 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int TIMER3_INT : 1; /*--- Bit 10 The interrupt corresponding to General Purpose Timer3. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register. ---*/ volatile unsigned int TIMER2_INT : 1; /*--- Bit 9 The interrupt corresponding to General Purpose Timer2. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register. ---*/ volatile unsigned int TIMER1_INT : 1; /*--- Bit 8 The interrupt corresponding to General Purpose Timer1. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register. ---*/ volatile unsigned int reserved3 : 2; /*--- Bits 6 ... 7 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int PC_INT : 1; /*--- Bit 5 CPU performance counter interrupt. Generated whenever either of the internal CPU performance counters have bit[31] set. The relevant performance counter must be reset to clear this interrupt. ---*/ volatile unsigned int WATCHDOG_INT : 1; /*--- Bit 4 The watchdog timer interrupt. this interrupt is generated when the watchdog timer reaches zero and the watchdog configuration register is configured to generate a general-purpose interrupt. ---*/ volatile unsigned int UART_INT : 1; /*--- Bit 3 The UART interrupt. UART interrupt registers must be read before this interrupt can be cleared. ---*/ volatile unsigned int GPIO_INT : 1; /*--- Bit 2 the GPIO interrupt. Individual lines ust be masked before this interrupt can be cleared. ---*/ volatile unsigned int reserved4 : 1; /*--- Bit 1 Reserved ---*/ volatile unsigned int TIMER_INT : 1; /*--- Bit 0 The interrupt corresponding to General Purpose Timer0. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register. ---*/ } Bits; volatile unsigned int Register; } virian_rst_misc_interrupt_status_t; /*------------------------------------------------------------------------------------------*\ DDR DRAM Configuration \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_CONFIG_REGISTER (DDR_REGISTER_OFFSET + 0x00000000) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_MSB_SHIFT 31 #define VIRIAN_DDR_CONFIG_CAS_LATENCY_MSB_MASK (((1 << 1) - 1) << 31) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_MSB_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 31) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_MSB_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 31) #define VIRIAN_DDR_CONFIG_OPEN_PAGE_SHIFT 30 #define VIRIAN_DDR_CONFIG_OPEN_PAGE_MASK (((1 << 1) - 1) << 30) #define VIRIAN_DDR_CONFIG_OPEN_PAGE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 30) #define VIRIAN_DDR_CONFIG_OPEN_PAGE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 30) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_SHIFT 27 #define VIRIAN_DDR_CONFIG_CAS_LATENCY_MASK (((1 << 3) - 1) << 27) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_SET_VALUE(value) ((((1 << 3) - 1) & (value)) << 27) #define VIRIAN_DDR_CONFIG_CAS_LATENCY_GET_VALUE ((((1 << 3) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 27) #define VIRIAN_DDR_CONFIG_TMRD_SHIFT 23 #define VIRIAN_DDR_CONFIG_TMRD_MASK (((1 << 4) - 1) << 23) #define VIRIAN_DDR_CONFIG_TMRD_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 23) #define VIRIAN_DDR_CONFIG_TMRD_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 23) #define VIRIAN_DDR_CONFIG_TRFC_SHIFT 17 #define VIRIAN_DDR_CONFIG_TRFC_MASK (((1 << 6) - 1) << 17) #define VIRIAN_DDR_CONFIG_TRFC_SET_VALUE(value) ((((1 << 6) - 1) & (value)) << 17) #define VIRIAN_DDR_CONFIG_TRFC_GET_VALUE ((((1 << 6) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 17) #define VIRIAN_DDR_CONFIG_TRRD_SHIFT 13 #define VIRIAN_DDR_CONFIG_TRRD_MASK (((1 << 4) - 1) << 13) #define VIRIAN_DDR_CONFIG_TRRD_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 13) #define VIRIAN_DDR_CONFIG_TRRD_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 13) #define VIRIAN_DDR_CONFIG_TRP_SHIFT 9 #define VIRIAN_DDR_CONFIG_TRP_MASK (((1 << 4) - 1) << 9) #define VIRIAN_DDR_CONFIG_TRP_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 9) #define VIRIAN_DDR_CONFIG_TRP_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 9) #define VIRIAN_DDR_CONFIG_TRCD_SHIFT 5 #define VIRIAN_DDR_CONFIG_TRCD_MASK (((1 << 4) - 1) << 5) #define VIRIAN_DDR_CONFIG_TRCD_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 5) #define VIRIAN_DDR_CONFIG_TRCD_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 5) #define VIRIAN_DDR_CONFIG_TRAS_SHIFT 0 #define VIRIAN_DDR_CONFIG_TRAS_MASK (((1 << 5) - 1) << 0) #define VIRIAN_DDR_CONFIG_TRAS_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 0) #define VIRIAN_DDR_CONFIG_TRAS_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG_REGISTER)) >> 0) typedef union __virian_ddr_config { struct _virian_ddr_config { volatile unsigned int CAS_LATENCY_MSB : 1; /*--- Bit 31 MSB bit of 4-bit CAS_LATENCY field ---*/ volatile unsigned int OPEN_PAGE : 1; /*--- Bit 30 Controller open page policy; open page policy increases bus efficiency if accesses are local to a page but increase random read/write latency (0 - Page open, 1 - Page closed) ---*/ volatile unsigned int CAS_LATENCY : 3; /*--- Bits 27 ... 29 DRAM CAS latency parameter (first 3 bits) rounded up in memory core clock cycles; CAS_LATENCY is used by the hardware to estimate the internal DDR clock latency of a read; it should be grester than or equal to GATE_OPEN_LATENCY as specified in the DDR_CONFIG2 register. The value of this register should be memory cas_latency * 2 or cas_latency * 2 + 1 / 2 / 3. ---*/ volatile unsigned int TMRD : 4; /*--- Bits 23 ... 26 DRAM tMRD parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRFC : 6; /*--- Bits 17 ... 22 DRAM tRFC parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRRD : 4; /*--- Bits 13 ... 16 DRAM tRRD parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRP : 4; /*--- Bits 9 ... 12 DRAM tRP parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRCD : 4; /*--- Bits 5 ... 8 DRAM tRCD parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRAS : 5; /*--- Bits 0 ... 4 DRAM tRAS parameter rounded up in memory core clock cycles ---*/ } Bits; volatile unsigned int Register; } virian_ddr_config_t; /*------------------------------------------------------------------------------------------*\ Write Buffer Flush for USB Interface \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_WB_FLUSH_USB_REGISTER (DDR_REGISTER_OFFSET + 0x00000084) #define VIRIAN_DDR_WB_FLUSH_USB_FLUSH_SHIFT 0 #define VIRIAN_DDR_WB_FLUSH_USB_FLUSH_MASK (((1 << 1) - 1) << 0) #define VIRIAN_DDR_WB_FLUSH_USB_FLUSH_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_DDR_WB_FLUSH_USB_FLUSH_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_WB_FLUSH_USB_REGISTER)) >> 0) typedef union __virian_ddr_wb_flush_usb { struct _virian_ddr_wb_flush_usb { volatile unsigned int reserved1 : 31; /*--- Bits 1 ... 31 Reserved ---*/ volatile unsigned int FLUSH : 1; /*--- Bit 0 Set to 1 to flush; will reset to 0 when flush is complete ---*/ } Bits; volatile unsigned int Register; } virian_ddr_wb_flush_usb_t; /*------------------------------------------------------------------------------------------*\ SPI I/O Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_SPI_IO_CONTROL_REGISTER (SPI_REGISTER_OFFSET + 0x00000008) #define VIRIAN_SPI_IO_CONTROL_IO_CS_2_SHIFT 18 #define VIRIAN_SPI_IO_CONTROL_IO_CS_2_MASK (((1 << 1) - 1) << 18) #define VIRIAN_SPI_IO_CONTROL_IO_CS_2_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 18) #define VIRIAN_SPI_IO_CONTROL_IO_CS_2_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_IO_CONTROL_REGISTER)) >> 18) #define VIRIAN_SPI_IO_CONTROL_IO_CS_1_SHIFT 17 #define VIRIAN_SPI_IO_CONTROL_IO_CS_1_MASK (((1 << 1) - 1) << 17) #define VIRIAN_SPI_IO_CONTROL_IO_CS_1_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 17) #define VIRIAN_SPI_IO_CONTROL_IO_CS_1_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_IO_CONTROL_REGISTER)) >> 17) #define VIRIAN_SPI_IO_CONTROL_IO_CS_0_SHIFT 16 #define VIRIAN_SPI_IO_CONTROL_IO_CS_0_MASK (((1 << 1) - 1) << 16) #define VIRIAN_SPI_IO_CONTROL_IO_CS_0_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 16) #define VIRIAN_SPI_IO_CONTROL_IO_CS_0_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_IO_CONTROL_REGISTER)) >> 16) #define VIRIAN_SPI_IO_CONTROL_IO_CLOCK_SHIFT 8 #define VIRIAN_SPI_IO_CONTROL_IO_CLOCK_MASK (((1 << 1) - 1) << 8) #define VIRIAN_SPI_IO_CONTROL_IO_CLOCK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 8) #define VIRIAN_SPI_IO_CONTROL_IO_CLOCK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_IO_CONTROL_REGISTER)) >> 8) #define VIRIAN_SPI_IO_CONTROL_IO_DO_SHIFT 0 #define VIRIAN_SPI_IO_CONTROL_IO_DO_MASK (((1 << 1) - 1) << 0) #define VIRIAN_SPI_IO_CONTROL_IO_DO_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_SPI_IO_CONTROL_IO_DO_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_IO_CONTROL_REGISTER)) >> 0) typedef union __virian_spi_io_control { struct _virian_spi_io_control { volatile unsigned int reserved1 : 13; /*--- Bits 19 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int IO_CS_2 : 1; /*--- Bit 18 This chip select 2 bit to be output ---*/ volatile unsigned int IO_CS_1 : 1; /*--- Bit 17 This chip select 1 bit to be output ---*/ volatile unsigned int IO_CS_0 : 1; /*--- Bit 16 This chip select 0 bit to be output ---*/ volatile unsigned int IO_CLOCK : 1; /*--- Bit 8 The clock bit to be output ---*/ volatile unsigned int reserved2 : 7; /*--- Bits 1 ... 7 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int IO_DO : 1; /*--- Bit 0 the data bit to be output ---*/ } Bits; volatile unsigned int Register; } virian_spi_io_control_t; /*------------------------------------------------------------------------------------------*\ Extended GPIO Function Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_FUNCTION_2_REGISTER (GPIO_REGISTER_OFFSET + 0x00000030) #define VIRIAN_GPIO_FUNCTION_2_I2SD_ON_12_SHIFT 5 #define VIRIAN_GPIO_FUNCTION_2_I2SD_ON_12_MASK (((1 << 1) - 1) << 5) #define VIRIAN_GPIO_FUNCTION_2_I2SD_ON_12_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_GPIO_FUNCTION_2_I2SD_ON_12_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_2_REGISTER)) >> 5) #define VIRIAN_GPIO_FUNCTION_2_EN_I2WS_ON_0_SHIFT 4 #define VIRIAN_GPIO_FUNCTION_2_EN_I2WS_ON_0_MASK (((1 << 1) - 1) << 4) #define VIRIAN_GPIO_FUNCTION_2_EN_I2WS_ON_0_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_GPIO_FUNCTION_2_EN_I2WS_ON_0_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_2_REGISTER)) >> 4) #define VIRIAN_GPIO_FUNCTION_2_EN_I2SCK_ON_1_SHIFT 3 #define VIRIAN_GPIO_FUNCTION_2_EN_I2SCK_ON_1_MASK (((1 << 1) - 1) << 3) #define VIRIAN_GPIO_FUNCTION_2_EN_I2SCK_ON_1_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_GPIO_FUNCTION_2_EN_I2SCK_ON_1_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_2_REGISTER)) >> 3) #define VIRIAN_GPIO_FUNCTION_2_I2S_ON_LED_SHIFT 1 #define VIRIAN_GPIO_FUNCTION_2_I2S_ON_LED_MASK (((1 << 1) - 1) << 1) #define VIRIAN_GPIO_FUNCTION_2_I2S_ON_LED_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_GPIO_FUNCTION_2_I2S_ON_LED_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_2_REGISTER)) >> 1) #define VIRIAN_GPIO_FUNCTION_2_DIS_MIC_SHIFT 0 #define VIRIAN_GPIO_FUNCTION_2_DIS_MIC_MASK (((1 << 1) - 1) << 0) #define VIRIAN_GPIO_FUNCTION_2_DIS_MIC_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_GPIO_FUNCTION_2_DIS_MIC_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_2_REGISTER)) >> 0) typedef union __virian_gpio_function_2 { struct _virian_gpio_function_2 { volatile const unsigned int reserved1 : 26; /*--- Bits 6 ... 31 Reserved ---*/ volatile const unsigned int I2SD_ON_12 : 1; /*--- Bit 5 Enables I2S_SD output signal on GPIO_12 ---*/ volatile const unsigned int EN_I2WS_ON_0 : 1; /*--- Bit 4 Enables I2S_WS on GPIO_0 ---*/ volatile const unsigned int EN_I2SCK_ON_1 : 1; /*--- Bit 3 Enables I2S_CK Out on GPIO_1 ---*/ volatile const unsigned int reserved2 : 1; /*--- Bit 2 Reserved ---*/ volatile const unsigned int I2S_ON_LED : 1; /*--- Bit 1 Brings out I2S-related signals on the pins GPIO_14, GPIO_15 and GPIO_16 ---*/ volatile const unsigned int DIS_MIC : 1; /*--- Bit 0 Disables MIC ---*/ } Bits; volatile unsigned int Register; } virian_gpio_function_2_t; /*------------------------------------------------------------------------------------------*\ DDR EMR2 Value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_EMR2_REGISTER (DDR_REGISTER_OFFSET + 0x00000090) #define VIRIAN_DDR_EMR2_VALUE_SHIFT 0 #define VIRIAN_DDR_EMR2_VALUE_MASK (((1 << 13) - 1) << 0) #define VIRIAN_DDR_EMR2_VALUE_SET_VALUE(value) ((((1 << 13) - 1) & (value)) << 0) #define VIRIAN_DDR_EMR2_VALUE_GET_VALUE ((((1 << 13) - 1) & *((volatile unsigned int *)VIRIAN_DDR_EMR2_REGISTER)) >> 0) typedef union __virian_ddr_emr2 { struct _virian_ddr_emr2 { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved ---*/ volatile unsigned int VALUE : 13; /*--- Bits 0 ... 12 Extended mode register 2 value ---*/ } Bits; volatile unsigned int Register; } virian_ddr_emr2_t; /*------------------------------------------------------------------------------------------*\ Mailbox 0 Tx DMA Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX0_DMA_TX_CONTROL_REGISTER (MBOX_REGISTER_OFFSET + 0x0000001C) #define VIRIAN_MBOX0_DMA_TX_CONTROL_RESUME_SHIFT 2 #define VIRIAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK (((1 << 1) - 1) << 2) #define VIRIAN_MBOX0_DMA_TX_CONTROL_RESUME_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_MBOX0_DMA_TX_CONTROL_RESUME_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_TX_CONTROL_REGISTER)) >> 2) #define VIRIAN_MBOX0_DMA_TX_CONTROL_START_SHIFT 1 #define VIRIAN_MBOX0_DMA_TX_CONTROL_START_MASK (((1 << 1) - 1) << 1) #define VIRIAN_MBOX0_DMA_TX_CONTROL_START_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_MBOX0_DMA_TX_CONTROL_START_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_TX_CONTROL_REGISTER)) >> 1) #define VIRIAN_MBOX0_DMA_TX_CONTROL_STOP_SHIFT 0 #define VIRIAN_MBOX0_DMA_TX_CONTROL_STOP_MASK (((1 << 1) - 1) << 0) #define VIRIAN_MBOX0_DMA_TX_CONTROL_STOP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_MBOX0_DMA_TX_CONTROL_STOP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_TX_CONTROL_REGISTER)) >> 0) typedef union __virian_mbox0_dma_tx_control { struct _virian_mbox0_dma_tx_control { volatile unsigned int reserved1 : 29; /*--- Bits 3 ... 31 Reserved ---*/ volatile unsigned int RESUME : 1; /*--- Bit 2 Programming a 1 to this field causes a potentially stalled (due to having caught up with CPU-owned descriptiors) DMA engine to resume its transfer by refetching the last descriptor it had fetched and found to be CPU owned. Software can use RESUME operations to add descriptors to the end of the descriptor chain (only modifying CPU-owned descriptors) in a reace-free atomic manner. If the RESUME operation is programmed and the DMA enigne is not stalled, it has no effect and is automatically cleared. ---*/ volatile unsigned int START : 1; /*--- Bit 1 Programming a 1 to this field causes the DMA engine to start transferring data by fetching the descriptor pointed to by the 'Mailbox 0 _Tx DMA Descriptors Base Address (MBOX0_DMA_TX_DESCRIPTOR_BASE)' register. The START operation should usually be used only when the DMA enigne is known to be stopped (after poweron or SOC reset) or after an explicit STOP operation. ---*/ volatile unsigned int STOP : 1; /*--- Bit 0 Programming a 1 to this field causes the DMA engine to stop transferring any more data from this descriptor chain (after the current descriptor is completed, if a transfer is already in progress). ---*/ } Bits; volatile unsigned int Register; } virian_mbox0_dma_tx_control_t; /*------------------------------------------------------------------------------------------*\ MBOX Related Interrupt Status \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_INT_STATUS_REGISTER (MBOX_REGISTER_OFFSET + 0x00000038) #define VIRIAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SHIFT 10 #define VIRIAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK (((1 << 2) - 1) << 10) #define VIRIAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 10) #define VIRIAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 10) #define VIRIAN_MBOX_INT_STATUS_TX_DM_EOM_COMPLETE_SHIFT 8 #define VIRIAN_MBOX_INT_STATUS_TX_DM_EOM_COMPLETE_MASK (((1 << 2) - 1) << 8) #define VIRIAN_MBOX_INT_STATUS_TX_DM_EOM_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 8) #define VIRIAN_MBOX_INT_STATUS_TX_DM_EOM_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 8) #define VIRIAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SHIFT 6 #define VIRIAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK (((1 << 2) - 1) << 6) #define VIRIAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 6) #define VIRIAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 6) #define VIRIAN_MBOX_INT_STATUS_TX_OVERFLOW_SHIFT 5 #define VIRIAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK (((1 << 1) - 1) << 5) #define VIRIAN_MBOX_INT_STATUS_TX_OVERFLOW_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_MBOX_INT_STATUS_TX_OVERFLOW_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 5) #define VIRIAN_MBOX_INT_STATUS_RX_UNDERFLOW_SHIFT 4 #define VIRIAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK (((1 << 1) - 1) << 4) #define VIRIAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 4) #define VIRIAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SHIFT 2 #define VIRIAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK (((1 << 2) - 1) << 2) #define VIRIAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 2) #define VIRIAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 2) #define VIRIAN_MBOX_INT_STATUS_RX_NOT_FULL_SHIFT 0 #define VIRIAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK (((1 << 2) - 1) << 0) #define VIRIAN_MBOX_INT_STATUS_RX_NOT_FULL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_MBOX_INT_STATUS_RX_NOT_FULL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_STATUS_REGISTER)) >> 0) typedef union __virian_mbox_int_status { struct _virian_mbox_int_status { volatile unsigned int reserved1 : 20; /*--- Bits 12 ... 31 Reserved ---*/ volatile unsigned int RX_DMA_COMPLETE : 2; /*--- Bits 10 ... 11 Per-mailbox Rx DMA completion (one descriptor completed) interrupts ---*/ volatile unsigned int TX_DM_EOM_COMPLETE : 2; /*--- Bits 8 ... 9 Per-mailbox Tx DMA completion of EOM (descriptor with EOM flag completed) interrupts ---*/ volatile unsigned int TX_DMA_COMPLETE : 2; /*--- Bits 6 ... 7 Per-mailbox Tx DMA completion (one descriptor completed) interrupts ---*/ volatile unsigned int TX_OVERFLOW : 1; /*--- Bit 5 MBOX Tx overflow error; the overflow condition is the same as the host interface overflow error ---*/ volatile unsigned int RX_UNDERFLOW : 1; /*--- Bit 4 MBOX Rx underflow error; the underflow condition is the same as the host interface underflow error ---*/ volatile unsigned int TX_NOT_EMPTY : 2; /*--- Bits 2 ... 3 TX_NOT_EMPTY not pending interrupt for each of the Tx mailboxes; bit sets when the MBOX FIFO has no room (Bit[0] = MBOX 0 TX_NOT_EMPTY interrupt, Bit[1] = MBOX 1 TX_NOT_EMPTY interrupt) ---*/ volatile unsigned int RX_NOT_FULL : 2; /*--- Bits 0 ... 1 RX_NOT_EMPTY not pending interrupt for each of the Rx mailboxes; bit sets when the MBOX FIFO has no room (Bit[0] = MBOX 0 RX_NOT_EMPTY interrupt, Bit[1] = MBOX 1 RX_NOT_EMPTY interrupt) ---*/ } Bits; volatile unsigned int Register; } virian_mbox_int_status_t; /*------------------------------------------------------------------------------------------*\ Mailbox 0 Tx DMA Descriptors Base Address \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_REGISTER (MBOX_REGISTER_OFFSET + 0x00000018) #define VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SHIFT 2 #define VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK (((1 << 26) - 1) << 2) #define VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET_VALUE(value) ((((1 << 26) - 1) & (value)) << 2) #define VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET_VALUE ((((1 << 26) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_REGISTER)) >> 2) typedef union __virian_mbox0_dma_tx_descriptor_base { struct _virian_mbox0_dma_tx_descriptor_base { volatile unsigned int reserved1 : 4; /*--- Bits 28 ... 31 Reserved ---*/ volatile unsigned int ADDRESS : 26; /*--- Bits 2 ... 27 Most significant 26 bits of the 4-byte-aligned address of the first descriptor in the DMA ---*/ volatile unsigned int reserved2 : 2; /*--- Bits 0 ... 1 Reserved ---*/ } Bits; volatile unsigned int Register; } virian_mbox0_dma_tx_descriptor_base_t; /*------------------------------------------------------------------------------------------*\ SPI Read Data \*------------------------------------------------------------------------------------------*/ #define VIRIAN_SPI_READ_DATA_REGISTER (SPI_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_SPI_READ_DATA_READ_DATA_SHIFT 0 #define VIRIAN_SPI_READ_DATA_READ_DATA_MASK (((1 << 32) - 1) << 0) #define VIRIAN_SPI_READ_DATA_READ_DATA_SET_VALUE(value) ((((1 << 32) - 1) & (value)) << 0) #define VIRIAN_SPI_READ_DATA_READ_DATA_GET_VALUE ((((1 << 32) - 1) & *((volatile unsigned int *)VIRIAN_SPI_READ_DATA_REGISTER)) >> 0) typedef union __virian_spi_read_data { struct _virian_spi_read_data { volatile const unsigned int READ_DATA : 32; /*--- Bits 0 ... 31 The read data sampled in every clock ---*/ } Bits; volatile unsigned int Register; } virian_spi_read_data_t; /*------------------------------------------------------------------------------------------*\ MBOX Related Interrupt Enables \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_INT_ENABLE_REGISTER (MBOX_REGISTER_OFFSET + 0x0000003C) #define VIRIAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SHIFT 10 #define VIRIAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK (((1 << 2) - 1) << 10) #define VIRIAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 10) #define VIRIAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 10) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SHIFT 8 #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK (((1 << 2) - 1) << 8) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 8) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 8) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SHIFT 6 #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK (((1 << 2) - 1) << 6) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 6) #define VIRIAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 6) #define VIRIAN_MBOX_INT_ENABLE_TX_OVERFLOW_SHIFT 5 #define VIRIAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK (((1 << 1) - 1) << 5) #define VIRIAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 5) #define VIRIAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SHIFT 4 #define VIRIAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK (((1 << 1) - 1) << 4) #define VIRIAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 4) #define VIRIAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SHIFT 2 #define VIRIAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK (((1 << 2) - 1) << 2) #define VIRIAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 2) #define VIRIAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 2) #define VIRIAN_MBOX_INT_ENABLE_RX_NOT_FULL_SHIFT 0 #define VIRIAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK (((1 << 2) - 1) << 0) #define VIRIAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_INT_ENABLE_REGISTER)) >> 0) typedef union __virian_mbox_int_enable { struct _virian_mbox_int_enable { volatile unsigned int reserved1 : 20; /*--- Bits 12 ... 31 Reserved ---*/ volatile unsigned int RX_DMA_COMPLETE : 2; /*--- Bits 10 ... 11 Enable per mailbox Rx DMA completion interrupts ---*/ volatile unsigned int TX_DMA_EOM_COMPLETE : 2; /*--- Bits 8 ... 9 Enable per mailbox Tx DMA completion of end message interrupts ---*/ volatile unsigned int TX_DMA_COMPLETE : 2; /*--- Bits 6 ... 7 Enable per mailbox Tx DMA completion interrupts ---*/ volatile unsigned int TX_OVERFLOW : 1; /*--- Bit 5 Enable MBOX Tx overflow error ---*/ volatile unsigned int RX_UNDERFLOW : 1; /*--- Bit 4 Enable MBOX Rx overflow error ---*/ volatile unsigned int TX_NOT_EMPTY : 2; /*--- Bits 2 ... 3 Enable TX_NOT_EMPTY interrupts from MBOX Tx FIFOs (Bit[0] = Enable MBOX 0 TX_NOT_EMPTY interrupt, Bit[1] = Enable MBOX 1 TX_NOT_EMPTY interrupt) ---*/ volatile unsigned int RX_NOT_FULL : 2; /*--- Bits 0 ... 1 Enable RX_NOT_EMPTY interrupts from MBOX Rx FIFOs (Bit[0] = Enable MBOX 0 RX_NOT_EMPTY interrupt, Bit[1] = Enable MBOX 1 RX_NOT_EMPTY interrupt) ---*/ } Bits; volatile unsigned int Register; } virian_mbox_int_enable_t; /*------------------------------------------------------------------------------------------*\ Mailbox 0 Rx DMA Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX0_DMA_RX_CONTROL_REGISTER (MBOX_REGISTER_OFFSET + 0x00000014) #define VIRIAN_MBOX0_DMA_RX_CONTROL_RESUME_SHIFT 2 #define VIRIAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK (((1 << 1) - 1) << 2) #define VIRIAN_MBOX0_DMA_RX_CONTROL_RESUME_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_MBOX0_DMA_RX_CONTROL_RESUME_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_RX_CONTROL_REGISTER)) >> 2) #define VIRIAN_MBOX0_DMA_RX_CONTROL_START_SHIFT 1 #define VIRIAN_MBOX0_DMA_RX_CONTROL_START_MASK (((1 << 1) - 1) << 1) #define VIRIAN_MBOX0_DMA_RX_CONTROL_START_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_MBOX0_DMA_RX_CONTROL_START_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_RX_CONTROL_REGISTER)) >> 1) #define VIRIAN_MBOX0_DMA_RX_CONTROL_STOP_SHIFT 0 #define VIRIAN_MBOX0_DMA_RX_CONTROL_STOP_MASK (((1 << 1) - 1) << 0) #define VIRIAN_MBOX0_DMA_RX_CONTROL_STOP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_MBOX0_DMA_RX_CONTROL_STOP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX0_DMA_RX_CONTROL_REGISTER)) >> 0) typedef union __virian_mbox0_dma_rx_control { struct _virian_mbox0_dma_rx_control { volatile unsigned int reserved1 : 29; /*--- Bits 3 ... 31 Reserved ---*/ volatile unsigned int RESUME : 1; /*--- Bit 2 Programming a 1 to this field causes a potentially stalled (due to having caught up with CPU-owned descriptiors) DMA engine to resume its transfer by refetching the last descriptor it had fetched and found to be CPU owned. Software can use RESUME operations to add descriptors to the end of the descriptor chain (only modifying CPU-owned descriptors) in a reace-free atomic manner. If the RESUME operation is programmed and the DMA enigne is not stalled, it has no effect and is automatically cleared. ---*/ volatile unsigned int START : 1; /*--- Bit 1 Programming a 1 to this field causes the DMA engine to start transferring data by fetching the descriptor pointed to by the 'Mailbox 0 _Rx DMA Descriptors Base Address (MBOX0_DMA_RX_DESCRIPTOR_BASE)' register. The START operation should usually be used only when the DMA enigne is known to be stopped (after poweron or SOC reset) or after an explicit STOP operation. ---*/ volatile unsigned int STOP : 1; /*--- Bit 0 Programming a 1 to this field causes the DMA engine to stop transferring any more data from this descriptor chain (after the current descriptor is completed, if a transfer is already in progress). ---*/ } Bits; volatile unsigned int Register; } virian_mbox0_dma_rx_control_t; /*------------------------------------------------------------------------------------------*\ USB PHY Programmability \*------------------------------------------------------------------------------------------*/ #define VIRIAN_USB_PHY_PROGRAM_REGISTER (USB_REGISTER_OFFSET + 0x00000008) #define VIRIAN_USB_PHY_PROGRAM_PREEMDEPTH_SHIFT 23 #define VIRIAN_USB_PHY_PROGRAM_PREEMDEPTH_MASK (((1 << 1) - 1) << 23) #define VIRIAN_USB_PHY_PROGRAM_PREEMDEPTH_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 23) #define VIRIAN_USB_PHY_PROGRAM_PREEMDEPTH_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 23) #define VIRIAN_USB_PHY_PROGRAM_ENPRE_SHIFT 22 #define VIRIAN_USB_PHY_PROGRAM_ENPRE_MASK (((1 << 1) - 1) << 22) #define VIRIAN_USB_PHY_PROGRAM_ENPRE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 22) #define VIRIAN_USB_PHY_PROGRAM_ENPRE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 22) #define VIRIAN_USB_PHY_PROGRAM_FSRFTSEL_SHIFT 20 #define VIRIAN_USB_PHY_PROGRAM_FSRFTSEL_MASK (((1 << 2) - 1) << 20) #define VIRIAN_USB_PHY_PROGRAM_FSRFTSEL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 20) #define VIRIAN_USB_PHY_PROGRAM_FSRFTSEL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 20) #define VIRIAN_USB_PHY_PROGRAM_LSRFTSEL_SHIFT 18 #define VIRIAN_USB_PHY_PROGRAM_LSRFTSEL_MASK (((1 << 2) - 1) << 18) #define VIRIAN_USB_PHY_PROGRAM_LSRFTSEL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 18) #define VIRIAN_USB_PHY_PROGRAM_LSRFTSEL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 18) #define VIRIAN_USB_PHY_PROGRAM_ICPCTRL_SHIFT 16 #define VIRIAN_USB_PHY_PROGRAM_ICPCTRL_MASK (((1 << 2) - 1) << 16) #define VIRIAN_USB_PHY_PROGRAM_ICPCTRL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 16) #define VIRIAN_USB_PHY_PROGRAM_ICPCTRL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 16) #define VIRIAN_USB_PHY_PROGRAM_HSTEDVSEL_SHIFT 14 #define VIRIAN_USB_PHY_PROGRAM_HSTEDVSEL_MASK (((1 << 2) - 1) << 14) #define VIRIAN_USB_PHY_PROGRAM_HSTEDVSEL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 14) #define VIRIAN_USB_PHY_PROGRAM_HSTEDVSEL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 14) #define VIRIAN_USB_PHY_PROGRAM_FSTUNEVSEL_SHIFT 11 #define VIRIAN_USB_PHY_PROGRAM_FSTUNEVSEL_MASK (((1 << 3) - 1) << 11) #define VIRIAN_USB_PHY_PROGRAM_FSTUNEVSEL_SET_VALUE(value) ((((1 << 3) - 1) & (value)) << 11) #define VIRIAN_USB_PHY_PROGRAM_FSTUNEVSEL_GET_VALUE ((((1 << 3) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 11) #define VIRIAN_USB_PHY_PROGRAM_HSDEDVSEL_SHIFT 9 #define VIRIAN_USB_PHY_PROGRAM_HSDEDVSEL_MASK (((1 << 2) - 1) << 9) #define VIRIAN_USB_PHY_PROGRAM_HSDEDVSEL_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 9) #define VIRIAN_USB_PHY_PROGRAM_HSDEDVSEL_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 9) #define VIRIAN_USB_PHY_PROGRAM_HSDRVSLOPE_SHIFT 5 #define VIRIAN_USB_PHY_PROGRAM_HSDRVSLOPE_MASK (((1 << 4) - 1) << 5) #define VIRIAN_USB_PHY_PROGRAM_HSDRVSLOPE_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 5) #define VIRIAN_USB_PHY_PROGRAM_HSDRVSLOPE_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 5) #define VIRIAN_USB_PHY_PROGRAM_HSDRVAMPLITUDE_SHIFT 3 #define VIRIAN_USB_PHY_PROGRAM_HSDRVAMPLITUDE_MASK (((1 << 2) - 1) << 3) #define VIRIAN_USB_PHY_PROGRAM_HSDRVAMPLITUDE_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 3) #define VIRIAN_USB_PHY_PROGRAM_HSDRVAMPLITUDE_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 3) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGN_SHIFT 1 #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGN_MASK (((1 << 2) - 1) << 1) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGN_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 1) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGN_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 1) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGP_SHIFT 0 #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGP_MASK (((1 << 1) - 1) << 0) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_USB_PHY_PROGRAM_HSDRVTIMINGP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PHY_PROGRAM_REGISTER)) >> 0) typedef union __virian_usb_phy_program { struct _virian_usb_phy_program { volatile unsigned int reserved1 : 8; /*--- Bits 24 ... 31 Reserved ---*/ volatile unsigned int PREEMDEPTH : 1; /*--- Bit 23 HW driver pre-emphasis depth ---*/ volatile unsigned int ENPRE : 1; /*--- Bit 22 HW driver pre-emphasis enable ---*/ volatile unsigned int FSRFTSEL : 2; /*--- Bits 20 ... 21 FS driver rise/fall time control ---*/ volatile unsigned int LSRFTSEL : 2; /*--- Bits 18 ... 19 LS driver rise/fall time control ---*/ volatile unsigned int ICPCTRL : 2; /*--- Bits 16 ... 17 PLL charge pump current control ---*/ volatile unsigned int HSTEDVSEL : 2; /*--- Bits 14 ... 15 Reference voltage for high speed transmission envelope detector ---*/ volatile unsigned int FSTUNEVSEL : 3; /*--- Bits 11 ... 13 Reference voltage control for calibration circuit ---*/ volatile unsigned int HSDEDVSEL : 2; /*--- Bits 9 ... 10 Reference voltage for high speed disconnect envelope detector ---*/ volatile unsigned int HSDRVSLOPE : 4; /*--- Bits 5 ... 8 HW driver slope control ---*/ volatile unsigned int HSDRVAMPLITUDE : 2; /*--- Bits 3 ... 4 HS driver amplitude control ---*/ volatile unsigned int HSDRVTIMINGN : 2; /*--- Bits 1 ... 2 HS driver timing control for NMOS ---*/ volatile unsigned int HSDRVTIMINGP : 1; /*--- Bit 0 HS driver timing control for PMOS ---*/ } Bits; volatile unsigned int Register; } virian_usb_phy_program_t; /*------------------------------------------------------------------------------------------*\ Write Buffer Flush for GE0/GE1 Interface \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_WB_FLUSH_GE0_REGISTER (DDR_REGISTER_OFFSET + 124) #define VIRIAN_DDR_WB_FLUSH_GE1_REGISTER (DDR_REGISTER_OFFSET + 128) #define VIRIAN_DDR_WB_FLUSH_GE_FLUSH_SHIFT 0 #define VIRIAN_DDR_WB_FLUSH_GE_FLUSH_MASK (((1 << 1) - 1) << 0) #define VIRIAN_DDR_WB_FLUSH_GE_FLUSH_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_DDR_WB_FLUSH_GE_FLUSH_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_WB_FLUSH_GE_REGISTER)) >> 0) typedef union __virian_ddr_wb_flush_ge { struct _virian_ddr_wb_flush_ge { volatile unsigned int reserved1 : 31; /*--- Bits 1 ... 31 Reserved ---*/ volatile unsigned int FLUSH : 1; /*--- Bit 0 Set to 1 to flush; will reset to 0 when flush is complete ---*/ } Bits; volatile unsigned int Register; } virian_ddr_wb_flush_ge_t; /*------------------------------------------------------------------------------------------*\ DDR DRAM Configuration \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_CONFIG2_REGISTER (DDR_REGISTER_OFFSET + 0x00000004) #define VIRIAN_DDR_CONFIG2_HALF_WIDTH_LOW_SHIFT 31 #define VIRIAN_DDR_CONFIG2_HALF_WIDTH_LOW_MASK (((1 << 1) - 1) << 31) #define VIRIAN_DDR_CONFIG2_HALF_WIDTH_LOW_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 31) #define VIRIAN_DDR_CONFIG2_HALF_WIDTH_LOW_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 31) #define VIRIAN_DDR_CONFIG2_GATE_OPEN_LATENCY_SHIFT 26 #define VIRIAN_DDR_CONFIG2_GATE_OPEN_LATENCY_MASK (((1 << 4) - 1) << 26) #define VIRIAN_DDR_CONFIG2_GATE_OPEN_LATENCY_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 26) #define VIRIAN_DDR_CONFIG2_GATE_OPEN_LATENCY_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 26) #define VIRIAN_DDR_CONFIG2_TWTR_SHIFT 21 #define VIRIAN_DDR_CONFIG2_TWTR_MASK (((1 << 5) - 1) << 21) #define VIRIAN_DDR_CONFIG2_TWTR_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 21) #define VIRIAN_DDR_CONFIG2_TWTR_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 21) #define VIRIAN_DDR_CONFIG2_TRTP_SHIFT 17 #define VIRIAN_DDR_CONFIG2_TRTP_MASK (((1 << 4) - 1) << 17) #define VIRIAN_DDR_CONFIG2_TRTP_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 17) #define VIRIAN_DDR_CONFIG2_TRTP_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 17) #define VIRIAN_DDR_CONFIG2_TRTW_SHIFT 12 #define VIRIAN_DDR_CONFIG2_TRTW_MASK (((1 << 5) - 1) << 12) #define VIRIAN_DDR_CONFIG2_TRTW_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 12) #define VIRIAN_DDR_CONFIG2_TRTW_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 12) #define VIRIAN_DDR_CONFIG2_TWR_SHIFT 8 #define VIRIAN_DDR_CONFIG2_TWR_MASK (((1 << 4) - 1) << 8) #define VIRIAN_DDR_CONFIG2_TWR_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 8) #define VIRIAN_DDR_CONFIG2_TWR_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 8) #define VIRIAN_DDR_CONFIG2_CKE_SHIFT 7 #define VIRIAN_DDR_CONFIG2_CKE_MASK (((1 << 1) - 1) << 7) #define VIRIAN_DDR_CONFIG2_CKE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 7) #define VIRIAN_DDR_CONFIG2_CKE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 7) #define VIRIAN_DDR_CONFIG2_PHASE_SELECT_SHIFT 6 #define VIRIAN_DDR_CONFIG2_PHASE_SELECT_MASK (((1 << 1) - 1) << 6) #define VIRIAN_DDR_CONFIG2_PHASE_SELECT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_DDR_CONFIG2_PHASE_SELECT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 6) #define VIRIAN_DDR_CONFIG2_CNTL_OE_EN_SHIFT 5 #define VIRIAN_DDR_CONFIG2_CNTL_OE_EN_MASK (((1 << 1) - 1) << 5) #define VIRIAN_DDR_CONFIG2_CNTL_OE_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_DDR_CONFIG2_CNTL_OE_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 5) #define VIRIAN_DDR_CONFIG2_BURST_TYPE_SHIFT 4 #define VIRIAN_DDR_CONFIG2_BURST_TYPE_MASK (((1 << 1) - 1) << 4) #define VIRIAN_DDR_CONFIG2_BURST_TYPE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_DDR_CONFIG2_BURST_TYPE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 4) #define VIRIAN_DDR_CONFIG2_BURST_LENGTH_SHIFT 0 #define VIRIAN_DDR_CONFIG2_BURST_LENGTH_MASK (((1 << 4) - 1) << 0) #define VIRIAN_DDR_CONFIG2_BURST_LENGTH_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 0) #define VIRIAN_DDR_CONFIG2_BURST_LENGTH_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_DDR_CONFIG2_REGISTER)) >> 0) typedef union __virian_ddr_config2 { struct _virian_ddr_config2 { volatile unsigned int HALF_WIDTH_LOW : 1; /*--- Bit 31 Controls which part of the 32-bit DDR DQ bus is populated with DRAM in a 16-bit memory system (0 = 31:16, 1 = 15:0) ---*/ volatile unsigned int reserved1 : 1; /*--- Bit 30 Reserved ---*/ volatile unsigned int GATE_OPEN_LATENCY : 4; /*--- Bits 26 ... 29 Memory CAS LATENCY * 2 ---*/ volatile unsigned int TWTR : 5; /*--- Bits 21 ... 25 DRAM tWTR parameter rounded up in memory core clock cycles ---*/ volatile unsigned int TRTP : 4; /*--- Bits 17 ... 20 DRAM read to precharge parameter rounded up in memory core clock cycles; normal value is 2 control cycles ---*/ volatile unsigned int TRTW : 5; /*--- Bits 12 ... 16 DRAM tRTW parameter rounded up in memory core clock cycles; the value should be CAS LATENCY + BURST LENGTH + BUS TURNAROUND TIME ---*/ volatile unsigned int TWR : 4; /*--- Bits 8 ... 11 DRAM tWR parameter rounded up in memory core clock cycles ---*/ volatile unsigned int CKE : 1; /*--- Bit 7 DRAM CKE bit ---*/ volatile unsigned int PHASE_SELECT : 1; /*--- Bit 6 Select output phase ---*/ volatile unsigned int CNTL_OE_EN : 1; /*--- Bit 5 Control bit to allow the memory controller to tri-state the address / control outpus ---*/ volatile unsigned int BURST_TYPE : 1; /*--- Bit 4 DRAM burst type (0 = Sequentialm 1 = Interleaved) ---*/ volatile unsigned int BURST_LENGTH : 4; /*--- Bits 0 ... 3 DRAM burst length setting (2, 4, or 8; only 8 is supported) ---*/ } Bits; volatile unsigned int Register; } virian_ddr_config2_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Interrupt Pending \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_INT_PENDING_REGISTER (GPIO_REGISTER_OFFSET + 0x00000020) #define VIRIAN_GPIO_INT_PENDING_PENDING_SHIFT 0 #define VIRIAN_GPIO_INT_PENDING_PENDING_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_INT_PENDING_PENDING_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_INT_PENDING_PENDING_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_INT_PENDING_REGISTER)) >> 0) typedef union __virian_gpio_int_pending { struct _virian_gpio_int_pending { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int PENDING : 20; /*--- Bits 0 ... 19 For each bit, indicates that an interrupt is currently pending; for edge-sensitive interrupts, this register is read-with-clear ---*/ } Bits; volatile unsigned int Register; } virian_gpio_int_pending_t; /*------------------------------------------------------------------------------------------*\ DDR Mode Value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_MODE_REGISTER_REGISTER (DDR_REGISTER_OFFSET + 0x00000008) #define VIRIAN_DDR_MODE_REGISTER_VALUE_SHIFT 0 #define VIRIAN_DDR_MODE_REGISTER_VALUE_MASK (((1 << 13) - 1) << 0) #define VIRIAN_DDR_MODE_REGISTER_VALUE_SET_VALUE(value) ((((1 << 13) - 1) & (value)) << 0) #define VIRIAN_DDR_MODE_REGISTER_VALUE_GET_VALUE ((((1 << 13) - 1) & *((volatile unsigned int *)VIRIAN_DDR_MODE_REGISTER_REGISTER)) >> 0) typedef union __virian_ddr_mode_register { struct _virian_ddr_mode_register { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved ---*/ volatile unsigned int VALUE : 13; /*--- Bits 0 ... 12 Mode register value. Reset to CAS 3, BL=8, sequential, DLL reset off ---*/ } Bits; volatile unsigned int Register; } virian_ddr_mode_register_t; /*------------------------------------------------------------------------------------------*\ Chip Revision ID \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_REVISION_ID_REGISTER (RST_REGISTER_OFFSET + 0x00000090) #define VIRIAN_RST_REVISION_ID_MAJOR_SHIFT 4 #define VIRIAN_RST_REVISION_ID_MAJOR_MASK (((1 << 16) - 1) << 4) #define VIRIAN_RST_REVISION_ID_MAJOR_SET_VALUE(value) ((((1 << 16) - 1) & (value)) << 4) #define VIRIAN_RST_REVISION_ID_MAJOR_GET_VALUE ((((1 << 16) - 1) & *((volatile unsigned int *)VIRIAN_RST_REVISION_ID_REGISTER)) >> 4) #define VIRIAN_RST_REVISION_ID_MINOR_SHIFT 0 #define VIRIAN_RST_REVISION_ID_MINOR_MASK (((1 << 4) - 1) << 0) #define VIRIAN_RST_REVISION_ID_MINOR_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 0) #define VIRIAN_RST_REVISION_ID_MINOR_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_RST_REVISION_ID_REGISTER)) >> 0) typedef union __virian_rst_revision_id { struct _virian_rst_revision_id { volatile const unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile const unsigned int MAJOR : 16; /*--- Bits 4 ... 19 Major revision ID ---*/ volatile const unsigned int MINOR : 4; /*--- Bits 0 ... 3 Minor revision ID ---*/ } Bits; volatile unsigned int Register; } virian_rst_revision_id_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Interrupt Enable \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_INT_REGISTER (GPIO_REGISTER_OFFSET + 0x00000014) #define VIRIAN_GPIO_INT_INT_SHIFT 0 #define VIRIAN_GPIO_INT_INT_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_INT_INT_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_INT_INT_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_INT_REGISTER)) >> 0) typedef union __virian_gpio_int { struct _virian_gpio_int { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int INT : 20; /*--- Bits 0 ... 19 Each bit that is set is considered an interrupt ORd into the GPIO line ---*/ } Bits; volatile unsigned int Register; } virian_gpio_int_t; /*------------------------------------------------------------------------------------------*\ USB Power Control and Status \*------------------------------------------------------------------------------------------*/ #define VIRIAN_USB_PWRCTL_REGISTER (USB_REGISTER_OFFSET + 0x00000000) #define VIRIAN_USB_PWRCTL_WAKEUP_STATUS_SHIFT 6 #define VIRIAN_USB_PWRCTL_WAKEUP_STATUS_MASK (((1 << 1) - 1) << 6) #define VIRIAN_USB_PWRCTL_WAKEUP_STATUS_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_USB_PWRCTL_WAKEUP_STATUS_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 6) #define VIRIAN_USB_PWRCTL_USR_WAKEUP_SHIFT 5 #define VIRIAN_USB_PWRCTL_USR_WAKEUP_MASK (((1 << 1) - 1) << 5) #define VIRIAN_USB_PWRCTL_USR_WAKEUP_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 5) #define VIRIAN_USB_PWRCTL_USR_WAKEUP_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 5) #define VIRIAN_USB_PWRCTL_WAKE_OVRCURR_EN_SHIFT 4 #define VIRIAN_USB_PWRCTL_WAKE_OVRCURR_EN_MASK (((1 << 1) - 1) << 4) #define VIRIAN_USB_PWRCTL_WAKE_OVRCURR_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 4) #define VIRIAN_USB_PWRCTL_WAKE_OVRCURR_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 4) #define VIRIAN_USB_PWRCTL_WAKE_DSCNNT_EN_SHIFT 3 #define VIRIAN_USB_PWRCTL_WAKE_DSCNNT_EN_MASK (((1 << 1) - 1) << 3) #define VIRIAN_USB_PWRCTL_WAKE_DSCNNT_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_USB_PWRCTL_WAKE_DSCNNT_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 3) #define VIRIAN_USB_PWRCTL_WAKE_CNNT_EN_SHIFT 2 #define VIRIAN_USB_PWRCTL_WAKE_CNNT_EN_MASK (((1 << 1) - 1) << 2) #define VIRIAN_USB_PWRCTL_WAKE_CNNT_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_USB_PWRCTL_WAKE_CNNT_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 2) #define VIRIAN_USB_PWRCTL_SUSPEND_CLR_SHIFT 1 #define VIRIAN_USB_PWRCTL_SUSPEND_CLR_MASK (((1 << 1) - 1) << 1) #define VIRIAN_USB_PWRCTL_SUSPEND_CLR_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_USB_PWRCTL_SUSPEND_CLR_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 1) #define VIRIAN_USB_PWRCTL_SUSPEND_SHIFT 0 #define VIRIAN_USB_PWRCTL_SUSPEND_MASK (((1 << 1) - 1) << 0) #define VIRIAN_USB_PWRCTL_SUSPEND_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_USB_PWRCTL_SUSPEND_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_USB_PWRCTL_REGISTER)) >> 0) typedef union __virian_usb_pwrctl { struct _virian_usb_pwrctl { volatile unsigned int reserved1 : 25; /*--- Bits 7 ... 31 Reserved ---*/ volatile const unsigned int WAKEUP_STATUS : 1; /*--- Bit 6 Final wake-up status that wakes the USB core ---*/ volatile unsigned int USR_WAKEUP : 1; /*--- Bit 5 User wake-up signal; input clears suspend output, suspends outputs synchronize to a clock, and input does not propagate to suspend outputs until related clock begins running; must remain asserted until the related suspend output transitions to zero ---*/ volatile const unsigned int WAKE_OVRCURR_EN : 1; /*--- Bit 4 Wake-up status due to power fault ---*/ volatile const unsigned int WAKE_DSCNNT_EN : 1; /*--- Bit 3 Wake-up status due to a disconnect event ---*/ volatile const unsigned int WAKE_CNNT_EN : 1; /*--- Bit 2 Wake-up status due to connect event ---*/ volatile const unsigned int SUSPEND_CLR : 1; /*--- Bit 1 Output to notify software of a commanded wake-up. Not synchronized and remains set until the SUSPEND (bit[0]) clears ---*/ volatile const unsigned int SUSPEND : 1; /*--- Bit 0 Suspend output synchronized to the XCVR_CLK ---*/ } Bits; volatile unsigned int Register; } virian_usb_pwrctl_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Input enable \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_IN_REGISTER (GPIO_REGISTER_OFFSET + 0x00000004) #define VIRIAN_GPIO_IN_IN1_SHIFT 18 #define VIRIAN_GPIO_IN_IN1_MASK (((1 << 2) - 1) << 18) #define VIRIAN_GPIO_IN_IN1_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 18) #define VIRIAN_GPIO_IN_IN1_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_IN_REGISTER)) >> 18) #define VIRIAN_GPIO_IN_IN2_SHIFT 0 #define VIRIAN_GPIO_IN_IN2_MASK (((1 << 13) - 1) << 0) #define VIRIAN_GPIO_IN_IN2_SET_VALUE(value) ((((1 << 13) - 1) & (value)) << 0) #define VIRIAN_GPIO_IN_IN2_GET_VALUE ((((1 << 13) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_IN_REGISTER)) >> 0) typedef union __virian_gpio_in { struct _virian_gpio_in { volatile const unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile const unsigned int IN1 : 2; /*--- Bits 18 ... 19 Current values of each of the GPIO pins (along with bits [12:0]) ---*/ volatile const unsigned int reserved2 : 5; /*--- Bits 13 ... 17 Reserved; output only ---*/ volatile const unsigned int IN2 : 13; /*--- Bits 0 ... 12 Current values of each of the GPIO pins (along with bits [19:18]) ---*/ } Bits; volatile unsigned int Register; } virian_gpio_in_t; /*------------------------------------------------------------------------------------------*\ DDR Refresh Control and Configuration \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_REFRESH_REGISTER (DDR_REGISTER_OFFSET + 0x00000014) #define VIRIAN_DDR_REFRESH_ENABLE_SHIFT 14 #define VIRIAN_DDR_REFRESH_ENABLE_MASK (((1 << 1) - 1) << 14) #define VIRIAN_DDR_REFRESH_ENABLE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 14) #define VIRIAN_DDR_REFRESH_ENABLE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_REFRESH_REGISTER)) >> 14) #define VIRIAN_DDR_REFRESH_PERIOD_SHIFT 0 #define VIRIAN_DDR_REFRESH_PERIOD_MASK (((1 << 14) - 1) << 0) #define VIRIAN_DDR_REFRESH_PERIOD_SET_VALUE(value) ((((1 << 14) - 1) & (value)) << 0) #define VIRIAN_DDR_REFRESH_PERIOD_GET_VALUE ((((1 << 14) - 1) & *((volatile unsigned int *)VIRIAN_DDR_REFRESH_REGISTER)) >> 0) typedef union __virian_ddr_refresh { struct _virian_ddr_refresh { volatile unsigned int reserved1 : 17; /*--- Bits 15 ... 31 Reserved ---*/ volatile unsigned int ENABLE : 1; /*--- Bit 14 Refresh enable ---*/ volatile unsigned int PERIOD : 14; /*--- Bits 0 ... 13 Refresh period ---*/ } Bits; volatile unsigned int Register; } virian_ddr_refresh_t; /*------------------------------------------------------------------------------------------*\ General Purpose Timer Reload \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_GENERAL_TIMER_RELOAD0_REGISTER (RST_REGISTER_OFFSET + 4) #define VIRIAN_RST_GENERAL_TIMER_RELOAD1_REGISTER (RST_REGISTER_OFFSET + 0x00000098) #define VIRIAN_RST_GENERAL_TIMER_RELOAD2_REGISTER (RST_REGISTER_OFFSET + 0x000000A0) #define VIRIAN_RST_GENERAL_TIMER_RELOAD3_REGISTER (RST_REGISTER_OFFSET + 168) #define VIRIAN_RST_GENERAL_TIMER_RELOAD_RELOAD_VALUE_SHIFT 0 #define VIRIAN_RST_GENERAL_TIMER_RELOAD_RELOAD_VALUE_MASK (((1 << 32) - 1) << 0) #define VIRIAN_RST_GENERAL_TIMER_RELOAD_RELOAD_VALUE_SET_VALUE(value) ((((1 << 32) - 1) & (value)) << 0) #define VIRIAN_RST_GENERAL_TIMER_RELOAD_RELOAD_VALUE_GET_VALUE ((((1 << 32) - 1) & *((volatile unsigned int *)VIRIAN_RST_GENERAL_TIMER_RELOAD_REGISTER)) >> 0) typedef union __virian_rst_general_timer_reload { struct _virian_rst_general_timer_reload { volatile unsigned int RELOAD_VALUE : 32; /*--- Bits 0 ... 31 Timer reload value ---*/ } Bits; volatile unsigned int Register; } virian_rst_general_timer_reload_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Interrupt Polarity \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_INT_POLARITY_REGISTER (GPIO_REGISTER_OFFSET + 0x0000001C) #define VIRIAN_GPIO_INT_POLARITY_POLARITY_SHIFT 0 #define VIRIAN_GPIO_INT_POLARITY_POLARITY_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_INT_POLARITY_POLARITY_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_INT_POLARITY_POLARITY_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_INT_POLARITY_REGISTER)) >> 0) typedef union __virian_gpio_int_polarity { struct _virian_gpio_int_polarity { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int POLARITY : 20; /*--- Bits 0 ... 19 0 = Indicates that the interrupt is active low (level) or falling edge (edge), 1 = Indicates that the interrupt is active high (level) or rising edge (edge) ---*/ } Bits; volatile unsigned int Register; } virian_gpio_int_polarity_t; /*------------------------------------------------------------------------------------------*\ GPIO Function \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_FUNCTION_1_REGISTER (GPIO_REGISTER_OFFSET + 0x00000028) #define VIRIAN_GPIO_FUNCTION_1_SPDIF2TCK_SHIFT 31 #define VIRIAN_GPIO_FUNCTION_1_SPDIF2TCK_MASK (((1 << 1) - 1) << 31) #define VIRIAN_GPIO_FUNCTION_1_SPDIF2TCK_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 31) #define VIRIAN_GPIO_FUNCTION_1_SPDIF2TCK_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 31) #define VIRIAN_GPIO_FUNCTION_1_SPDIF_EN_SHIFT 30 #define VIRIAN_GPIO_FUNCTION_1_SPDIF_EN_MASK (((1 << 1) - 1) << 30) #define VIRIAN_GPIO_FUNCTION_1_SPDIF_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 30) #define VIRIAN_GPIO_FUNCTION_1_SPDIF_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 30) #define VIRIAN_GPIO_FUNCTION_1_I2S_MCKEN_SHIFT 27 #define VIRIAN_GPIO_FUNCTION_1_I2S_MCKEN_MASK (((1 << 1) - 1) << 27) #define VIRIAN_GPIO_FUNCTION_1_I2S_MCKEN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 27) #define VIRIAN_GPIO_FUNCTION_1_I2S_MCKEN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 27) #define VIRIAN_GPIO_FUNCTION_1_I2S0_EN_SHIFT 26 #define VIRIAN_GPIO_FUNCTION_1_I2S0_EN_MASK (((1 << 1) - 1) << 26) #define VIRIAN_GPIO_FUNCTION_1_I2S0_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 26) #define VIRIAN_GPIO_FUNCTION_1_I2S0_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 26) #define VIRIAN_GPIO_FUNCTION_1_LED_DUPL_SHIFT 25 #define VIRIAN_GPIO_FUNCTION_1_LED_DUPL_MASK (((1 << 1) - 1) << 25) #define VIRIAN_GPIO_FUNCTION_1_LED_DUPL_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 25) #define VIRIAN_GPIO_FUNCTION_1_LED_DUPL_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 25) #define VIRIAN_GPIO_FUNCTION_1_LED_COLL_SHIFT 24 #define VIRIAN_GPIO_FUNCTION_1_LED_COLL_MASK (((1 << 1) - 1) << 24) #define VIRIAN_GPIO_FUNCTION_1_LED_COLL_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 24) #define VIRIAN_GPIO_FUNCTION_1_LED_COLL_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 24) #define VIRIAN_GPIO_FUNCTION_1_LED_ACTV_SHIFT 23 #define VIRIAN_GPIO_FUNCTION_1_LED_ACTV_MASK (((1 << 1) - 1) << 23) #define VIRIAN_GPIO_FUNCTION_1_LED_ACTV_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 23) #define VIRIAN_GPIO_FUNCTION_1_LED_ACTV_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 23) #define VIRIAN_GPIO_FUNCTION_1_SPI_EN_SHIFT 18 #define VIRIAN_GPIO_FUNCTION_1_SPI_EN_MASK (((1 << 1) - 1) << 18) #define VIRIAN_GPIO_FUNCTION_1_SPI_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 18) #define VIRIAN_GPIO_FUNCTION_1_SPI_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 18) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN2_SHIFT 14 #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN2_MASK (((1 << 1) - 1) << 14) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN2_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 14) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN2_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 14) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN1_SHIFT 13 #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN1_MASK (((1 << 1) - 1) << 13) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN1_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 13) #define VIRIAN_GPIO_FUNCTION_1_SPI_CS_EN1_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 13) #define VIRIAN_GPIO_FUNCTION_1_LED0_EN_SHIFT 3 #define VIRIAN_GPIO_FUNCTION_1_LED0_EN_MASK (((1 << 1) - 1) << 3) #define VIRIAN_GPIO_FUNCTION_1_LED0_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_GPIO_FUNCTION_1_LED0_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 3) #define VIRIAN_GPIO_FUNCTION_1_UART_RTS_CTS_EN_SHIFT 2 #define VIRIAN_GPIO_FUNCTION_1_UART_RTS_CTS_EN_MASK (((1 << 1) - 1) << 2) #define VIRIAN_GPIO_FUNCTION_1_UART_RTS_CTS_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_GPIO_FUNCTION_1_UART_RTS_CTS_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 2) #define VIRIAN_GPIO_FUNCTION_1_UART_EN_SHIFT 1 #define VIRIAN_GPIO_FUNCTION_1_UART_EN_MASK (((1 << 1) - 1) << 1) #define VIRIAN_GPIO_FUNCTION_1_UART_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_GPIO_FUNCTION_1_UART_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 1) #define VIRIAN_GPIO_FUNCTION_1_JTAG_DISABLE_SHIFT 0 #define VIRIAN_GPIO_FUNCTION_1_JTAG_DISABLE_MASK (((1 << 1) - 1) << 0) #define VIRIAN_GPIO_FUNCTION_1_JTAG_DISABLE_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_GPIO_FUNCTION_1_JTAG_DISABLE_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_FUNCTION_1_REGISTER)) >> 0) typedef union __virian_gpio_function_1 { struct _virian_gpio_function_1 { volatile unsigned int SPDIF2TCK : 1; /*--- Bit 31 Enable SPDIF_OUT on the pin TCK ---*/ volatile unsigned int SPDIF_EN : 1; /*--- Bit 30 Enable GPIO_13 or TCL as the SPDIF serial output ---*/ volatile unsigned int reserved1 : 2; /*--- Bits 28 ... 29 Reserved; must be set to zero ---*/ volatile unsigned int I2S_MCKEN : 1; /*--- Bit 27 Enable master audio CLK_MCK to be output through GPIO_11; works only if I2S0_EN (bit[26]) is also set ---*/ volatile unsigned int I2S0_EN : 1; /*--- Bit 26 Enable bits [12:11] and bits [8:6] as I2S interface pins: (Bit[6] = BITCLK (Input/Output), Bit[7] = WS (Input/Output), Bit[8] = SD (Output), Bit[11] = MCK (Intput/Output), Bit[12] = MICIN (Input)) ---*/ volatile unsigned int LED_DUPL : 1; /*--- Bit 25 LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_DUPLEXN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out ---*/ volatile unsigned int LED_COLL : 1; /*--- Bit 24 LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_COLN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out ---*/ volatile unsigned int LED_ACTV : 1; /*--- Bit 23 LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_ACTN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out ---*/ volatile unsigned int reserved2 : 4; /*--- Bits 19 ... 22 Reserved ---*/ volatile unsigned int SPI_EN : 1; /*--- Bit 18 Enables SPI Interface signals in GPIO_2, GPIO_3, GPIO_4 and GPIO_5 ---*/ volatile unsigned int reserved3 : 2; /*--- Bits 16 ... 17 Reserved ---*/ volatile unsigned int reserved4 : 1; /*--- Bit 15 Reserved; set to 1 ---*/ volatile unsigned int SPI_CS_EN2 : 1; /*--- Bit 14 Enables additional SPI chip select on GPIO_1 ---*/ volatile unsigned int SPI_CS_EN1 : 1; /*--- Bit 13 Enables additional SPI chip select on GPIO_0 ---*/ volatile unsigned int reserved5 : 5; /*--- Bits 8 ... 12 Reserved ---*/ volatile unsigned int reserved6 : 4; /*--- Bits 4 ... 7 Reserved; set to 0 ---*/ volatile unsigned int LED0_EN : 1; /*--- Bit 3 Enables Ethernet MAC/PHY LED data on GPIO_13 ---*/ volatile unsigned int UART_RTS_CTS_EN : 1; /*--- Bit 2 Enable UART RTS/CTS IO on GPIO_11 (RTS) and GPIO_12 (CTS) ---*/ volatile unsigned int UART_EN : 1; /*--- Bit 1 Enable UART IO on GPIO_9 (SIN) and GPIO_10 (SOUT) ---*/ volatile unsigned int JTAG_DISABLE : 1; /*--- Bit 0 Disable JTAG port functionality to enable GPIO functionality; can be set to 1 to enable using GPIO_5, GPIO_6 and GPIO_7 as GPIO pins ---*/ } Bits; volatile unsigned int Register; } virian_gpio_function_1_t; /*------------------------------------------------------------------------------------------*\ Mailbox DMA Engine Policy Control \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_DMA_POLICY_REGISTER (MBOX_REGISTER_OFFSET + 0x0000000C) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH1_SHIFT 8 #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH1_MASK (((1 << 4) - 1) << 8) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH1_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 8) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH1_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 8) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH0_SHIFT 4 #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH0_MASK (((1 << 4) - 1) << 4) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH0_SET_VALUE(value) ((((1 << 4) - 1) & (value)) << 4) #define VIRIAN_MBOX_DMA_POLICY_TX_FIFO_THRESH0_GET_VALUE ((((1 << 4) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 4) #define VIRIAN_MBOX_DMA_POLICY_TX_QUANTUM_SHIFT 3 #define VIRIAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK (((1 << 1) - 1) << 3) #define VIRIAN_MBOX_DMA_POLICY_TX_QUANTUM_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 3) #define VIRIAN_MBOX_DMA_POLICY_TX_QUANTUM_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 3) #define VIRIAN_MBOX_DMA_POLICY_TX_ORDER_SHIFT 2 #define VIRIAN_MBOX_DMA_POLICY_TX_ORDER_MASK (((1 << 1) - 1) << 2) #define VIRIAN_MBOX_DMA_POLICY_TX_ORDER_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 2) #define VIRIAN_MBOX_DMA_POLICY_TX_ORDER_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 2) #define VIRIAN_MBOX_DMA_POLICY_RX_QUANTUM_SHIFT 1 #define VIRIAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK (((1 << 1) - 1) << 1) #define VIRIAN_MBOX_DMA_POLICY_RX_QUANTUM_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 1) #define VIRIAN_MBOX_DMA_POLICY_RX_QUANTUM_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 1) #define VIRIAN_MBOX_DMA_POLICY_RX_ORDER_SHIFT 0 #define VIRIAN_MBOX_DMA_POLICY_RX_ORDER_MASK (((1 << 1) - 1) << 0) #define VIRIAN_MBOX_DMA_POLICY_RX_ORDER_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_MBOX_DMA_POLICY_RX_ORDER_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_DMA_POLICY_REGISTER)) >> 0) typedef union __virian_mbox_dma_policy { struct _virian_mbox_dma_policy { volatile unsigned int reserved1 : 20; /*--- Bits 12 ... 31 Reserved ---*/ volatile unsigned int TX_FIFO_THRESH1 : 4; /*--- Bits 8 ... 11 Threshold for MBOX TX FIFO1 in units of word (a value of 0 maps to 0 bytes, a value of 1 maps to 4 bytes, etc.). Only if this threshold is reached, the MBOX DMA engine will take Tx Chain1 into consideration while making queue service choices ---*/ volatile unsigned int TX_FIFO_THRESH0 : 4; /*--- Bits 4 ... 7 Threshold for MBOX TX FIFO0 in units of word (a value of 0 maps to 0 bytes, a value of 1 maps to 4 bytes, etc.). Only if this threshold is reached, the MBOX DMA engine will take Tx Chain0 into consideration while making queue service choices ---*/ volatile unsigned int TX_QUANTUM : 1; /*--- Bit 3 0 = Programming this field to 0 forces the Tx mailbox DMA engine to make queue service choices only at the end of messages (i.e., upon completing descriptors with the EOM bit set), 1 = Programming this field to 1 allows it to make choices upon the completion of every descriptor ---*/ volatile unsigned int TX_ORDER : 1; /*--- Bit 2 0 = Programming this field to 0 chooses roundrobin and programming, 1 = Programming this field to 1 chooses strict priotity (queue 0 is the highest priority) service ordering of mailbox Tx queues ---*/ volatile unsigned int RX_QUANTUM : 1; /*--- Bit 1 0 = Programming this field to 0 forces the Rx mailbox DMA engine to make queue service choices only at the end of messages (i.e., upon completing descriptors with the EOM bit set), 1 = Programming this field to 1 allows it to make choices upon the completion of every descriptor ---*/ volatile unsigned int RX_ORDER : 1; /*--- Bit 0 0 = Programming this field to 0 chooses roundrobin and programming, 1 = Programming this field to 1 chooses strict priotity (queue 0 is the highest priority) service ordering of mailbox Rx queues ---*/ } Bits; volatile unsigned int Register; } virian_mbox_dma_policy_t; /*------------------------------------------------------------------------------------------*\ Write Buffer Flush for PCIE Interface \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_WB_FLUSH_PCIE_REGISTER (DDR_REGISTER_OFFSET + 0x00000088) #define VIRIAN_DDR_WB_FLUSH_PCIE_FLUSH_SHIFT 0 #define VIRIAN_DDR_WB_FLUSH_PCIE_FLUSH_MASK (((1 << 1) - 1) << 0) #define VIRIAN_DDR_WB_FLUSH_PCIE_FLUSH_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_DDR_WB_FLUSH_PCIE_FLUSH_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_DDR_WB_FLUSH_PCIE_REGISTER)) >> 0) typedef union __virian_ddr_wb_flush_pcie { struct _virian_ddr_wb_flush_pcie { volatile unsigned int reserved1 : 31; /*--- Bits 1 ... 31 Reserved ---*/ volatile unsigned int FLUSH : 1; /*--- Bit 0 Set to 1 to flush; will reset to 0 when flush is complete ---*/ } Bits; volatile unsigned int Register; } virian_ddr_wb_flush_pcie_t; /*------------------------------------------------------------------------------------------*\ DDR EMR3 Value \*------------------------------------------------------------------------------------------*/ #define VIRIAN_DDR_EMR3_REGISTER (DDR_REGISTER_OFFSET + 0x00000094) #define VIRIAN_DDR_EMR3_VALUE_SHIFT 0 #define VIRIAN_DDR_EMR3_VALUE_MASK (((1 << 13) - 1) << 0) #define VIRIAN_DDR_EMR3_VALUE_SET_VALUE(value) ((((1 << 13) - 1) & (value)) << 0) #define VIRIAN_DDR_EMR3_VALUE_GET_VALUE ((((1 << 13) - 1) & *((volatile unsigned int *)VIRIAN_DDR_EMR3_REGISTER)) >> 0) typedef union __virian_ddr_emr3 { struct _virian_ddr_emr3 { volatile unsigned int reserved1 : 19; /*--- Bits 13 ... 31 Reserved ---*/ volatile unsigned int VALUE : 13; /*--- Bits 0 ... 12 Extended mode register 3 value ---*/ } Bits; volatile unsigned int Register; } virian_ddr_emr3_t; /*------------------------------------------------------------------------------------------*\ General Purpose Timer \*------------------------------------------------------------------------------------------*/ #define VIRIAN_RST_GENERAL_TIMER0_REGISTER (RST_REGISTER_OFFSET + 0) #define VIRIAN_RST_GENERAL_TIMER1_REGISTER (RST_REGISTER_OFFSET + 0x00000094) #define VIRIAN_RST_GENERAL_TIMER2_REGISTER (RST_REGISTER_OFFSET + 0x0000009C) #define VIRIAN_RST_GENERAL_TIMER3_REGISTER (RST_REGISTER_OFFSET + 164) #define VIRIAN_RST_GENERAL_TIMER_TIMER_SHIFT 0 #define VIRIAN_RST_GENERAL_TIMER_TIMER_MASK (((1 << 32) - 1) << 0) #define VIRIAN_RST_GENERAL_TIMER_TIMER_SET_VALUE(value) ((((1 << 32) - 1) & (value)) << 0) #define VIRIAN_RST_GENERAL_TIMER_TIMER_GET_VALUE ((((1 << 32) - 1) & *((volatile unsigned int *)VIRIAN_RST_GENERAL_TIMER_REGISTER)) >> 0) typedef union __virian_rst_general_timer { struct _virian_rst_general_timer { volatile unsigned int TIMER : 32; /*--- Bits 0 ... 31 Timer value ---*/ } Bits; volatile unsigned int Register; } virian_rst_general_timer_t; /*------------------------------------------------------------------------------------------*\ General Purpose I/O Per Bit Clear \*------------------------------------------------------------------------------------------*/ #define VIRIAN_GPIO_CLEAR_REGISTER (GPIO_REGISTER_OFFSET + 0x00000010) #define VIRIAN_GPIO_CLEAR_CLEAR_SHIFT 0 #define VIRIAN_GPIO_CLEAR_CLEAR_MASK (((1 << 20) - 1) << 0) #define VIRIAN_GPIO_CLEAR_CLEAR_SET_VALUE(value) ((((1 << 20) - 1) & (value)) << 0) #define VIRIAN_GPIO_CLEAR_CLEAR_GET_VALUE ((((1 << 20) - 1) & *((volatile unsigned int *)VIRIAN_GPIO_CLEAR_REGISTER)) >> 0) typedef union __virian_gpio_clear { struct _virian_gpio_clear { volatile unsigned int reserved1 : 12; /*--- Bits 20 ... 31 Reserved ---*/ volatile unsigned int CLEAR : 20; /*--- Bits 0 ... 19 One a write, any bit that is set causes the corresponding GPIO bit to be cleared; any bit that is not set will have no effect. Bits [19:18] must be set to 0x3 initially to cause these output values to be 0. ---*/ } Bits; volatile unsigned int Register; } virian_gpio_clear_t; /*------------------------------------------------------------------------------------------*\ SPI Function Select \*------------------------------------------------------------------------------------------*/ #define VIRIAN_SPI_FUNC_SELECT_REGISTER (SPI_REGISTER_OFFSET + 0x00000000) #define VIRIAN_SPI_FUNC_SELECT_FUNCTION_SELECT_SHIFT 0 #define VIRIAN_SPI_FUNC_SELECT_FUNCTION_SELECT_MASK (((1 << 1) - 1) << 0) #define VIRIAN_SPI_FUNC_SELECT_FUNCTION_SELECT_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 0) #define VIRIAN_SPI_FUNC_SELECT_FUNCTION_SELECT_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_SPI_FUNC_SELECT_REGISTER)) >> 0) typedef union __virian_spi_func_select { struct _virian_spi_func_select { volatile unsigned int reserved1 : 31; /*--- Bits 1 ... 31 Reserved. Must be written with zero. Contains zeros when read. ---*/ volatile unsigned int FUNCTION_SELECT : 1; /*--- Bit 0 Setting this bit to 0 enables SPI. Setting this bit to 1 makes the rest of the registers visible ---*/ } Bits; volatile unsigned int Register; } virian_spi_func_select_t; /*------------------------------------------------------------------------------------------*\ Mailbox FIFO status \*------------------------------------------------------------------------------------------*/ #define VIRIAN_MBOX_FRAME_REGISTER (MBOX_REGISTER_OFFSET + 0x00000030) #define VIRIAN_MBOX_FRAME_RX_EOM_SHIFT 2 #define VIRIAN_MBOX_FRAME_RX_EOM_MASK (((1 << 2) - 1) << 2) #define VIRIAN_MBOX_FRAME_RX_EOM_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 2) #define VIRIAN_MBOX_FRAME_RX_EOM_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FRAME_REGISTER)) >> 2) #define VIRIAN_MBOX_FRAME_RX_SOM_SHIFT 0 #define VIRIAN_MBOX_FRAME_RX_SOM_MASK (((1 << 2) - 1) << 0) #define VIRIAN_MBOX_FRAME_RX_SOM_SET_VALUE(value) ((((1 << 2) - 1) & (value)) << 0) #define VIRIAN_MBOX_FRAME_RX_SOM_GET_VALUE ((((1 << 2) - 1) & *((volatile unsigned int *)VIRIAN_MBOX_FRAME_REGISTER)) >> 0) typedef union __virian_mbox_frame { struct _virian_mbox_frame { volatile const unsigned int reserved1 : 28; /*--- Bits 4 ... 31 Reserved ---*/ volatile const unsigned int RX_EOM : 2; /*--- Bits 2 ... 3 Rx FIFO contains a data byte with the EOM marker set in the corresponding mailbox. ---*/ volatile const unsigned int RX_SOM : 2; /*--- Bits 0 ... 1 Rx FIFO contains a data byte with the SOM marker set in the corresponding mailbox, a SOM byte always follows an EOM byte from the previou message ---*/ } Bits; volatile unsigned int Register; } virian_mbox_frame_t; /*------------------------------------------------------------------------------------------*\ DQS Delay Tap Control for Byte 0/1 \*------------------------------------------------------------------------------------------*/ #define VIRIAN_TAP_CONTROL_0_REGISTER (DDR_REGISTER_OFFSET + 28) #define VIRIAN_TAP_CONTROL_1_REGISTER (DDR_REGISTER_OFFSET + 32) #define VIRIAN_TAP_CONTROL__BYPASS_EN_SHIFT 6 #define VIRIAN_TAP_CONTROL__BYPASS_EN_MASK (((1 << 1) - 1) << 6) #define VIRIAN_TAP_CONTROL__BYPASS_EN_SET_VALUE(value) ((((1 << 1) - 1) & (value)) << 6) #define VIRIAN_TAP_CONTROL__BYPASS_EN_GET_VALUE ((((1 << 1) - 1) & *((volatile unsigned int *)VIRIAN_TAP_CONTROL__REGISTER)) >> 6) #define VIRIAN_TAP_CONTROL__TAP_SHIFT 0 #define VIRIAN_TAP_CONTROL__TAP_MASK (((1 << 5) - 1) << 0) #define VIRIAN_TAP_CONTROL__TAP_SET_VALUE(value) ((((1 << 5) - 1) & (value)) << 0) #define VIRIAN_TAP_CONTROL__TAP_GET_VALUE ((((1 << 5) - 1) & *((volatile unsigned int *)VIRIAN_TAP_CONTROL__REGISTER)) >> 0) typedef union __virian_tap_control_ { struct _virian_tap_control_ { volatile unsigned int reserved1 : 25; /*--- Bits 7 ... 31 Reserved ---*/ volatile unsigned int BYPASS_EN : 1; /*--- Bit 6 Bypass enable. Short circuits the first four taps directly to the ouput; only used in the very slow corner for the absolute minimum delay ---*/ volatile unsigned int reserved2 : 1; /*--- Bit 5 Reserved ---*/ volatile unsigned int TAP : 5; /*--- Bits 0 ... 4 Tap setting for delay chain ---*/ } Bits; volatile unsigned int Register; } virian_tap_control__t; #endif /*--- #ifndef _ARCH_ASM_MACH_VIRIAN_AR7242_H_ ---*/