#! /usr/bin/perl -w

use strict;
use warnings;



my %registers;

my @offsets;

@offsets = (
    { "name" => "USB_REGISTER_OFFSET",         "start" => "0x00000000", "end" => "0x0000000C", "descriptions" => "USB Registers" },
    { "name" => "DDR_REGISTER_OFFSET",         "start" => "0x18000000", "end" => "0x18000098", "descriptions" => "" },
    { "name" => "UART_REGISTER_OFFSET",        "start" => "0x18020000", "end" => "0x18020018", "descriptions" => "" },
    { "name" => "GPIO_REGISTER_OFFSET",        "start" => "0x18040000", "end" => "0x18040030", "descriptions" => "" },
    { "name" => "PLL_CONTROL_REGISTER_OFFSET", "start" => "0x18050000", "end" => "0x1805003C", "descriptions" => "" },
    { "name" => "RESET_REGISTER_OFFSET",       "start" => "0x18060000", "end" => "0x18060044", "descriptions" => "" },
    { "name" => "GMAC_REGISTER_OFFSET",        "start" => "0x18070000", "end" => "0x18070000", "descriptions" => "" },
    { "name" => "MBOX_REGISTER_OFFSET",        "start" => "0x180A0000", "end" => "0x180A0040", "descriptions" => "" },
    { "name" => "I2S_REGISTER_OFFSET",         "start" => "0x180B0000", "end" => "0x180B0018", "descriptions" => "" },
    { "name" => "PCIE_REGISTER_OFFSET",        "start" => "0x180F0000", "end" => "0x180F0050", "descriptions" => "" },
    { "name" => "ETH0_REGISTER_OFFSET",        "start" => "0x19000000", "end" => "0x190002BC", "descriptions" => "" },
    { "name" => "ETH1_REGISTER_OFFSET",        "start" => "0x1A000000", "end" => "0x1A0002BC", "descriptions" => "" },
    { "name" => "SPI_REGISTER_OFFSET",         "start" => "0x1F000000", "end" => "0x1F00000C", "descriptions" => "" },
    { "name" => "MAC_REGISTER_OFFSET",         "start" => "0x00000000", "end" => "0x000204A4", "descriptions" => "" },
    { "name" => "PCIE_CONFIG_REGISTER_OFFSET", "start" => "0x10000000", "end" => "0x1000003C", "descriptions" => "" },
);

sub print_offsets {
    my ( $handle, $prefix ) = @_;
    foreach my $off (@offsets) {
        print $handle "#define " . $prefix . ${off}->{name} . " ";
        print $handle ${off}->{start};
        print $handle "\n";
    }
}

$registers{"usb_pwrctl"} = {
    "name" => "USB_PWRCTL",
    "description" => "USB Power Control and Status",
    "offset" => "USB_REGISTER_OFFSET",
    "address" => ["0x00000000"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",       "attr" => "rw", "width" => "25", "shift" => "7", "description" => "Reserved" },
        { "name" => "WAKEUP_STATUS",   "attr" => "ro", "width" =>  "1", "shift" => "6", "description" => "Final wake-up status that wakes the USB core" },
        { "name" => "USR_WAKEUP",      "attr" => "rw", "width" =>  "1", "shift" => "5", "description" => "User wake-up signal; input clears suspend output, suspends outputs synchronize to a clock, and input does not propagate to suspend outputs until related clock begins running; must remain asserted until the related suspend output transitions to zero" },
        { "name" => "WAKE_OVRCURR_EN", "attr" => "ro", "width" =>  "1", "shift" => "4", "description" => "Wake-up status due to power fault" },
        { "name" => "WAKE_DSCNNT_EN",  "attr" => "ro", "width" =>  "1", "shift" => "3", "description" => "Wake-up status due to a disconnect event" },
        { "name" => "WAKE_CNNT_EN",    "attr" => "ro", "width" =>  "1", "shift" => "2", "description" => "Wake-up status due to connect event" },
        { "name" => "SUSPEND_CLR",     "attr" => "ro", "width" =>  "1", "shift" => "1", "description" => "Output to notify software of a commanded wake-up. Not synchronized and remains set until the SUSPEND (bit[0]) clears" },
        { "name" => "SUSPEND",         "attr" => "ro", "width" =>  "1", "shift" => "0", "description" => "Suspend output synchronized to the XCVR_CLK" }
    ]
};

$registers{"usb_config"} = {
    "name" => "USB_CONFIG",
    "description" => "USB Configuration",
    "offset" => "USB_REGISTER_OFFSET",
    "address" => ["0x00000004"],
    "reset" => "0x00000534",
    "bits" => [
        { "name" => "reserved1",       "attr" => "rw", "width" => "13", "shift" => "19", "description" => "Reserved" },
        { "name" => "CONF3",           "attr" => "rw", "width" =>  "1", "shift" => "18", "description" => "During non-driving (opmode < 1:0> = 01): If conf3 = 1, the 15 K pulldown resistors are connected (if dppulldown = dnpulldown = 1); should be tied to 0 for device-only applications" },
        { "name" => "CONF2",           "attr" => "rw", "width" =>  "1", "shift" => "17", "description" => "Active high; when asserted, turns on OTG comparators during suspend (SUSPEND = 0)" },
        { "name" => "EXTCAL",          "attr" => "rw", "width" =>  "5", "shift" => "12", "description" => "Externally controls calibration values; valid when CALBP = 1" },
        { "name" => "CALBP",           "attr" => "rw", "width" =>  "1", "shift" => "11", "description" => "Enables calibration bypass for both DP and DN lines" },
        { "name" => "CLK_SEL",         "attr" => "rw", "width" =>  "2", "shift" =>  "9", "description" => "select input clock frequency to USB PHY (0 = 12, 1 = 19.2, 2 = 24, 3 = Reserved)" },
        { "name" => "HOST_ONLY",       "attr" => "rw", "width" =>  "1", "shift" =>  "8", "description" => "If set to 1, the IDPULLUP input to UTMI PHY is tied to 0 to make sure the ID signal is not sampled by the PHY" },
        { "name" => "PHY_TEST_MODE",   "attr" => "rw", "width" =>  "1", "shift" =>  "7", "description" => "Bypass the USB core and connect all USB PHY I/Os to the USB PHY test bus" },
        { "name" => "CORE_TEST_MODE",  "attr" => "rw", "width" =>  "1", "shift" =>  "6", "description" => "Bypass the USB PHY and connect all USB core I/Os to the USB CORE test bus" },
        { "name" => "AHB_HRDATA_SWAP", "attr" => "rw", "width" =>  "1", "shift" =>  "5", "description" => "Swap the read data on AHB bus" },
        { "name" => "AHB_HWDATA_SWAP", "attr" => "rw", "width" =>  "1", "shift" =>  "4", "description" => "Swap the write data on AHB bus" },
        { "name" => "reserved2",       "attr" => "rw", "width" =>  "1", "shift" =>  "3", "description" => "Reserved" },
        { "name" => "HS_MODE_EN",      "attr" => "ro", "width" =>  "1", "shift" =>  "2", "description" => "Asserted when the HS interface is selected" },
        { "name" => "UTMI_PHY_EN",     "attr" => "ro", "width" =>  "1", "shift" =>  "1", "description" => "Asserted when the UTMI interface is selected" },
        { "name" => "ONCLOCK",         "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "Allows system clocks to clock out and the SIE clock to be available even if suspend is asserted" },
    ]
};

$registers{"usb_phy_program"} = {
    "name" => "USB_PHY_PROGRAM",
    "description" => "USB PHY Programmability",
    "offset" => "USB_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x0014A400",
    "bits" => [
        { "name" => "reserved1",      "attr" => "rw", "width" => "8", "shift" => "24", "description" => "Reserved" },
        { "name" => "PREEMDEPTH",     "attr" => "rw", "width" => "1", "shift" => "23", "description" => "HW driver pre-emphasis depth" },
        { "name" => "ENPRE",          "attr" => "rw", "width" => "1", "shift" => "22", "description" => "HW driver pre-emphasis enable" },
        { "name" => "FSRFTSEL",       "attr" => "rw", "width" => "2", "shift" => "20", "description" => "FS driver rise/fall time control" },
        { "name" => "LSRFTSEL",       "attr" => "rw", "width" => "2", "shift" => "18", "description" => "LS driver rise/fall time control" },
        { "name" => "ICPCTRL",        "attr" => "rw", "width" => "2", "shift" => "16", "description" => "PLL charge pump current control" },
        { "name" => "HSTEDVSEL",      "attr" => "rw", "width" => "2", "shift" => "14", "description" => "Reference voltage for high speed transmission envelope detector" },
        { "name" => "FSTUNEVSEL",     "attr" => "rw", "width" => "3", "shift" => "11", "description" => "Reference voltage control for calibration circuit" },
        { "name" => "HSDEDVSEL",      "attr" => "rw", "width" => "2", "shift" =>  "9", "description" => "Reference voltage for high speed disconnect envelope detector" },
        { "name" => "HSDRVSLOPE",     "attr" => "rw", "width" => "4", "shift" =>  "5", "description" => "HW driver slope control" },
        { "name" => "HSDRVAMPLITUDE", "attr" => "rw", "width" => "2", "shift" =>  "3", "description" => "HS driver amplitude control" },
        { "name" => "HSDRVTIMINGN",   "attr" => "rw", "width" => "2", "shift" =>  "1", "description" => "HS driver timing control for NMOS" },
        { "name" => "HSDRVTIMINGP",   "attr" => "rw", "width" => "1", "shift" =>  "0", "description" => "HS driver timing control for PMOS" },
    ]
};
 
$registers{"usb_phy_charger"} = {
    "name" => "USB_PHY_CHARGER",
    "description" => "USB PHY Charger Detection",
    "offset" => "USB_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "27", "shift" => "5", "description" => "Reserved" },
        { "name" => "CHGRDET",   "attr" => "rw", "width" =>  "1", "shift" => "4", "description" => "Charger detector output" },
        { "name" => "ONDCD",     "attr" => "rw", "width" =>  "1", "shift" => "3", "description" => "Enables data contact detect circuitry. Note: Cannot be asserted together with EN_CHGRDET" },
        { "name" => "CHGRMODE",  "attr" => "rw", "width" =>  "1", "shift" => "2", "description" => "Charger detector mode. Note: Maximum response time = 10ms (0 = Host charger detection, 1 = Device charger detection)" },
        { "name" => "CHGRDETEN", "attr" => "rw", "width" =>  "1", "shift" => "1", "description" => "Enable charger detector" },
        { "name" => "CHGRDETON", "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Charger detector power on control. Note: Must be asserted at least 10ms before EN_CHGRDET assertion" },
    ]
};

$registers{"ddr_config"} = {
    "name" => "DDR_CONFIG",
    "description" => "DDR DRAM Configuration",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000000"],
    "reset" => "0x77BC8CC2",
    "bits" => [
        { "name" => "CAS_LATENCY_MSB", "attr" => "rw", "width" => "1", "shift" => "31", "description" => "MSB bit of 4-bit CAS_LATENCY field" },
        { "name" => "OPEN_PAGE",       "attr" => "rw", "width" => "1", "shift" => "30", "description" => "Controller open page policy; open page policy increases bus efficiency if accesses are local to a page but increase random read/write latency (0 - Page open, 1 - Page closed)" },
        { "name" => "CAS_LATENCY",     "attr" => "rw", "width" => "3", "shift" => "27", "description" => "DRAM CAS latency parameter (first 3 bits) rounded up in memory core clock cycles; CAS_LATENCY is used by the hardware to estimate the internal DDR clock latency of a read; it should be grester than or equal to GATE_OPEN_LATENCY as specified in the DDR_CONFIG2 register. The value of this register should be memory cas_latency * 2 or cas_latency * 2 + 1 / 2 / 3." },
        { "name" => "TMRD",            "attr" => "rw", "width" => "4", "shift" => "23", "description" => "DRAM tMRD parameter rounded up in memory core clock cycles" },
        { "name" => "TRFC",            "attr" => "rw", "width" => "6", "shift" => "17", "description" => "DRAM tRFC parameter rounded up in memory core clock cycles" },
        { "name" => "TRRD",            "attr" => "rw", "width" => "4", "shift" => "13", "description" => "DRAM tRRD parameter rounded up in memory core clock cycles" },
        { "name" => "TRP",             "attr" => "rw", "width" => "4", "shift" =>  "9", "description" => "DRAM tRP parameter rounded up in memory core clock cycles" },
        { "name" => "TRCD",            "attr" => "rw", "width" => "4", "shift" =>  "5", "description" => "DRAM tRCD parameter rounded up in memory core clock cycles" },
        { "name" => "TRAS",            "attr" => "rw", "width" => "5", "shift" =>  "0", "description" => "DRAM tRAS parameter rounded up in memory core clock cycles" },
    ]
};

$registers{"ddr_config2"} = {
    "name" => "DDR_CONFIG2",
    "description" => "DDR DRAM Configuration",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000004"],
    "reset" => "0x99D10628",
    "bits" => [
        { "name" => "HALF_WIDTH_LOW",    "attr" => "rw", "width" => "1", "shift" => "31", "description" => "Controls which part of the 32-bit DDR DQ bus is populated with DRAM in a 16-bit memory system (0 = 31:16, 1 = 15:0)" },
        { "name" => "reserved1",         "attr" => "rw", "width" => "1", "shift" => "30", "description" => "Reserved" },
        { "name" => "GATE_OPEN_LATENCY", "attr" => "rw", "width" => "4", "shift" => "26", "description" => "Memory CAS LATENCY * 2" },
        { "name" => "TWTR",              "attr" => "rw", "width" => "5", "shift" => "21", "description" => "DRAM tWTR parameter rounded up in memory core clock cycles" },
        { "name" => "TRTP",              "attr" => "rw", "width" => "4", "shift" => "17", "description" => "DRAM read to precharge parameter rounded up in memory core clock cycles; normal value is 2 control cycles" },
        { "name" => "TRTW",              "attr" => "rw", "width" => "5", "shift" => "12", "description" => "DRAM tRTW parameter rounded up in memory core clock cycles; the value should be CAS LATENCY + BURST LENGTH + BUS TURNAROUND TIME" },
        { "name" => "TWR",               "attr" => "rw", "width" => "4", "shift" =>  "8", "description" => "DRAM tWR parameter rounded up in memory core clock cycles" },
        { "name" => "CKE",               "attr" => "rw", "width" => "1", "shift" =>  "7", "description" => "DRAM CKE bit" },
        { "name" => "PHASE_SELECT",      "attr" => "rw", "width" => "1", "shift" =>  "6", "description" => "Select output phase" },
        { "name" => "CNTL_OE_EN",        "attr" => "rw", "width" => "1", "shift" =>  "5", "description" => "Control bit to allow the memory controller to tri-state the address / control outpus" },
        { "name" => "BURST_TYPE",        "attr" => "rw", "width" => "1", "shift" =>  "4", "description" => "DRAM burst type (0 = Sequentialm 1 = Interleaved)" },
        { "name" => "BURST_LENGTH",      "attr" => "rw", "width" => "4", "shift" =>  "0", "description" => "DRAM burst length setting (2, 4, or 8; only 8 is supported)" },
    ]
};

$registers{"ddr_mode_register"} = {
    "name" => "DDR_MODE_REGISTER",
    "description" => "DDR Mode Value",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x00000133",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved" },
        { "name" => "VALUE",     "attr" => "rw", "width" => "13", "shift" =>  "0", "description" => "Mode register value. Reset to CAS 3, BL=8, sequential, DLL reset off" },
    ]
};

$registers{"ddr_extended_mode_register"} = {
    "name" => "DDR_EXTENDED_MODE_REGISTER",
    "description" => "DDR Extended Mode Value",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000002",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved" },
        { "name" => "VALUE",     "attr" => "rw", "width" => "13", "shift" =>  "0", "description" => "Extende4d mode register value. Reset to weak driver, DLL on" },
    ]
};

$registers{"ddr_control"} = {
    "name" => "DDR_CONTROL",
    "description" => "DDR Control",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000010"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "26", "shift" => "6", "description" => "Reserved" },
        { "name" => "EMR3",      "attr" => "rw", "width" =>  "1", "shift" => "5", "description" => "Force an EMR3S update cycle" },
        { "name" => "EMR2",      "attr" => "rw", "width" =>  "1", "shift" => "4", "description" => "Force an EMR2S update cycle" },
        { "name" => "PREA",      "attr" => "rw", "width" =>  "1", "shift" => "3", "description" => "Force a PRECHARGE ALL cycle" },
        { "name" => "REF",       "attr" => "rw", "width" =>  "1", "shift" => "2", "description" => "Force an AUTO REFRESH cycle" },
        { "name" => "EMRS",      "attr" => "rw", "width" =>  "1", "shift" => "1", "description" => "Force an EMRS update cycle" },
        { "name" => "MRS",       "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Force a MRS update cycle" },
    ]
};

$registers{"ddr_refresh"} = {
    "name" => "DDR_REFRESH",
    "description" => "DDR Refresh Control and Configuration",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000014"],
    "reset" => "0x00002000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "17", "shift" => "15", "description" => "Reserved" },
        { "name" => "ENABLE",    "attr" => "rw", "width" =>  "1", "shift" => "14", "description" => "Refresh enable" },
        { "name" => "PERIOD",    "attr" => "rw", "width" => "14", "shift" =>  "0", "description" => "Refresh period" },
    ]
};

$registers{"ddr_rd_data_this_cycle"} = {
    "name" => "DDR_RD_DATA_THIS_CYCLE",
    "description" => "DDR Read Data Capture Bit Mask",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000018"],
    "reset" => "0x0000FFFF",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" =>  "8", "shift" => "24", "description" => "Reserved" },
        { "name" => "VEC",       "attr" => "rw", "width" => "24", "shift" =>  "0", "description" => "Each bit represents a cycle of valid data" },
    ]
};

$registers{"tap_control_"} = {
    "name" => "TAP_CONTROL_",
    "description" => "DQS Delay Tap Control for Byte 0/1",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => [0x0000001C, 0x00000020],
    "reset" => "0x00000005",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "25", "shift" => "7", "description" => "Reserved" },
        { "name" => "BYPASS_EN", "attr" => "rw", "width" =>  "1", "shift" => "6", "description" => "Bypass enable. Short circuits the first four taps directly to the ouput; only used in the very slow corner for the absolute minimum delay" },
        { "name" => "reserved2", "attr" => "rw", "width" =>  "1", "shift" => "5", "description" => "Reserved" },
        { "name" => "TAP",       "attr" => "rw", "width" =>  "5", "shift" => "0", "description" => "Tap setting for delay chain" },
    ]
};

$registers{"ddr_wb_flush_ge"} = {
    "name" => "DDR_WB_FLUSH_GE",
    "description" => "Write Buffer Flush for GE0/GE1 Interface",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => [0x0000007C, 0x00000080],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "31", "shift" => "1", "description" => "Reserved" },
        { "name" => "FLUSH",     "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Set to 1 to flush; will reset to 0 when flush is complete" },
    ]
};

$registers{"ddr_wb_flush_usb"} = {
    "name" => "DDR_WB_FLUSH_USB",
    "description" => "Write Buffer Flush for USB Interface",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000084"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "31", "shift" => "1", "description" => "Reserved" },
        { "name" => "FLUSH",     "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Set to 1 to flush; will reset to 0 when flush is complete" },
    ]
};

$registers{"ddr_wb_flush_pcie"} = {
    "name" => "DDR_WB_FLUSH_PCIE",
    "description" => "Write Buffer Flush for PCIE Interface",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000088"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "31", "shift" => "1", "description" => "Reserved" },
        { "name" => "FLUSH",     "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Set to 1 to flush; will reset to 0 when flush is complete" },
    ]
};

$registers{"ddr_ddr2_config"} = {
    "name" => "DDR_DDR2_CONFIG",
    "description" => "DDR2 Configuration",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x0000008C"],
    "reset" => "0x00000858",
    "bits" => [
        { "name" => "reserved1",   "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved" },
        { "name" => "DDR2_TWL",    "attr" => "rw", "width" =>  "3", "shift" => "10", "description" => "Delay between WE_L/CAS_L assertion on DQS, DQ assertion for a DDR2 write transaction (in DDR_CLK cycles)" },
        { "name" => "reserved2",   "attr" => "rw", "width" =>  "2", "shift" =>  "8", "description" => "Reserved" },
        { "name" => "DDR2_TFAW",   "attr" => "rw", "width" =>  "6", "shift" =>  "2", "description" => "tFAW parameter in core DDR_CLK cycles" },
        { "name" => "reserved3",   "attr" => "rw", "width" =>  "1", "shift" =>  "1", "description" => "Reserved" },
        { "name" => "ENABLE_DDR2", "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "(0 = DDR1, 1 = DDR2)" },
    ]
};

$registers{"ddr_emr2"} = {
    "name" => "DDR_EMR2",
    "description" => "DDR EMR2 Value",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000090"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved" },
        { "name" => "VALUE",     "attr" => "rw", "width" => "13", "shift" =>  "0", "description" => "Extended mode register 2 value" },
    ]
};

$registers{"ddr_emr3"} = {
    "name" => "DDR_EMR3",
    "description" => "DDR EMR3 Value",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000094"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved" },
        { "name" => "VALUE",     "attr" => "rw", "width" => "13", "shift" =>  "0", "description" => "Extended mode register 3 value" },
    ]
};

$registers{"ddr_burst"} = {
    "name" => "DDR_BURST",
    "description" => "DDR Bank Arbiter Per Client Burst Size",
    "offset" => "DDR_REGISTER_OFFSET",
    "address" => ["0x00000098"],
    "reset" => "0x78822222",
    "bits" => [
        { "name" => "CPU_PRIORITY",    "attr" => "rw", "width" => "1", "shift" => "31", "description" => "Setting this bit causes bank arbiters to break the current burst and grant CPU" },
        { "name" => "CPU_PRIORITY_BE", "attr" => "rw", "width" => "1", "shift" => "30", "description" => "Setting it makes the bank arbiters to break only at current burst completion and grant CPU" },
        { "name" => "ENABLE_RWP_MASK", "attr" => "rw", "width" => "2", "shift" => "28", "description" => "Enable read/write mask, precharge mask" },
        { "name" => "MAX_WRITE_BURST", "attr" => "rw", "width" => "4", "shift" => "24", "description" => "Max write burst size until reads are masked in BANK_ARB" },
        { "name" => "MAX_READ_BURST",  "attr" => "rw", "width" => "4", "shift" => "20", "description" => "Max read burst size until writes are maeked in BANK_ARB" },
        { "name" => "CPU_MAX_BL",      "attr" => "rw", "width" => "4", "shift" => "16", "description" => "USB burst size" },
        { "name" => "USB_MAX_BL",      "attr" => "rw", "width" => "4", "shift" => "12", "description" => "USB burst size" },
        { "name" => "PCIE_MAX_BL",     "attr" => "rw", "width" => "4", "shift" =>  "8", "description" => "PCIE burst size" },
        { "name" => "GE1_MAX_BL",      "attr" => "rw", "width" => "4", "shift" =>  "4", "description" => "GE1 burst size" },
        { "name" => "GE0_MAX_BL",      "attr" => "rw", "width" => "4", "shift" =>  "0", "description" => "Ethernet burst size" },
    ]
};

$registers{"rst_general_timer"} = {
    "name" => "RST_GENERAL_TIMER",
    "description" => "General Purpose Timer",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => [0x00000000, "0x00000094", "0x0000009C", 0x000000A4],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "TIMER", "attr" => "rw", "width" => "32", "shift" =>  "0", "description" => "Timer value" },
    ]
};

$registers{"rst_general_timer_reload"} = {
    "name" => "RST_GENERAL_TIMER_RELOAD",
    "description" => "General Purpose Timer Reload",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => [0x00000004, "0x00000098", "0x000000A0", 0x000000A8],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "RELOAD_VALUE", "attr" => "rw", "width" => "32", "shift" =>  "0", "description" => "Timer reload value" },
    ]
};

$registers{"rst_watchdog_timer_control"} = {
    "name" => "RST_WATCHDOG_TIMER_CONTROL",
    "description" => "Watchdog Timer Control Register",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "LAST",      "attr" => "ro", "width" =>  "1", "shift" => "31", "description" => "Indicates if the last reset was due to a watchdog timeout" },
        { "name" => "reserved1", "attr" => "ro", "width" => "29", "shift" =>  "2", "description" => "Reserved. Must be written with zero. Contains zero when read." },
        { "name" => "ACTION",    "attr" => "rw", "width" =>  "2", "shift" =>  "0", "description" => "The action to be taken after timer reaches zero (00 = No action, 01 = General purpose interrupt, 10 Non-maskable interrupt, 11 = Full chip reset)" },
    ]
};

$registers{"rst_watchdog_timer"} = {
    "name" => "RST_watchdog_TIMER",
    "description" => "Watchdog Timer Register",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "TIMER", "attr" => "rw", "width" => "32", "shift" =>  "0", "description" => "Counts down to zero until the software sets this timer to another value. These bits should be set to a non-zero value before updating the 'Watchdog Timer Control Register (RST_WATCHDOG_TIMER_CONTROL)' register to a non-zero number." },
    ]
};

$registers{"rst_misc_interrupt_status"} = {
    "name" => "RST_MISC_INTERRUPT_STATUS",
    "description" => "Miscellaneous Interrupt Status",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x00000010"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",    "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "ETH_MAC_INT",  "attr" => "rw", "width" =>  "1", "shift" => "12", "description" => "The interrupt generated by the Ethernet MAC/PHY." },
        { "name" => "reserved2",    "attr" => "rw", "width" =>  "1", "shift" => "11", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "TIMER3_INT",   "attr" => "rw", "width" =>  "1", "shift" => "10", "description" => "The interrupt corresponding to General Purpose Timer3. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register." },
        { "name" => "TIMER2_INT",   "attr" => "rw", "width" =>  "1", "shift" =>  "9", "description" => "The interrupt corresponding to General Purpose Timer2. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register." },
        { "name" => "TIMER1_INT",   "attr" => "rw", "width" =>  "1", "shift" =>  "8", "description" => "The interrupt corresponding to General Purpose Timer1. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register." },
        { "name" => "reserved3",    "attr" => "rw", "width" =>  "2", "shift" =>  "6", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "PC_INT",       "attr" => "rw", "width" =>  "1", "shift" =>  "5", "description" => "CPU performance counter interrupt. Generated whenever either of the internal CPU performance counters have bit[31] set. The relevant performance counter must be reset to clear this interrupt." },
        { "name" => "WATCHDOG_INT", "attr" => "rw", "width" =>  "1", "shift" =>  "4", "description" => "The watchdog timer interrupt. this interrupt is generated when the watchdog timer reaches zero and the watchdog configuration register is configured to generate a general-purpose interrupt." },
        { "name" => "UART_INT",     "attr" => "rw", "width" =>  "1", "shift" =>  "3", "description" => "The UART interrupt. UART interrupt registers must be read before this interrupt can be cleared." },
        { "name" => "GPIO_INT",     "attr" => "rw", "width" =>  "1", "shift" =>  "2", "description" => "the GPIO interrupt. Individual lines ust be masked before this interrupt can be cleared." },
        { "name" => "reserved4",    "attr" => "rw", "width" =>  "1", "shift" =>  "1", "description" => "Reserved" },
        { "name" => "TIMER_INT",    "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "The interrupt corresponding to General Purpose Timer0. This bit is cleared after being read. The timer has been immediately reloaded from the 'General Purpose Timers Reload (RST_GENERAL_TIMER_RELOADx)' register." },
    ]
};

$registers{"rst_misc_interrupt_mask"} = {
    "name" => "RST_MISC_INTERRUPT_MASK",
    "description" => "Miscellaneous Interrupt Mask",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x00000014"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",        "attr" => "rw", "width" => "19", "shift" => "13", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "ETH_MAC_INT_MASK", "attr" => "rw", "width" =>  "1", "shift" => "12", "description" => "Enables the interrupt generated by the Ethernet MAC/PHY" },
        { "name" => "reserved2",        "attr" => "rw", "width" =>  "1", "shift" => "11", "description" => "Reserved" },
        { "name" => "TIMER3_MASK",      "attr" => "rw", "width" =>  "1", "shift" => "10", "description" => "When set, enables Timer 3 interrupt" },
        { "name" => "TIMER2_MASK",      "attr" => "rw", "width" =>  "1", "shift" =>  "9", "description" => "When set, enables Timer 2 interrupt" },
        { "name" => "TIMER1_MASK",      "attr" => "rw", "width" =>  "1", "shift" =>  "8", "description" => "When set, enables Timer 1 interrupt" },
        { "name" => "MBOX_MASK",        "attr" => "rw", "width" =>  "1", "shift" =>  "7", "description" => "When set, enables MBOX interrupt" },
        { "name" => "reserved3",        "attr" => "rw", "width" =>  "1", "shift" =>  "6", "description" => "Reserved" },
        { "name" => "PC_MASK",          "attr" => "rw", "width" =>  "1", "shift" =>  "5", "description" => "When set, enables CPU performance counter interrupt" },
        { "name" => "WATCHDOG_MASK",    "attr" => "rw", "width" =>  "1", "shift" =>  "4", "description" => "When set, enables UART interrupt" },
        { "name" => "UART_MASK",        "attr" => "rw", "width" =>  "1", "shift" =>  "3", "description" => "When set, enables GPIO interrupt" },
        { "name" => "GPIO_MASK",        "attr" => "rw", "width" =>  "1", "shift" =>  "2", "description" => "When set, " },
        { "name" => "reserved4",        "attr" => "rw", "width" =>  "1", "shift" =>  "1", "description" => "Reserved" },
        { "name" => "TIMER_MASK",       "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "When set, enables timer interrupt" },
    ]
};

$registers{"rst_global_interrupt_status"} = {
    "name" => "RST_GLOBAL_INTERRUPT_STATUS",
    "description" => "Global Interrupt Status",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x00000018"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "26", "shift" => "6", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "TIMER_INT", "attr" => "ro", "width" =>  "1", "shift" => "5", "description" => "Internal count/compare timer interrupt" },
        { "name" => "MISC_INT",  "attr" => "ro", "width" =>  "1", "shift" => "4", "description" => "Miscellaneous interrupt; source of the interrupt available on the 'Miscellaneous Interrupt Status (RST_MISC_INTERRUPT_STATUS)' register" },
        { "name" => "GE1_INT",   "attr" => "ro", "width" =>  "1", "shift" => "3", "description" => "Ethernet1 interrupt; information available in the Ethernet1 register space" },
        { "name" => "GE0_INT",   "attr" => "ro", "width" =>  "1", "shift" => "2", "description" => "Ethernet0 interrupt; information available in the Ethernet0 register space" },
        { "name" => "USB_INT",   "attr" => "ro", "width" =>  "1", "shift" => "1", "description" => "USB interrupt; information available in the USB register space" },
        { "name" => "PCIE_INT",  "attr" => "ro", "width" =>  "1", "shift" => "0", "description" => "PCIE interrupt" },
    ]
};

$registers{"rst_reset"} = {
    "name" => "RST_RESET",
    "description" => "Reset",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x0000001C"],
    "reset" => "0x000027E0",
    "bits" => [
        { "name" => "reserved1",             "attr" => "rw", "width" => "3", "shift" => "29", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "EXTERNAL_RESET",        "attr" => "rw", "width" => "1", "shift" => "28", "description" => "Commands an external reset (SYS_RST_L pin); inverted before being sent to the pin." },
        { "name" => "reserved2",             "attr" => "rw", "width" => "3", "shift" => "25", "description" => "Reserved" },
        { "name" => "FULL_CHIP_RESET",       "attr" => "rw", "width" => "1", "shift" => "24", "description" => "Used to command a full chip reset. this is the software equivalent of pulling the reset pin. The system will reboot with PLL disabled. Always zero when read." },
        { "name" => "reserved3",             "attr" => "rw", "width" => "2", "shift" => "22", "description" => "Reserved" },
        { "name" => "CPU_NMI",               "attr" => "rw", "width" => "1", "shift" => "21", "description" => "Used to send an NMI to the CPU. always zero when read." },
        { "name" => "CPU_COLD_RESET",        "attr" => "rw", "width" => "1", "shift" => "20", "description" => "Used to cold reset the CPU. Always zero when read." },
        { "name" => "reserved4",             "attr" => "rw", "width" => "3", "shift" => "17", "description" => "Reserved" },
        { "name" => "DDR_RESET",             "attr" => "rw", "width" => "1", "shift" => "16", "description" => "Used to reset the DDR controller" },
        { "name" => "reserved5",             "attr" => "rw", "width" => "2", "shift" => "14", "description" => "Reserved" },
        { "name" => "GE1_MAC_RESET",         "attr" => "rw", "width" => "1", "shift" => "13", "description" => "Used to reset the GE1 MAC" },
        { "name" => "reserved6",             "attr" => "rw", "width" => "2", "shift" => "11", "description" => "Reserved" },
        { "name" => "PCIE_PHY_SERIAL_RESET", "attr" => "rw", "width" => "1", "shift" => "10", "description" => "Resets the PCIE PHY Shift reset" },
        { "name" => "GE0_MAC_RESET",         "attr" => "rw", "width" => "1", "shift" =>  "9", "description" => "Resetes the GE0 MAC" },
        { "name" => "ETH_MACPHY_RESET",      "attr" => "rw", "width" => "1", "shift" =>  "8", "description" => "Resets the Ethernet MAC/PHY" },
        { "name" => "PCIE_PHY_RESET",        "attr" => "rw", "width" => "1", "shift" =>  "7", "description" => "Used to reset the PCIE host controller" },
        { "name" => "PCIE_RESET",            "attr" => "rw", "width" => "1", "shift" =>  "6", "description" => "Used to reset the PCIE host controller. This bit will reset the endpoint as well." },
        { "name" => "USB_HOST_RESET",        "attr" => "rw", "width" => "1", "shift" =>  "5", "description" => "Used to reset the USB controller" },
        { "name" => "reserved7",             "attr" => "rw", "width" => "1", "shift" =>  "4", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "reserved8",             "attr" => "rw", "width" => "4", "shift" =>  "0", "description" => "Reserved" },
    ]
};

$registers{"rst_revision_id"} = {
    "name" => "RST_REVISION_ID",
    "description" => "Chip Revision ID",
    "offset" => "RST_REGISTER_OFFSET",
    "address" => ["0x00000090"],
    "reset" => "0x00011000",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "MAJOR",     "attr" => "ro", "width" => "16", "shift" =>  "4", "description" => "Major revision ID" },
        { "name" => "MINOR",     "attr" => "ro", "width" =>  "4", "shift" =>  "0", "description" => "Minor revision ID" },
    ]
};

$registers{"gpio_oe"} = {
    "name" => "GPIO_OE",
    "description" => "General Purpose I/O Output enable",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000000"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Must to set to zero" },
        { "name" => "OE",        "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "Per bit output enable; bits[19:18] must be set to 0x3 by software; bits[17:13] cannot be set as inputs. (0 = this bit is used as input, 1 = enables the bit as output)" },
    ]
};

$registers{"gpio_in"} = {
    "name" => "GPIO_IN",
    "description" => "General Purpose I/O Input enable",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000004"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "IN1",       "attr" => "ro", "width" =>  "2", "shift" => "18", "description" => "Current values of each of the GPIO pins (along with bits [12:0])" },
        { "name" => "reserved2", "attr" => "ro", "width" =>  "5", "shift" => "13", "description" => "Reserved; output only" },
        { "name" => "IN2",       "attr" => "ro", "width" => "13", "shift" =>  "0", "description" => "Current values of each of the GPIO pins (along with bits [19:18])" },
    ]
};

$registers{"gpio_out"} = {
    "name" => "GPIO_OUT",
    "description" => "General Purpose I/O Output value",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "OUT",       "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "Driver output value. If the corresponding bit in the OE register is set to 1, the GPIO pin will drive the value in the corresponding bit of the register" },
    ]
};

$registers{"gpio_set"} = {
    "name" => "GPIO_SET",
    "description" => "General Purpose I/O Per Bit Set",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "SET",       "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "One a write, any bit that is set causes the corresponding GPIO bit to be set; any bit that is not set will have no effect" },
    ]
};

$registers{"gpio_clear"} = {
    "name" => "GPIO_CLEAR",
    "description" => "General Purpose I/O Per Bit Clear",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000010"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "CLEAR",     "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "One a write, any bit that is set causes the corresponding GPIO bit to be cleared; any bit that is not set will have no effect. Bits [19:18] must be set to 0x3 initially to cause these output values to be 0." },
    ]
};

$registers{"gpio_int"} = {
    "name" => "GPIO_INT",
    "description" => "General Purpose I/O Interrupt Enable",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000014"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "INT",       "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "Each bit that is set is considered an interrupt ORd into the GPIO line" },
    ]
};

$registers{"gpio_int_type"} = {
    "name" => "GPIO_INT_TYPE",
    "description" => "General Purpose I/O Interrupt Type",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000018"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "TYPE",      "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "0 = Indicates the bit is a level-sensitive interrupt, 1 = Indicates the bit is an edge-sensitive interrupt" },
    ]
};

$registers{"gpio_int_polarity"} = {
    "name" => "GPIO_INT_POLARITY",
    "description" => "General Purpose I/O Interrupt Polarity",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x0000001C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "POLARITY",  "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "0 = Indicates that the interrupt is active low (level) or falling edge (edge), 1 = Indicates that the interrupt is active high (level) or rising edge (edge)" },
    ]
};

$registers{"gpio_int_pending"} = {
    "name" => "GPIO_INT_PENDING",
    "description" => "General Purpose I/O Interrupt Pending",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000020"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "PENDING",   "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "For each bit, indicates that an interrupt is currently pending; for edge-sensitive interrupts, this register is read-with-clear" },
    ]
};

$registers{"gpio_int_mask"} = {
    "name" => "GPIO_INT_MASK",
    "description" => "General Purpose I/O Interrupt Mask",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000024"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "MASK",      "attr" => "rw", "width" => "20", "shift" =>  "0", "description" => "For each bit that is set, the corresponding interrupt in the register 'General Purpose I/O Interrupt Pending (GPIO_INT_PENDING)' is passed on to the central interrupt controller" },
    ]
};

$registers{"gpio_function_1"} = {
    "name" => "GPIO_FUNCTION_1",
    "description" => "GPIO Function",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000028"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "SPDIF2TCK",       "attr" => "rw", "width" => "1", "shift" => "31", "description" => "Enable SPDIF_OUT on the pin TCK" },
        { "name" => "SPDIF_EN",        "attr" => "rw", "width" => "1", "shift" => "30", "description" => "Enable GPIO_13 or TCL as the SPDIF serial output" },
        { "name" => "reserved1",       "attr" => "rw", "width" => "2", "shift" => "28", "description" => "Reserved; must be set to zero" },
        { "name" => "I2S_MCKEN",       "attr" => "rw", "width" => "1", "shift" => "27", "description" => "Enable master audio CLK_MCK to be output through GPIO_11; works only if I2S0_EN (bit[26]) is also set" },
        { "name" => "I2S0_EN",         "attr" => "rw", "width" => "1", "shift" => "26", "description" => "Enable bits [12:11] and bits [8:6] as I2S interface pins: (Bit[6] = BITCLK (Input/Output), Bit[7] = WS (Input/Output), Bit[8] = SD (Output), Bit[11] = MCK (Intput/Output), Bit[12] = MICIN (Input))" },
        { "name" => "LED_DUPL",        "attr" => "rw", "width" => "1", "shift" => "25", "description" => "LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_DUPLEXN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out" },
        { "name" => "LED_COLL",        "attr" => "rw", "width" => "1", "shift" => "24", "description" => "LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_COLN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out" },
        { "name" => "LED_ACTV",        "attr" => "rw", "width" => "1", "shift" => "23", "description" => "LED signal to select whether Link, Activity, or both must be indicated in the LED. Selects the LED_ACTN_O signal go out as LED signals; if inactive, LED_LINK100N_O and LED_LINK10N_O is the default signal going out" },
        { "name" => "reserved2",       "attr" => "rw", "width" => "4", "shift" => "19", "description" => "Reserved" },
        { "name" => "SPI_EN",          "attr" => "rw", "width" => "1", "shift" => "18", "description" => "Enables SPI Interface signals in GPIO_2, GPIO_3, GPIO_4 and GPIO_5" },
        { "name" => "reserved3",       "attr" => "rw", "width" => "2", "shift" => "16", "description" => "Reserved" },
        { "name" => "reserved4",       "attr" => "rw", "width" => "1", "shift" => "15", "description" => "Reserved; set to 1" },
        { "name" => "SPI_CS_EN2",      "attr" => "rw", "width" => "1", "shift" => "14", "description" => "Enables additional SPI chip select on GPIO_1" },
        { "name" => "SPI_CS_EN1",      "attr" => "rw", "width" => "1", "shift" => "13", "description" => "Enables additional SPI chip select on GPIO_0" },
        { "name" => "reserved5",       "attr" => "rw", "width" => "5", "shift" =>  "8", "description" => "Reserved" },
        { "name" => "reserved6",       "attr" => "rw", "width" => "4", "shift" =>  "4", "description" => "Reserved; set to 0" },
        { "name" => "LED0_EN",         "attr" => "rw", "width" => "1", "shift" =>  "3", "description" => "Enables Ethernet MAC/PHY LED data on GPIO_13" },
        { "name" => "UART_RTS_CTS_EN", "attr" => "rw", "width" => "1", "shift" =>  "2", "description" => "Enable UART RTS/CTS IO on GPIO_11 (RTS) and GPIO_12 (CTS)" },
        { "name" => "UART_EN",         "attr" => "rw", "width" => "1", "shift" =>  "1", "description" => "Enable UART IO on GPIO_9 (SIN) and GPIO_10 (SOUT)" },
        { "name" => "JTAG_DISABLE",    "attr" => "rw", "width" => "1", "shift" =>  "0", "description" => "Disable JTAG port functionality to enable GPIO functionality; can be set to 1 to enable using GPIO_5, GPIO_6 and GPIO_7 as GPIO pins" },
    ]
};

$registers{"eth_led"} = {
    "name" => "ETH_LED",
    "description" => "General Purpose I/O Input Value",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x0000002C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "12", "shift" => "20", "description" => "Reserved" },
        { "name" => "LINK",      "attr" => "ro", "width" =>  "5", "shift" => "15", "description" => "Current value of LED_LINK100N_O and LED_LINK10N_O" },
        { "name" => "DUPL",      "attr" => "ro", "width" =>  "5", "shift" => "10", "description" => "Current value of LED_DUPLEXN_O" },
        { "name" => "COLL",      "attr" => "ro", "width" =>  "5", "shift" =>  "5", "description" => "Current value of LED_COLN_O" },
        { "name" => "ACTV",      "attr" => "ro", "width" =>  "5", "shift" =>  "0", "description" => "Current value of LED_ACTN_O" },
    ]
};

$registers{"gpio_function_2"} = {
    "name" => "GPIO_FUNCTION_2",
    "description" => "Extended GPIO Function Control",
    "offset" => "GPIO_REGISTER_OFFSET",
    "address" => ["0x00000030"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",     "attr" => "ro", "width" => "26", "shift" => "6", "description" => "Reserved" },
        { "name" => "I2SD_ON_12",    "attr" => "ro", "width" =>  "1", "shift" => "5", "description" => "Enables I2S_SD output signal on GPIO_12" },
        { "name" => "EN_I2WS_ON_0",  "attr" => "ro", "width" =>  "1", "shift" => "4", "description" => "Enables I2S_WS on GPIO_0" },
        { "name" => "EN_I2SCK_ON_1", "attr" => "ro", "width" =>  "1", "shift" => "3", "description" => "Enables I2S_CK Out on GPIO_1" },
        { "name" => "reserved2",     "attr" => "ro", "width" =>  "1", "shift" => "2", "description" => "Reserved" },
        { "name" => "I2S_ON_LED",    "attr" => "ro", "width" =>  "1", "shift" => "1", "description" => "Brings out I2S-related signals on the pins GPIO_14, GPIO_15 and GPIO_16" },
        { "name" => "DIS_MIC",       "attr" => "ro", "width" =>  "1", "shift" => "0", "description" => "Disables MIC" },
    ]
};

$registers{"mbox_fifo_status"} = {
    "name" => "MBOX_FIFO_STATUS",
    "description" => "Non-Destructive FIFO Status Query",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x0000000F",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "28", "shift" => "4", "description" => "Reserved" },
        { "name" => "EMPTY",     "attr" => "ro", "width" =>  "2", "shift" => "2", "description" => "On a read: returns an empty status for the Tx mailbox (Bit[3] = MBOX 1 Tx FIFO is empty (I2S1), Bit[2] = MBOX 0 Tx FIFO is empty (I2S0))" },
        { "name" => "FULL",      "attr" => "ro", "width" =>  "2", "shift" => "0", "description" => "On a read: returns an empty status for the Rx mailbox (Bit[3] = MBOX 1 Rx FIFO is empty (I2S1), Bit[2] = MBOX 0 Rx FIFO is empty (I2S0))" },
    ]
};

$registers{"mbox_dma_policy"} = {
    "name" => "MBOX_DMA_POLICY",
    "description" => "Mailbox DMA Engine Policy Control",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000440",
    "bits" => [
        { "name" => "reserved1",       "attr" => "rw", "width" => "20", "shift" => "12", "description" => "Reserved" },
        { "name" => "TX_FIFO_THRESH1", "attr" => "rw", "width" =>  "4", "shift" =>  "8", "description" => "Threshold for MBOX TX FIFO1 in units of word (a value of 0 maps to 0 bytes, a value of 1 maps to 4 bytes, etc.). Only if this threshold is reached, the MBOX DMA engine will take Tx Chain1 into consideration while making queue service choices" },
        { "name" => "TX_FIFO_THRESH0", "attr" => "rw", "width" =>  "4", "shift" =>  "4", "description" => "Threshold for MBOX TX FIFO0 in units of word (a value of 0 maps to 0 bytes, a value of 1 maps to 4 bytes, etc.). Only if this threshold is reached, the MBOX DMA engine will take Tx Chain0 into consideration while making queue service choices" },
        { "name" => "TX_QUANTUM",      "attr" => "rw", "width" =>  "1", "shift" =>  "3", "description" => "0 = Programming this field to 0 forces the Tx mailbox DMA engine to make queue service choices only at the end of messages (i.e., upon completing descriptors with the EOM bit set), 1 = Programming this field to 1 allows it to make choices upon the completion of every descriptor" },
        { "name" => "TX_ORDER",        "attr" => "rw", "width" =>  "1", "shift" =>  "2", "description" => "0 = Programming this field to 0 chooses roundrobin and programming, 1 = Programming this field to 1 chooses strict priotity (queue 0 is the highest priority) service ordering of mailbox Tx queues" },
        { "name" => "RX_QUANTUM",      "attr" => "rw", "width" =>  "1", "shift" =>  "1", "description" => "0 = Programming this field to 0 forces the Rx mailbox DMA engine to make queue service choices only at the end of messages (i.e., upon completing descriptors with the EOM bit set), 1 = Programming this field to 1 allows it to make choices upon the completion of every descriptor" },
        { "name" => "RX_ORDER",        "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "0 = Programming this field to 0 chooses roundrobin and programming, 1 = Programming this field to 1 chooses strict priotity (queue 0 is the highest priority) service ordering of mailbox Rx queues" },
    ]
};

$registers{"mbox0_dma_rx_descriptor_base"} = {
    "name" => "MBOX0_DMA_RX_DESCRIPTOR_BASE",
    "description" => "Mailbox 0 Rx DMA Descriptors Base Address",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000010"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" =>  "4", "shift" => "28", "description" => "Reserved" },
        { "name" => "ADDRESS",   "attr" => "rw", "width" => "26", "shift" =>  "2", "description" => "Most significant 26 bits of the 4-byte-aligned address of the first descriptor in the DMA" },
        { "name" => "reserved2", "attr" => "rw", "width" =>  "2", "shift" =>  "0", "description" => "Reserved" },
    ]
};

$registers{"mbox0_dma_rx_control"} = {
    "name" => "MBOX0_DMA_RX_CONTROL",
    "description" => "Mailbox 0 Rx DMA Control",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000014"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "29", "shift" => "3", "description" => "Reserved" },
        { "name" => "RESUME",    "attr" => "rw", "width" =>  "1", "shift" => "2", "description" => "Programming a 1 to this field causes a potentially stalled (due to having caught up with CPU-owned descriptiors) DMA engine to resume its transfer by refetching the last descriptor it had fetched and found to be CPU owned. Software can use RESUME operations to add descriptors to the end of the descriptor chain (only modifying CPU-owned descriptors) in a reace-free atomic manner. If the RESUME operation is programmed and the DMA enigne is not stalled, it has no effect and is automatically cleared." },
        { "name" => "START",     "attr" => "rw", "width" =>  "1", "shift" => "1", "description" => "Programming a 1 to this field causes the DMA engine to start transferring data by fetching the descriptor pointed to by the 'Mailbox 0 _Rx DMA Descriptors Base Address (MBOX0_DMA_RX_DESCRIPTOR_BASE)' register. The START operation should usually be used only when the DMA enigne is known to be stopped (after poweron or SOC reset) or after an explicit STOP operation." },
        { "name" => "STOP",      "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Programming a 1 to this field causes the DMA engine to stop transferring any more data from this descriptor chain (after the current descriptor is completed, if a transfer is already in progress)." },
    ]
};

$registers{"mbox0_dma_tx_descriptor_base"} = {
    "name" => "MBOX0_DMA_TX_DESCRIPTOR_BASE",
    "description" => "Mailbox 0 Tx DMA Descriptors Base Address",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000018"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" =>  "4", "shift" => "28", "description" => "Reserved" },
        { "name" => "ADDRESS",   "attr" => "rw", "width" => "26", "shift" =>  "2", "description" => "Most significant 26 bits of the 4-byte-aligned address of the first descriptor in the DMA" },
        { "name" => "reserved2", "attr" => "rw", "width" =>  "2", "shift" =>  "0", "description" => "Reserved" },
    ]
};

$registers{"mbox0_dma_tx_control"} = {
    "name" => "MBOX0_DMA_TX_CONTROL",
    "description" => "Mailbox 0 Tx DMA Control",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x0000001C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "29", "shift" => "3", "description" => "Reserved" },
        { "name" => "RESUME",    "attr" => "rw", "width" =>  "1", "shift" => "2", "description" => "Programming a 1 to this field causes a potentially stalled (due to having caught up with CPU-owned descriptiors) DMA engine to resume its transfer by refetching the last descriptor it had fetched and found to be CPU owned. Software can use RESUME operations to add descriptors to the end of the descriptor chain (only modifying CPU-owned descriptors) in a reace-free atomic manner. If the RESUME operation is programmed and the DMA enigne is not stalled, it has no effect and is automatically cleared." },
        { "name" => "START",     "attr" => "rw", "width" =>  "1", "shift" => "1", "description" => "Programming a 1 to this field causes the DMA engine to start transferring data by fetching the descriptor pointed to by the 'Mailbox 0 _Tx DMA Descriptors Base Address (MBOX0_DMA_TX_DESCRIPTOR_BASE)' register. The START operation should usually be used only when the DMA enigne is known to be stopped (after poweron or SOC reset) or after an explicit STOP operation." },
        { "name" => "STOP",      "attr" => "rw", "width" =>  "1", "shift" => "0", "description" => "Programming a 1 to this field causes the DMA engine to stop transferring any more data from this descriptor chain (after the current descriptor is completed, if a transfer is already in progress)." },
    ]
};

$registers{"mbox_frame"} = {
    "name" => "MBOX_FRAME",
    "description" => "Mailbox FIFO status",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000030"],
    "reset" => "0x00000003",
    "bits" => [
        { "name" => "reserved1", "attr" => "ro", "width" => "28", "shift" => "4", "description" => "Reserved" },
        { "name" => "RX_EOM",    "attr" => "ro", "width" =>  "2", "shift" => "2", "description" => "Rx FIFO contains a data byte with the EOM marker set in the corresponding mailbox." },
        { "name" => "RX_SOM",    "attr" => "ro", "width" =>  "2", "shift" => "0", "description" => "Rx FIFO contains a data byte with the SOM marker set in the corresponding mailbox, a SOM byte always follows an EOM byte from the previou message" },
    ]
};

$registers{"fifo_timeout"} = {
    "name" => "FIFO_TIMEOUT",
    "description" => "FIFO Timeout Period",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000034"],
    "reset" => "0x000001FF",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "23", "shift" => "9", "description" => "Reserved" },
        { "name" => "ENABLE",    "attr" => "rw", "width" =>  "1", "shift" => "8", "description" => "0 = FIFO timeouts are disabled, 1 = FIFO timeouts are enabled" },
        { "name" => "VALUE",     "attr" => "rw", "width" =>  "8", "shift" => "0", "description" => "Timeout value (in ms) when CORE_CLK = 40 MHz, or in 0.5 ms when CORE_CLK = 80 MHz; should never be set to 0" },
    ]
};

$registers{"mbox_int_status"} = {
    "name" => "MBOX_INT_STATUS",
    "description" => "MBOX Related Interrupt Status",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000038"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",          "attr" => "rw", "width" => "20", "shift" => "12", "description" => "Reserved" },
        { "name" => "RX_DMA_COMPLETE",    "attr" => "rw", "width" =>  "2", "shift" => "10", "description" => "Per-mailbox Rx DMA completion (one descriptor completed) interrupts" },
        { "name" => "TX_DM_EOM_COMPLETE", "attr" => "rw", "width" =>  "2", "shift" =>  "8", "description" => "Per-mailbox Tx DMA completion of EOM (descriptor with EOM flag completed) interrupts" },
        { "name" => "TX_DMA_COMPLETE",    "attr" => "rw", "width" =>  "2", "shift" =>  "6", "description" => "Per-mailbox Tx DMA completion (one descriptor completed) interrupts" },
        { "name" => "TX_OVERFLOW",        "attr" => "rw", "width" =>  "1", "shift" =>  "5", "description" => "MBOX Tx overflow error; the overflow condition is the same as the host interface overflow error" },
        { "name" => "RX_UNDERFLOW",       "attr" => "rw", "width" =>  "1", "shift" =>  "4", "description" => "MBOX Rx underflow error; the underflow condition is the same as the host interface underflow error" },
        { "name" => "TX_NOT_EMPTY",       "attr" => "rw", "width" =>  "2", "shift" =>  "2", "description" => "TX_NOT_EMPTY not pending interrupt for each of the Tx mailboxes; bit sets when the MBOX FIFO has no room (Bit[0] = MBOX 0 TX_NOT_EMPTY interrupt, Bit[1] = MBOX 1 TX_NOT_EMPTY interrupt)" },
        { "name" => "RX_NOT_FULL",        "attr" => "rw", "width" =>  "2", "shift" =>  "0", "description" => "RX_NOT_EMPTY not pending interrupt for each of the Rx mailboxes; bit sets when the MBOX FIFO has no room (Bit[0] = MBOX 0 RX_NOT_EMPTY interrupt, Bit[1] = MBOX 1 RX_NOT_EMPTY interrupt)" },
    ]
};

$registers{"mbox_int_enable"} = {
    "name" => "MBOX_INT_ENABLE",
    "description" => "MBOX Related Interrupt Enables",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x0000003C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",           "attr" => "rw", "width" => "20", "shift" => "12", "description" => "Reserved" },
        { "name" => "RX_DMA_COMPLETE",     "attr" => "rw", "width" =>  "2", "shift" => "10", "description" => "Enable per mailbox Rx DMA completion interrupts" },
        { "name" => "TX_DMA_EOM_COMPLETE", "attr" => "rw", "width" =>  "2", "shift" =>  "8", "description" => "Enable per mailbox Tx DMA completion of end message interrupts" },
        { "name" => "TX_DMA_COMPLETE",     "attr" => "rw", "width" =>  "2", "shift" =>  "6", "description" => "Enable per mailbox Tx DMA completion interrupts" },
        { "name" => "TX_OVERFLOW",         "attr" => "rw", "width" =>  "1", "shift" =>  "5", "description" => "Enable MBOX Tx overflow error" },
        { "name" => "RX_UNDERFLOW",        "attr" => "rw", "width" =>  "1", "shift" =>  "4", "description" => "Enable MBOX Rx overflow error" },
        { "name" => "TX_NOT_EMPTY",        "attr" => "rw", "width" =>  "2", "shift" =>  "2", "description" => "Enable TX_NOT_EMPTY interrupts from MBOX Tx FIFOs (Bit[0] = Enable MBOX 0 TX_NOT_EMPTY interrupt, Bit[1] = Enable MBOX 1 TX_NOT_EMPTY interrupt)" },
        { "name" => "RX_NOT_FULL",         "attr" => "rw", "width" =>  "2", "shift" =>  "0", "description" => "Enable RX_NOT_EMPTY interrupts from MBOX Rx FIFOs (Bit[0] = Enable MBOX 0 RX_NOT_EMPTY interrupt, Bit[1] = Enable MBOX 1 RX_NOT_EMPTY interrupt)" },
    ]
};

$registers{"mbox_fifo_reset"} = {
    "name" => "MBOX_FIFO_RESET",
    "description" => "Reset and Clear MBOX FIFOs",
    "offset" => "MBOX_REGISTER_OFFSET",
    "address" => ["0x00000040"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "28", "shift" => "4", "description" => "Reserved" },
        { "name" => "RX_INIT",   "attr" => "rw", "width" =>  "2", "shift" => "2", "description" => "Writing a 1 causes a Rx FIFO reset. The register is automatically reset to 0, and will always return 0 on a read. (RX_INIT[0] = Resets MBOX 0, RX_INIT[1] = Resets MBOX 1)" },
        { "name" => "TX_INIT",   "attr" => "rw", "width" =>  "2", "shift" => "0", "description" => "Writing a 1 causes a Tx FIFO reset. The register is automatically reset to 0, and will always return 0 on a read. (TX_INIT[0] = Resets MBOX 0, TX_INIT[1] = Resets MBOX 1)" },
    ]
};

$registers{"spi_func_select"} = {
    "name" => "SPI_FUNC_SELECT",
    "description" => "SPI Function Select",
    "offset" => "SPI_REGISTER_OFFSET",
    "address" => ["0x00000000"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1",       "attr" => "rw", "width" => "31", "shift" =>  "1", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "FUNCTION_SELECT", "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "Setting this bit to 0 enables SPI. Setting this bit to 1 makes the rest of the registers visible" },
    ]
};

$registers{"spi_control"} = {
    "name" => "SPI_CONTROL",
    "description" => "SPI Control",
    "offset" => "SPI_REGISTER_OFFSET",
    "address" => ["0x00000004"],
    "reset" => "0x00000008",
    "bits" => [
        { "name" => "reserved1",     "attr" => "rw", "width" => "25", "shift" => "7", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "REMAP_DISABLE", "attr" => "rw", "width" =>  "1", "shift" => "6", "description" => "Remaps 4 MB space over unless explicity disabled by setting this bit to 1. If set to 1, 16 MB is accessible." },
        { "name" => "CLOCK_DIVIDER", "attr" => "rw", "width" =>  "6", "shift" => "0", "description" => "Specifies the clock devider setting. Actual clock frequency would be (AHB_CLK/((CLOCK_DIVIDER+1)*2)). Therefore by default, if the AHB_CLK is 200 MHz, this would give 200/18 = ~ 11 MHz" },
    ]
};

$registers{"spi_io_control"} = {
    "name" => "SPI_IO_CONTROL",
    "description" => "SPI I/O Control",
    "offset" => "SPI_REGISTER_OFFSET",
    "address" => ["0x00000008"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "reserved1", "attr" => "rw", "width" => "13", "shift" => "19", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "IO_CS_2",   "attr" => "rw", "width" =>  "1", "shift" => "18", "description" => "This chip select 2 bit to be output" },
        { "name" => "IO_CS_1",   "attr" => "rw", "width" =>  "1", "shift" => "17", "description" => "This chip select 1 bit to be output" },
        { "name" => "IO_CS_0",   "attr" => "rw", "width" =>  "1", "shift" => "16", "description" => "This chip select 0 bit to be output" },
        { "name" => "IO_CLOCK",  "attr" => "rw", "width" =>  "1", "shift" =>  "8", "description" => "The clock bit to be output" },
        { "name" => "reserved2", "attr" => "rw", "width" =>  "7", "shift" =>  "1", "description" => "Reserved. Must be written with zero. Contains zeros when read." },
        { "name" => "IO_DO",     "attr" => "rw", "width" =>  "1", "shift" =>  "0", "description" => "the data bit to be output" },
    ]
};

$registers{"spi_read_data"} = {
    "name" => "SPI_READ_DATA",
    "description" => "SPI Read Data",
    "offset" => "SPI_REGISTER_OFFSET",
    "address" => ["0x0000000C"],
    "reset" => "0x00000000",
    "bits" => [
        { "name" => "READ_DATA", "attr" => "ro", "width" => "32", "shift" =>  "0", "description" => "The read data sampled in every clock" },
    ]
};


# $registers{"spi_"} = {
#     "name" => "SPI_",
#     "description" => "",
#     "offset" => "SPI_REGISTER_OFFSET",
#     "address" => ["0x00000000"],
#     "reset" => "0x00000000",
#     "bits" => [
#         { "name" => "", "attr" => "rw", "width" => "1", "shift" =>  "0", "description" => "" },
#     ]
# };
#


my $prefix = "VIRIAN_";
my $filename = "ar7242";
my $handle;

open $handle, "> " . $filename . ".h";

print $handle "#ifndef _ARCH_ASM_MACH_" . $prefix . uc($filename) . "_H_\n";
print $handle "#define _ARCH_ASM_MACH_" . $prefix . uc($filename) . "_H_\n\n";

print_offsets($handle, $prefix);

for my $i (keys %registers) {
    print "process " . $i . " ...\n";
    print $handle "\n/*------------------------------------------------------------------------------------------*\\\n";
    print $handle "      " . $registers{$i}->{description} . "\n";
    print $handle "\\*------------------------------------------------------------------------------------------*/\n";
    if(defined(@{$registers{$i}->{address}}[1])) {
        my $count = 0;
        foreach my $a (@{$registers{$i}->{address}}) {
            print $handle "#define " . $prefix . $registers{$i}->{name} . $count  . "_REGISTER\t\t" . 
                  "(" . $registers{$i}->{offset} . " + " . $a . ")\n";
            $count = $count + 1;
        }
    } else {
        print $handle "#define " . $prefix . $registers{$i}->{name} . "_REGISTER\t\t" . 
              "(" . $registers{$i}->{offset} . " + " . @{$registers{$i}->{address}}[0] . ")\n\n";
    }
    foreach my $bits ( @{$registers{$i}->{bits}} ) {
        if($bits->{name} !~ m/reserved/) {
            print $handle "#define " . $prefix . $registers{$i}->{name} . "_" . $bits->{name} . "_SHIFT" . 
                "            " . $bits->{shift} . "\n";
            print $handle "#define " . $prefix . $registers{$i}->{name} . "_" . $bits->{name} . "_MASK" . 
                "             (((1 << " . $bits->{width} . ") - 1) << " . $bits->{shift} . ")\n";
            print $handle "#define " . $prefix . $registers{$i}->{name} . "_" . $bits->{name} . "_SET_VALUE(value)" . 
                " ((((1 << " . $bits->{width} . ") - 1) & (value)) << " . $bits->{shift} . ")\n";
            print $handle "#define " . $prefix . $registers{$i}->{name} . "_" . $bits->{name} . "_GET_VALUE" . 
                "        ((((1 << " . $bits->{width} . ") - 1) & *(" . 
                "(volatile unsigned int *)" .  $prefix . $registers{$i}->{name} . "_REGISTER))" .
                " >> " . $bits->{shift} . ")\n";
        }
    }

    my $base_name = lc($prefix) . lc($registers{$i}->{name});

    print $handle "\n\ntypedef union __" . $base_name . " {\n";
    print $handle "    struct _" . $base_name . " {\n";
    foreach my $bits ( @{$registers{$i}->{bits}} ) {
        my $type = "volatile unsigned int";
        
        if($bits->{attr} eq "ro") {
            $type = "volatile const unsigned int";
        }
        print $handle "        " . $type . " " . $bits->{name} . " : " . $bits->{width} . "; ";
        if($bits->{width} == 1) {
            print $handle "/*--- Bit " . $bits->{shift};
        } else {
            print $handle "/*--- Bits " . $bits->{shift} . " ... " . ($bits->{shift} + $bits->{width} - 1);
        }
        if(defined($bits->{description})) {
            print $handle " " . $bits->{description};
        }
        print $handle " ---*/\n";
    }
    print $handle "    } Bits;\n";
    print $handle "    volatile unsigned int Register;\n";
    print $handle "} " . $base_name . "_t;\n";
}

print $handle "\n\n#endif /*--- #ifndef _ARCH_ASM_MACH_" . $prefix . uc($filename) . "_H_ ---*/\n";
close $handle;