/*
 * PROM interface routines.
 */
#include <linux/autoconf.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <asm/bootinfo.h>
#include <amazon_s.h>
#include <irq.h>
#include <emulation.h>
#include <model.h>
#include <asm/cpu.h>
#include <linux/version.h>

#ifdef CONFIG_SMP
#include <asm/smtc.h>
#include <asm/smtc_ipi.h>
extern struct plat_smp_ops msmtc_smp_ops;
#endif /*--- #ifdef CONFIG_SMP ---*/

extern void prom_printf(const char * fmt, ...);

// for Multithreading (APRP)
unsigned long physical_memsize = 1024L * 1024L * 16;

//static char fake_cmdline[21] = "console=ttyS1,115200";
/* flag to indicate whether the user put mem= in the command line */
//static int got_mem = 0;
#ifdef CONFIG_BLK_DEV_INITRD
  extern unsigned long initrd_start, initrd_end;
#endif
#ifdef CONFIG_MTD_AMAZON_S
  extern unsigned long flash_start, flash_size;
#endif

u32 *chip_cp1_base = NULL;

#if defined(CONFIG_ATM_BONDING_BM) || defined(CONFIG_USE_EMULATOR)
  #define  USE_BUILTIN_PARAMETER
#else
  #undef  USE_BUILTIN_PARAMETER
#endif

/*--- #ifndef USE_BUILTIN_PARAMETER ---*/ /*--- XXX ---*/
/*--- #define USE_BUILTIN_PARAMETER ---*/
/*--- #endif ---*/

#ifdef USE_BUILTIN_PARAMETER
/*--- #define CONFIG_IFX_ASC_CONSOLE_ASC1 ---*/ /*--- XXX ---*/
static char * chip_arg[3] =
{
    "<ignored>",
    "root=/dev/nfs rw "
    "nfsroot=192.168.178.252:/home/ar9 "
    "ip=192.168.178.1:192.168.178.252:192.168.178.252:255.255.255.0:fritz_box_benito:eth0:on "
    "console=ttyS1,115200 "
    "ethaddr=00:04:0e:ff:ff:01 "
    "phym=32M "
    "mem=32M "
    "panic=1 "
    "nowait=1 "
    "migration_debug=1",
    NULL
};
#endif //USE_BUILTIN_PARAMETER
static char * chip_env[] =
{
    /*--- "flash_start=0x10000000", ---*/
    /*--- "flash_size=0x00400000", ---*/
    "memsize=32 *1024 *1024",   /*--- HACK der halbe Speicher für die 2. CPU ---*/ 
    NULL
};

struct callvectors *debug_vectors;

u32* danube_get_cp1_base(void)
{
     return chip_cp1_base;
}
EXPORT_SYMBOL(danube_get_cp1_base);

#define DEBUG_PROM
//void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
void __init prom_init(void)
{
    int argc = fw_arg0;
    char **argv = (char **) fw_arg1;
    char **envp = (char **) fw_arg2;
    struct callvectors *cv = (struct callvectors *) fw_arg3;

    int i;
    unsigned long memsz = 0;
#ifdef CONFIG_BLK_DEV_INITRD
    unsigned long rdstart, rdsize;
    //int have_initrd = 0;
#endif
    char *scr;

    prom_printf("Infineon Amazon_S\n");
    debug_vectors = cv;
    /*--- mips_machgroup = MACH_GROUP_AMAZON_S; ---*/

#ifdef USE_BUILTIN_PARAMETER
    argv = (char **)KSEG1ADDR((unsigned long)chip_arg);
    envp = (char **)KSEG1ADDR((unsigned long)chip_env);
    argc = 2;
#else
    argv = (char **)KSEG1ADDR((unsigned long)argv);
    /*--- envp = (char **)KSEG1ADDR((unsigned long)envp); ---*/
    envp = (char **)KSEG1ADDR((unsigned long)chip_env); /*--- HACK der halbe Speicher für die 2. CPU ---*/ 
#endif
#ifdef DEBUG_PROM
    prom_printf("[%s %s %d]: argc %d, fw_arg0 %p, fw_arg1 %p, fw_arg2 %p fw_arg3 %p\n", __FILE__, __func__, __LINE__,
                argc, fw_arg0, fw_arg1, fw_arg2, fw_arg3);
#endif
    /* arg[0] is "g", the rest is boot parameters */
    arcs_cmdline[0] = '\0';
    for (i = 1; i < argc; i++) {
        argv[i] = (char *)KSEG1ADDR(argv[i]);
        if (!argv[i])
            continue;
        if (strlen(arcs_cmdline) + strlen(argv[i] + 1) >= sizeof(arcs_cmdline))
            break;
        strcat(arcs_cmdline, argv[i]);
        strcat(arcs_cmdline, " ");
    }
    if ( (scr = strstr(arcs_cmdline, "phym=")) )
    {
        scr += 5;
        memsz = 0;
        while ( *scr >= '0' && *scr <= '9' )
        {
            memsz = memsz * 10 + *scr - '0';
            scr++;
        }
        if ( *scr == 'm' || *scr == 'M' )
            memsz *= 1024 * 1024;
        else if ( *scr == 'k' || *scr == 'K' )
            memsz *= 1024;
        physical_memsize = memsz;
    }
    if ( (scr = strstr(arcs_cmdline, "mem=")) )
    {
        scr += 4;
        memsz = 0;
        while ( *scr >= '0' && *scr <= '9' )
        {
            memsz = memsz * 10 + *scr - '0';
            scr++;
        }
        if ( *scr == 'm' || *scr == 'M' )
            memsz *= 1024 * 1024;
        else if ( *scr == 'k' || *scr == 'K' )
            memsz *= 1024;
        if ( !physical_memsize )
            physical_memsize = memsz;
    }
    max_pfn = PFN_DOWN(memsz);
    printk("phym = %08lx, memsz = %08lx, max_pfn = %08lx\n", physical_memsize, memsz, max_pfn);
#ifdef DEBUG_PROM
    prom_printf("[%s %d]: arcs_cmdline - %s\n", __func__, __LINE__, arcs_cmdline);
#endif
    memsz = 0;
#ifdef CONFIG_BLK_DEV_INITRD
    rdstart = rdsize = 0;
#endif
    /* now handle envp */
    if (envp != (char **)KSEG1ADDR(0)) {
        /* assume for now that exactly 3 values get passed */
        while (*envp) {
            *envp = (char *)KSEG1ADDR(*envp);
            /* check for memsize */
            if (strncmp(*envp, "memsize=", 8) == 0) {
                scr = *envp + 8;
                memsz = (int)simple_strtoul(scr, NULL, 0);
#ifdef DEBUG_PROM
                prom_printf("[%s %s %d]: memsize=%d\n", __FILE__, __func__, __LINE__, memsz);
#endif
            }
#ifdef CONFIG_BLK_DEV_INITRD
            /* check for initrd_start */
            if (strncmp(*envp, "initrd_start=", 13) == 0) {
                scr = *envp + 13;
                rdstart = (int)simple_strtoul(scr, NULL, 0);
                rdstart = KSEG1ADDR(rdstart);
  #ifdef DEBUG_PROM
                prom_printf("initrd_start=%#x\n", (unsigned int)rdstart);
  #endif
            }
            /* check for initrd_size */
            if (strncmp(*envp, "initrd_size=", 12) == 0)
            {
                scr = *envp + 12;
                rdsize = (int)simple_strtoul(scr, NULL, 0);
  #ifdef DEBUG_PROM
                prom_printf("initrd_size=%ul\n", (unsigned int)rdsize);
  #endif
            }
#endif /* CONFIG_BLK_DEV_INITRD */

#ifdef CONFIG_MTD_AMAZON_S
            /* check for flash address and size */
            if (strncmp(*envp, "flash_start=", 12) == 0) {
                scr = *envp + 12;
                flash_start = simple_strtoul(scr, NULL, 0);
  #ifdef DEBUG_PROM
                prom_printf("flash_start=%#x\n", flash_start);
  #endif
            }
            if (strncmp(*envp, "flash_size=", 11) == 0) {
                scr = *envp + 11;
                flash_size = simple_strtoul(scr, NULL, 0);
#ifdef DEBUG_PROM
                prom_printf("flash_size=%ul\n", flash_size);
#endif
            }
#endif  /* CONFIG_MTD_AMAZON_S */
            envp++;
        }
    }

#if defined(CONFIG_DANUBE_RAM_SIZE) && (CONFIG_DANUBE_RAM_SIZE != 0)
    memsz=CONFIG_DANUBE_RAM_SIZE;
#endif
#if defined(CONFIG_DANUBE_FW_SIZE) && (CONFIG_DANUBE_FW_SIZE != 0)
    /* Store start of VCPU memory */
    memsz -= CONFIG_DANUBE_FW_SIZE;
#endif
    chip_cp1_base = (u32*)(0xA0000000 + (memsz * 1024 * 1024));
#ifdef DEBUG_PROM
    prom_printf("Reserving memory for CP1 @0x%08x\n", (u32)chip_cp1_base);
    prom_printf("memsize=%u\n", memsz);
#endif
#ifdef CONFIG_BLK_DEV_INITRD
    /* u-boot always passes a non-zero start, but a 0 size if there */
    /* is no ramdisk */
    if (rdstart != 0 && rdsize != 0)
    {
        initrd_start = rdstart;
        initrd_end = rdstart + rdsize;
    }
#endif
    /* Set the I/O base address */
    set_io_port_base(0);

    /* Set memory regions */
    ioport_resource.start = 0;      /* Should be KSEGx ???  */
    ioport_resource.end = 0xffffffff;   /* Should be ???    */

#ifdef DEBUG_PROM
    prom_printf("[%s %s %d]: finished\n", __FILE__, __func__, __LINE__);
#endif
#ifdef CONFIG_MIPS_CMP
	register_smp_ops(&cmp_smp_ops);
#endif
#ifdef CONFIG_MIPS_MT_SMP
	register_smp_ops(&vsmp_smp_ops);
#endif
#ifdef CONFIG_MIPS_MT_SMTC
	register_smp_ops(&msmtc_smp_ops);
#endif
}

void __init prom_free_prom_memory(void)
{
    return;
}

const char *get_system_type(void)
{
    return BOARD_SYSTEM_TYPE;
}