#include #include #include #define RST_REGISTER_OFFSET 0x18060000 #define MBOX_REGISTER_OFFSET 0x180A0000 #define GPIO_REGISTER_OFFSET 0x18040000 virian_rst_global_interrupt_status_t *virian_rst_global_interrupt_status = KSEG1ADDR(VIRIAN_RST_GLOBAL_INTERRUPT_STATUS_REGISTER); virian_fifo_timeout_t *virian_fifo_timeout = KSEG1ADDR( VIRIAN_FIFO_TIMEOUT_REGISTER); virian_rst_misc_interrupt_mask_t * virian_rst_misc_interrupt_mask = KSEG1ADDR( VIRIAN_RST_MISC_INTERRUPT_MASK_REGISTER); virian_rst_misc_interrupt_status_t * virian_rst_misc_interrupt_status = KSEG1ADDR( VIRIAN_RST_MISC_INTERRUPT_STATUS_REGISTER); virian_mbox_int_status_t * virian_mbox_int_status = KSEG1ADDR( VIRIAN_MBOX_INT_STATUS_REGISTER); virian_mbox_int_enable_t * virian_mbox_int_enable = KSEG1ADDR( VIRIAN_MBOX_INT_ENABLE_REGISTER ); virian_gpio_int_pending_t * virian_gpio_int_pending = KSEG1ADDR( VIRIAN_GPIO_INT_PENDING_REGISTER ); virian_gpio_int_t * virian_gpio_int = KSEG1ADDR( VIRIAN_GPIO_INT_REGISTER); virian_gpio_int_polarity_t * virian_gpio_int_polarity = KSEG1ADDR( VIRIAN_GPIO_INT_POLARITY_REGISTER);